/* rx.c --- opcode semantics for stand-alone RX simulator.
-Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
+Copyright (C) 2008-2020 Free Software Foundation, Inc.
Contributed by Red Hat, Inc.
This file is part of the GNU simulators.
#include <stdlib.h>
#include <string.h>
#include <signal.h>
+#include "libiberty.h"
#include "opcode/rx.h"
#include "cpu.h"
"RXO_nop",
"RXO_nop2",
"RXO_nop3",
+ "RXO_nop4",
+ "RXO_nop5",
+ "RXO_nop6",
+ "RXO_nop7",
"RXO_scmpu",
"RXO_smovu",
"RbRi" /* [Rb + scale * Ri] */
};
-#define N_RXO (sizeof(id_names)/sizeof(id_names[0]))
-#define N_RXT (sizeof(optype_names)/sizeof(optype_names[0]))
-#define N_MAP 30
+#define N_RXO ARRAY_SIZE (id_names)
+#define N_RXT ARRAY_SIZE (optype_names)
+#define N_MAP 90
static unsigned long long benchmark_start_cycle;
static unsigned long long benchmark_end_cycle;
put_reg (o->reg, get_reg (o->reg) - size2bytes[o->size]);
/* fall through */
case RX_Operand_Postinc: /* [Rn+] */
+ case RX_Operand_Zero_Indirect: /* [Rn + 0] */
case RX_Operand_Indirect: /* [Rn + addend] */
case RX_Operand_TwoReg: /* [Rn + scale * R2] */
#ifdef CYCLE_ACCURATE
switch (o->size)
{
+ default:
case RX_AnySize:
rx_abort ();
to the size. */
switch (o->size)
{
+ default:
case RX_AnySize:
rx_abort ();
switch (o->size)
{
+ default:
case RX_AnySize:
if (o->type != RX_Operand_Register)
rx_abort ();
put_reg (o->reg, get_reg (o->reg) - size2bytes[o->size]);
/* fall through */
case RX_Operand_Postinc: /* [Rn+] */
+ case RX_Operand_Zero_Indirect: /* [Rn + 0] */
case RX_Operand_Indirect: /* [Rn + addend] */
case RX_Operand_TwoReg: /* [Rn + scale * R2] */
switch (o->size)
{
+ default:
case RX_AnySize:
rx_abort ();
c = val & carry_mask; \
val OP 1; \
} \
- if (count) \
- set_oszc (val, 4, c); \
+ set_oszc (val, 4, c); \
PD (val); \
}
break;
case RXO_branchrel:
- if (GS())
+ if (opcode->op[1].type == RX_Operand_None || GS())
{
int delta = GD();
- regs.r_pc += delta;
+ regs.r_pc = opcode_pc + delta;
#ifdef CYCLE_ACCURATE
/* Note: specs say 3, chip says 2. */
if (delta >= 0 && delta < 16
case RXO_mov:
v = GS ();
+ if (opcode->op[1].type == RX_Operand_Register
+ && opcode->op[1].reg == 17 /* PC */)
+ {
+ /* Special case. We want the address of the insn, not the
+ address of the next insn. */
+ v = opcode_pc;
+ }
+
if (opcode->op[0].type == RX_Operand_Register
&& opcode->op[0].reg == 16 /* PSW */)
{
case RXO_nop:
case RXO_nop2:
case RXO_nop3:
+ case RXO_nop4:
+ case RXO_nop5:
+ case RXO_nop6:
+ case RXO_nop7:
E1;
break;
E1;
break;
+ case RXO_satr:
+ if (FLAG_O && ! FLAG_S)
+ {
+ put_reg (6, 0x0);
+ put_reg (5, 0x7fffffff);
+ put_reg (4, 0xffffffff);
+ }
+ else if (FLAG_O && FLAG_S)
+ {
+ put_reg (6, 0xffffffff);
+ put_reg (5, 0x80000000);
+ put_reg (4, 0x0);
+ }
+ E1;
+ break;
+
case RXO_sbb:
MATH_OP (-, ! carry);
break;