2003-06-27 Michael Snyder <msnyder@redhat.com>

[deliverable/binutils-gdb.git] / sim / sh / ChangeLog

diff --git a/sim/sh/ChangeLog b/sim/sh/ChangeLog
index d8a8f70ef4330b950970a6f1206f261cff21caec..2b6624d897333b683adc677007eef4602b922d98 100644 (file)
--- a/sim/sh/ChangeLog
+++ b/sim/sh/ChangeLog
@@ -1,3 +1,40 @@
+2003-07-03  Michael Snyder  <msnyder@redhat.com>
+
+       * gencode.c (movs): Fix a couple of text transpositions.
+
+2003-06-27  Michael Snyder  <msnyder@redhat.com>
+
+       * gencode.c (op tab): Implement movca.l.
+       * gencode.c (op movsxy_tab): Fix an error in the bit pattern.
+       * gencode.c (gensim_caselist): The movy instructions use
+       registers R6 and R7 (not R4 and R5 like the movx insns).
+
+2003-06-27  Michael Snyder  <msnyder@redhat.com>
+
+       * gencode.c (op movsxy_tab): Fix up some copy/paste errors
+       in name: s/REG_x/REG_y/.
+
+       * gencode.c (op tab): Move misplaced semicolon.
+
+2003-02-27  Andrew Cagney  <cagney@redhat.com>
+
+       * interp.c (init_dsp, sim_open, sim_create_inferior): Rename _bfd
+       to bfd.
+
+Fri Oct 11 16:22:28 2002  J"orn Rennecke <joern.rennecke@superh.com>
+
+       * interp.c (trap): Return int.  Take extra parameter for address
+       of the trap instruction.  Changed all callers.
+       Add case 33 for profiling.
+       * gencode.c (trapa): Handle trap 33 using the trap function.
+       Add read of vector for generic traps.
+
+Wed Jul 17 19:36:38 2002  J"orn Rennecke <joern.rennecke@superh.com>
+
+       * Makefile.in (interp.o): Depend on $(srcroot)/include/gdb/sim-sh.h.
+       * interp.c: Include "gdb/sim-sh.h".
+       (sim_store_register, sim_fetch_register): Use constants defined there.
+
 Tue Jun 18 16:53:11 2002  J"orn Rennecke <joern.rennecke@superh.com>
 
        * interp.c (sim_resume): Fix setting of bus error for