char *code;
char *stuff[MAX_NR_STUFF];
int index;
-}
-
-op;
+} op;
op tab[] =
"SET_SR_T (0);",
},
- { "", "", "div1 <REG_M>,<REG_N>", "0011nnnnmmmm0100",
+ { "", "nm", "div1 <REG_M>,<REG_N>", "0011nnnnmmmm0100", /* ? MVS */
"div1 (R, m, n/*, T*/);",
},
"R[n] = (R[m] & 0xffff);",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "fabs <FREG_N>", "1111nnnn01011101",
"FP_UNARY (n, fabs);",
"/* FIXME: FR(n) &= 0x7fffffff; */",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "fadd <FREG_M>,<FREG_N>", "1111nnnnmmmm0000",
"FP_OP (n, +, m);",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "fcmp/eq <FREG_M>,<FREG_N>", "1111nnnnmmmm0100",
"FP_CMP (n, ==, m);",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "fcmp/gt <FREG_M>,<FREG_N>", "1111nnnnmmmm0101",
"FP_CMP (n, >, m);",
},
"}",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "fdiv <FREG_M>,<FREG_N>", "1111nnnnmmmm0011",
"FP_OP (n, /, m);",
"/* FIXME: check for DP and (n & 1) == 0? */",
"/* FIXME: check for DP and (n & 1) == 0? */",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "fldi0 <FREG_N>", "1111nnnn10001101",
"SET_FR (n, (float)0.0);",
"/* FIXME: check for DP and (n & 1) == 0? */",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "fldi1 <FREG_N>", "1111nnnn10011101",
"SET_FR (n, (float)1.0);",
"/* FIXME: check for DP and (n & 1) == 0? */",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "flds <FREG_N>,FPUL", "1111nnnn00011101",
" union",
" {",
" FPUL = u.i;",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "float FPUL,<FREG_N>", "1111nnnn00101101",
/* sh4 */
"if (FPSCR_PR)",
"}",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "fmac <FREG_0>,<FREG_M>,<FREG_N>", "1111nnnnmmmm1110",
"SET_FR (n, FR(m) * FR(0) + FR(n));",
"/* FIXME: check for DP and (n & 1) == 0? */",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "fmov <FREG_M>,<FREG_N>", "1111nnnnmmmm1100",
/* sh4 */
"if (FPSCR_SZ) {",
" SET_FR (n, FR (m));",
"}",
},
- /* sh3e */
- { "", "", "fmov.s <FREG_M>,@<REG_N>", "1111nnnnmmmm1010",
+ /* sh2e */
+ { "", "n", "fmov.s <FREG_M>,@<REG_N>", "1111nnnnmmmm1010",
/* sh4 */
"if (FPSCR_SZ) {",
" MA (2);",
" WLAT (R[n], FI(m));",
"}",
},
- /* sh3e */
- { "", "", "fmov.s @<REG_M>,<FREG_N>", "1111nnnnmmmm1000",
+ /* sh2e */
+ { "", "m", "fmov.s @<REG_M>,<FREG_N>", "1111nnnnmmmm1000",
/* sh4 */
"if (FPSCR_SZ) {",
" MA (2);",
" SET_FI(n, RLAT(R[m]));",
"}",
},
- /* sh3e */
- { "", "", "fmov.s @<REG_M>+,<FREG_N>", "1111nnnnmmmm1001",
+ /* sh2e */
+ { "m", "m", "fmov.s @<REG_M>+,<FREG_N>", "1111nnnnmmmm1001",
/* sh4 */
"if (FPSCR_SZ) {",
" MA (2);",
" R[m] += 4;",
"}",
},
- /* sh3e */
- { "", "", "fmov.s <FREG_M>,@-<REG_N>", "1111nnnnmmmm1011",
+ /* sh2e */
+ { "n", "n", "fmov.s <FREG_M>,@-<REG_N>", "1111nnnnmmmm1011",
/* sh4 */
"if (FPSCR_SZ) {",
" MA (2);",
" WLAT (R[n], FI(m));",
"}",
},
- /* sh3e */
- { "", "", "fmov.s @(R0,<REG_M>),<FREG_N>", "1111nnnnmmmm0110",
+ /* sh2e */
+ { "", "0m", "fmov.s @(R0,<REG_M>),<FREG_N>", "1111nnnnmmmm0110",
/* sh4 */
"if (FPSCR_SZ) {",
" MA (2);",
" SET_FI(n, RLAT(R[0] + R[m]));",
"}",
},
- /* sh3e */
- { "", "", "fmov.s <FREG_M>,@(R0,<REG_N>)", "1111nnnnmmmm0111",
+ /* sh2e */
+ { "", "0n", "fmov.s <FREG_M>,@(R0,<REG_N>)", "1111nnnnmmmm0111",
/* sh4 */
"if (FPSCR_SZ) {",
" MA (2);",
/* sh4: See fmov instructions above for move to/from extended fp registers */
- /* sh3e */
+ /* sh2e */
{ "", "", "fmul <FREG_M>,<FREG_N>", "1111nnnnmmmm0010",
"FP_OP(n, *, m);",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "fneg <FREG_N>", "1111nnnn01001101",
"FP_UNARY(n, -);",
},
/* sh4 */
{ "", "", "frchg", "1111101111111101",
- "SET_FPSCR (GET_FPSCR() ^ FPSCR_MASK_FR);",
+ "if (FPSCR_PR)",
+ " RAISE_EXCEPTION (SIGILL);",
+ "else",
+ " SET_FPSCR (GET_FPSCR() ^ FPSCR_MASK_FR);",
},
/* sh4 */
"FP_UNARY(n, sqrt);",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "fsub <FREG_M>,<FREG_N>", "1111nnnnmmmm0001",
"FP_OP(n, -, m);",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "ftrc <FREG_N>, FPUL", "1111nnnn00111101",
/* sh4 */
"if (FPSCR_PR) {",
" FPUL = (int)FR(n);",
},
- /* sh3e */
+ /* sh2e */
{ "", "", "fsts FPUL,<FREG_N>", "1111nnnn00001101",
" union",
" {",
"/* FIXME: user mode */",
},
#endif
- { "", "n", "ldc.l @<REG_N>+,<CREG_M>", "0100nnnnmmmm0111",
+ { "n", "n", "ldc.l @<REG_N>+,<CREG_M>", "0100nnnnmmmm0111",
"MA (1);",
"CREG (m) = RLAT (R[n]);",
"R[n] += 4;",
"/* FIXME: user mode */",
},
- { "", "n", "ldc.l @<REG_N>+,SR", "0100nnnn00000111",
+ { "n", "n", "ldc.l @<REG_N>+,SR", "0100nnnn00000111",
"MA (1);",
"SET_SR (RLAT (R[n]));",
"R[n] += 4;",
"/* FIXME: user mode */",
},
- { "", "n", "ldc.l @<REG_N>+,MOD", "0100nnnn01010111",
+ { "n", "n", "ldc.l @<REG_N>+,MOD", "0100nnnn01010111",
"MA (1);",
"SET_MOD (RLAT (R[n]));",
"R[n] += 4;",
},
#if 0
- { "", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
+ { "n", "n", "ldc.l @<REG_N>+,DBR", "0100nnnn11110110",
"MA (1);",
"DBR = RLAT (R[n]);",
"R[n] += 4;",
{ "", "n", "lds <REG_N>,<SREG_M>", "0100nnnnssss1010",
"SREG (m) = R[n];",
},
- { "", "n", "lds.l @<REG_N>+,<SREG_M>", "0100nnnnssss0110",
+ { "n", "n", "lds.l @<REG_N>+,<SREG_M>", "0100nnnnssss0110",
"MA (1);",
"SREG (m) = RLAT(R[n]);",
"R[n] += 4;",
},
- /* sh3e / sh-dsp (lds <REG_N>,DSR) */
+ /* sh2e / sh-dsp (lds <REG_N>,DSR) */
{ "", "n", "lds <REG_N>,FPSCR", "0100nnnn01101010",
"SET_FPSCR(R[n]);",
},
- /* sh3e / sh-dsp (lds.l @<REG_N>+,DSR) */
- { "", "n", "lds.l @<REG_N>+,FPSCR", "0100nnnn01100110",
+ /* sh2e / sh-dsp (lds.l @<REG_N>+,DSR) */
+ { "n", "n", "lds.l @<REG_N>+,FPSCR", "0100nnnn01100110",
"MA (1);",
"SET_FPSCR (RLAT(R[n]));",
"R[n] += 4;",
},
{ "", "", "ldtlb", "0000000000111000",
- "/* FIXME: XXX*/ abort();",
+ "/* We don't implement cache or tlb, so this is a noop. */",
},
- { "", "nm", "mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111",
- "trap (255,R0,memory,maskl,maskw, endianw);",
+ { "nm", "nm", "mac.l @<REG_M>+,@<REG_N>+", "0000nnnnmmmm1111",
+ "trap (255, R0, PC, memory, maskl, maskw, endianw);",
"/* FIXME: mac.l support */",
},
- { "", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111",
+ { "nm", "nm", "mac.w @<REG_M>+,@<REG_N>+", "0100nnnnmmmm1111",
"macw(R0,memory,n,m,endianw);",
},
"R[n] = RSBAT (R0 + R[m]);",
"L (n);",
},
- { "n", "m", "mov.b @<REG_M>+,<REG_N>", "0110nnnnmmmm0100",
+ { "nm", "m", "mov.b @<REG_M>+,<REG_N>", "0110nnnnmmmm0100",
"MA (1);",
"R[n] = RSBAT (R[m]);",
"R[m] += 1;",
"MA (1);",
"WBAT (R[n] + R0, R[m]);",
},
- { "", "nm", "mov.b <REG_M>,@-<REG_N>", "0010nnnnmmmm0100",
+ { "n", "nm", "mov.b <REG_M>,@-<REG_N>", "0010nnnnmmmm0100",
"MA (1);",
"R[n] -= 1;",
"WBAT (R[n], R[m]);",
"MA (1);",
"WLAT (R0 + R[n], R[m]);",
},
- { "", "nm", "mov.l <REG_M>,@-<REG_N>", "0010nnnnmmmm0110",
+ { "n", "nm", "mov.l <REG_M>,@-<REG_N>", "0010nnnnmmmm0110",
"MA (1) ;",
"R[n] -= 4;",
"WLAT (R[n], R[m]);",
},
{ "0", "", "mov.w @(<disp>,GBR),R0", "11000101i8*2....",
- "MA (1)",
- ";R0 = RSWAT (i + GBR);",
+ "MA (1);",
+ "R0 = RSWAT (i + GBR);",
"L (0);",
},
{ "n", "", "mov.w @(<disp>,PC),<REG_N>", "1001nnnni8p2....",
"R0 = ((i + 4 + PH2T (PC)) & ~0x3);",
},
- { "0", "", "movca.l @R0, <REG_N>", "0000nnnn11000011",
- "/* FIXME: Not implemented */",
- "RAISE_EXCEPTION (SIGILL);",
+ { "", "n0", "movca.l R0, @<REG_N>", "0000nnnn11000011",
+ "/* We don't simulate cache, so this insn is identical to mov. */",
+ "MA (1);",
+ "WLAT (R[n], R[0]);",
},
{ "n", "", "movt <REG_N>", "0000nnnn00101001",
"R[n] = ~R[m];",
},
- { "0", "", "ocbi @<REG_N>", "0000nnnn10010011",
- "/* FIXME: Not implemented */",
- "RAISE_EXCEPTION (SIGILL);",
+ { "", "n", "ocbi @<REG_N>", "0000nnnn10010011",
+ "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop. */",
+ "/* FIXME: Cache not implemented */",
},
- { "0", "", "ocbp @<REG_N>", "0000nnnn10100011",
- "/* FIXME: Not implemented */",
- "RAISE_EXCEPTION (SIGILL);",
+ { "", "n", "ocbp @<REG_N>", "0000nnnn10100011",
+ "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop. */",
+ "/* FIXME: Cache not implemented */",
},
{ "", "n", "ocbwb @<REG_N>", "0000nnnn10110011",
- "RSBAT (R[n]); /* Take exceptions like byte load. */",
+ "RSBAT (R[n]); /* Take exceptions like byte load, otherwise noop. */",
"/* FIXME: Cache not implemented */",
},
{ "", "n", "setrc <REG_N>", "0100nnnn00010100",
"SET_RC (R[n]);",
},
- { "", "n", "setrc #<imm>", "10000010i8*1....",
+ { "", "", "setrc #<imm>", "10000010i8*1....",
/* It would be more realistic to let loop_start point to some static
memory that contains an illegal opcode and then give a bus error when
the loop is eventually encountered, but it seems not only simpler,
},
{ "", "", "sleep", "0000000000011011",
- "nip = PC;",
- "trap (0xc3, R0, memory, maskl, maskw, endianw);",
+ "nip += trap (0xc3, R0, PC, memory, maskl, maskw, endianw);",
},
{ "n", "", "stc <CREG_M>,<REG_N>", "0000nnnnmmmm0010",
},
{ "0", "", "trapa #<imm>", "11000011i8*1....",
-#if 0
- /* SH-[12] */
"long imm = 0xff & i;",
- "if (i==0xc3)",
- " PC-=2;",
- "if (i<20||i==34||i==0xc3)",
- " trap(i,R,memory,maskl,maskw,endianw);",
+ "if (i < 20 || i == 33 || i == 34 || i == 0xc3)",
+ " nip += trap (i, R, PC, memory, maskl, maskw,endianw);",
+#if 0
"else {",
+ /* SH-[12] */
" R[15]-=4;",
- " WLAT(R[15],GET_SR());",
+ " WLAT (R[15], GET_SR());",
" R[15]-=4;",
- " WLAT(R[15],PC+2);",
- " PC=RLAT(VBR+(imm<<2))-2;",
- "}",
+ " WLAT (R[15], PH2T (PC + 2));",
#else
- "if (i == 0xc3)",
- " {",
- " nip = PC;",
- " trap (i, R, memory, maskl, maskw,endianw);",
- " }",
- "else if (i < 20 || i==34 || i==0xc3)",
- " trap (i, R, memory, maskl, maskw,endianw);",
"else if (!SR_BL) {",
- " /* FIXME: TRA = (imm << 2); */",
" SSR = GET_SR();",
" SPC = PH2T (PC + 2);",
" SET_SR (GET_SR() | SR_MASK_MD | SR_MASK_BL | SR_MASK_RB);",
" /* FIXME: EXPEVT = 0x00000160; */",
- " SET_NIP (PT2H (VBR + 0x00000100));",
- "}",
#endif
+ " SET_NIP (PT2H (RLAT (VBR + (imm<<2))));",
+ "}",
},
{ "", "mn", "tst <REG_M>,<REG_N>", "0010nnnnmmmm1000",
"DSP_R (m) = RSWAT (R[n]);",
"R[n] += R[8];",
},
- { "n", "n", "<DSP_REG_M>,movs.w @-<REG_N>", "111101NNMMMM0001",
+ { "n", "n", "movs.w <DSP_REG_M>,@-<REG_N>", "111101NNMMMM0001",
"MA (1);",
"R[n] -= 2;",
"WWAT (R[n], DSP_R (m) >> 16);",
"DSP_GRD (m) = SIGN32 (DSP_R (m));",
"R[n] += R[8];",
},
- { "n", "n", "<DSP_REG_M>,movs.l @-<REG_N>", "111101NNMMMM0011",
+ { "n", "n", "movs.l <DSP_REG_M>,@-<REG_N>", "111101NNMMMM0011",
"MA (1);",
"R[n] -= 4;",
"WLAT (R[n], DSP_R (m));",
"WLAT (R[n], DSP_R (m));",
"R[n] += R[8];",
},
- { "n", "n", "<DSP_GRD_M>,movs.l @-<REG_N>", "111101NNGGGG0011",
+ { "n", "n", "movs.l <DSP_GRD_M>,@-<REG_N>", "111101NNGGGG0011",
"MA (1);",
"R[n] -= 4;",
"WLAT (R[n], SEXT (DSP_R (m)));",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;",
"iword &= 0xfd53; goto top;",
},
- { "n", "n8","movx.w @<REG_x>+REG_8,<DSP_XX>", "111100xxXX001000",
+ { "n", "n8","movx.w @<REG_x>+REG_8,<DSP_XX>", "111100xxXX001100",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
"iword &= 0xfd53; goto top;",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : 2;",
"iword &= 0xfd53; goto top;",
},
- { "n", "n8","movx.w <DSP_Aa>,@<REG_x>+REG_8","111100xxaa101000",
+ { "n", "n8","movx.w <DSP_Aa>,@<REG_x>+REG_8","111100xxaa101100",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] & 0xffff) == MOD_ME) ? MOD_DELTA : R[8];",
"iword &= 0xfd53; goto top;",
{ "", "n", "movy.w @<REG_y>,<DSP_YY>", "111100yyYY000001",
"DSP_R (m) = RSWAT (R[n]) << 16;",
},
- { "n", "n", "movy.w @<REG_x>+,<DSP_YY>", "111100yyYY000010",
+ { "n", "n", "movy.w @<REG_y>+,<DSP_YY>", "111100yyYY000010",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;",
},
- { "n", "n9","movy.w @<REG_x>+REG_9,<DSP_YY>", "111100yyYY000010",
+ { "n", "n9","movy.w @<REG_y>+REG_9,<DSP_YY>", "111100yyYY000011",
"DSP_R (m) = RSWAT (R[n]) << 16;",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
},
- { "", "n", "movy.w <DSP_Aa>,@<REG_x>", "111100yyAA010001",
+ { "", "n", "movy.w <DSP_Aa>,@<REG_y>", "111100yyAA010001",
"WWAT (R[n], DSP_R (m) >> 16);",
},
- { "n", "n", "movy.w <DSP_Aa>,@<REG_x>+", "111100yyAA010010",
+ { "n", "n", "movy.w <DSP_Aa>,@<REG_y>+", "111100yyAA010010",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : 2;",
},
- { "n", "n9", "movy.w <DSP_Aa>,@<REG_x>+REG_9", "111100yyAA010010",
+ { "n", "n9", "movy.w <DSP_Aa>,@<REG_y>+REG_9", "111100yyAA010011",
"WWAT (R[n], DSP_R (m) >> 16);",
"R[n] += ((R[n] | ~0xffff) == MOD_ME) ? MOD_DELTA : R[9];",
},
" res = Sz << i;",
"else if (i >= 128 - 16)",
" res = Sz >> 128 - i;",
- "else"
+ "else",
" {",
" RAISE_EXCEPTION (SIGILL);",
" return;",
"",
"if (i < 32)",
" {",
- " if (i == 32)"
+ " if (i == 32)",
" {",
" res = 0;",
" res_grd = Sz;",
"else if (i >= 96)",
" {",
" i = 128 - i;",
- " if (i == 32)"
+ " if (i == 32)",
" {",
" res_grd = SIGN32 (Sz_grd);",
" res = Sz_grd;",
" }",
" carry = Sz >> (i - 1) & 1;",
" }",
- "else"
+ "else",
" {",
" RAISE_EXCEPTION (SIGILL);",
" return;",
"greater_equal = 0;",
},
{ "","", "pmuls Se,Sf,Dg", "0100eeffxxyygguu",
- "res = (DSP_R (e)) >> 16 * (DSP_R (f) >> 16) * 2;",
+ "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
"if (res == 0x80000000)",
" res = 0x7fffffff;",
"DSP_R (g) = res;",
"int Sy = DSP_R (y);",
"int Sy_grd = SIGN32 (Sy);",
"",
- "res = (DSP_R (e)) >> 16 * (DSP_R (f) >> 16) * 2;",
+ "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
"if (res == 0x80000000)",
" res = 0x7fffffff;",
"DSP_R (g) = res;",
"int Sy = DSP_R (y);",
"int Sy_grd = SIGN32 (Sy);",
"",
- "res = (DSP_R (e)) >> 16 * (DSP_R (f) >> 16) * 2;",
+ "res = (DSP_R (e) >> 16) * (DSP_R (f) >> 16) * 2;",
"if (res == 0x80000000)",
" res = 0x7fffffff;",
"DSP_R (g) = res;",
"int Sx = DSP_R (x);",
"int Sx_grd = GET_DSP_GRD (x);",
"",
- "res = Sx + 0x8000;",
+ "res = (Sx + 0x8000) & 0xffff0000;",
"carry = (unsigned) res < (unsigned) Sx;",
"res_grd = Sx_grd + carry;",
"COMPUTE_OVERFLOW;",
"int Sy = DSP_R (y);",
"int Sy_grd = SIGN32 (Sy);",
"",
- "res = Sy + 0x8000;",
+ "res = (Sy + 0x8000) & 0xffff0000;",
"carry = (unsigned) res < (unsigned) Sy;",
"res_grd = Sy_grd + carry;",
"COMPUTE_OVERFLOW;",
" res = Sx << Sy;",
"else if (Sy >= 128 - 16)",
" res = Sx >> 128 - Sy;",
- "else"
+ "else",
" {",
" RAISE_EXCEPTION (SIGILL);",
" return;",
"",
"if (Sy < 32)",
" {",
- " if (Sy == 32)"
+ " if (Sy == 32)",
" {",
" res = 0;",
" res_grd = Sx;",
"else if (Sy >= 96)",
" {",
" Sy = 128 - Sy;",
- " if (Sy == 32)"
+ " if (Sy == 32)",
" {",
" res_grd = SIGN32 (Sx_grd);",
" res = Sx_grd;",
" }",
" carry = Sx >> (Sy - 1) & 1;",
" }",
- "else"
+ "else",
" {",
" RAISE_EXCEPTION (SIGILL);",
" return;",
{ "","", "(if cc) pdmsb Sx,Dz", "100111ccxx..zzzz",
"unsigned Sx = DSP_R (x);",
"int Sx_grd = GET_DSP_GRD (x);",
- "int i = 16;"
+ "int i = 16;",
"",
"if (Sx_grd < 0)",
" {",
" res = 30;",
"else",
" res = 31;",
- "do"
+ "do",
" {",
" if (Sx & ~0 << i)",
" {",
},
{ "","", "(if cc) pdmsb Sy,Dz", "101111cc..yyzzzz",
"unsigned Sy = DSP_R (y);",
- "int i;"
+ "int i;",
"",
"if (Sy < 0)",
" Sy = ~Sy;",
"Sy <<= 1;",
"res = 31;",
- "do"
+ "do",
" {",
" if (Sy & ~0 << i)",
" {",
{
switch (*s)
{
+ default:
+ fprintf (stderr, "gencode/gensim_caselist: illegal char '%c'\n",
+ *s);
+ exit (1);
+ break;
case '0':
case '1':
s += 2;
s += 2;
break;
case 'y':
- printf (" int n = ((iword >> 8) & 1) + 4;\n");
+ printf (" int n = ((iword >> 8) & 1) + 6;\n");
needn = 1;
s += 2;
break;
{
switch (s[0])
{
+ default:
+ fprintf (stderr, "gencode/expand_ppi_code: Illegal char '%c'\n",
+ s[0]);
+ exit (2);
+ break;
/* The last eight bits are disregarded for the switch table. */
case 'm':
case 'x':
break;
case 'c':
printf (" if ((((iword >> 8) ^ DSR) & 1) == 0)\n");
- printf ("\tbreak;\n");
+ printf ("\treturn;\n");
printf (" }\n");
printf (" case %d: \n", p->index + 1);
printf (" {\n");
projects / deliverable / binutils-gdb.git / blobdiff