* sim/m32r/uread16.ms: New testcase.

[deliverable/binutils-gdb.git] / sim / testsuite / ChangeLog

diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index 99e85eb8f1420d9e7f08ec1211cc029a3eeb7387..29dc2379fed2a49a2d170bd267c018d403b9928c 100644 (file)
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,3 +1,70 @@
+1998-12-14  Doug Evans  <devans@casey.cygnus.com>
+
+       * lib/sim-defs.exp (run_sim_test): New option xerror, for expected
+       errors.  Translate \n sequences in expected output to newline char.
+       (slurp_options): Make parentheses optional.
+       (sim_run): Look for board_info sim,options.
+       * sim/fr30/hello.ms: Add trailing \n to expected output.
+       * sim/m32r/hello.ms: Ditto.
+       * sim/m32r/hw-trap.ms: Ditto.
+
+       * sim/m32r/trap.cgs: Properly align trap2_handler.
+
+       * sim/m32r/uread16.ms: New testcase.
+       * sim/m32r/uread32.ms: New testcase.
+       * sim/m32r/uwrite16.ms: New testcase.
+       * sim/m32r/uwrite32.ms: New testcase.
+
+1998-12-14  Dave Brolley  <brolley@cygnus.com>
+
+       * sim/fr30/call.cgs: Test ret here as well.
+       * sim/fr30/ld.cgs: Remove bogus comment.
+       * sim/fr30/testutils.inc (save_rp,restore_rp): New macros.
+       * sim/fr30/div.ms: New testcase.
+       * sim/fr30/st.cgs: New testcase.
+       * sim/fr30/sth.cgs: New testcase.
+       * sim/fr30/stb.cgs: New testcase.
+       * sim/fr30/mov.cgs: New testcase.
+       * sim/fr30/jmp.cgs: New testcase.
+       * sim/fr30/ret.cgs: New testcase.
+       * sim/fr30/int.cgs: New testcase.
+
+Thu Dec 10 18:46:25 1998  Dave Brolley  <brolley@cygnus.com>
+
+       * sim/fr30/div0s.cgs: New testcase.
+       * sim/fr30/div0u.cgs: New testcase.
+       * sim/fr30/div1.cgs: New testcase.
+       * sim/fr30/div2.cgs: New testcase.
+       * sim/fr30/div3.cgs: New testcase.
+       * sim/fr30/div4s.cgs: New testcase.
+       * sim/fr30/testutils.inc (mvi_h_dr,set_dbits,test_dbits): New Macros.
+
+Tue Dec  8 13:16:53 1998  Dave Brolley  <brolley@cygnus.com>
+
+       * sim/fr30/testutils.inc (set_s_user): Correct Mask.
+       (set_s_system): Correct Mask.
+       * sim/fr30/ld.cgs (ld): Move previously failing test back
+       into place.
+       * sim/fr30/ldm0.cgs: New testcase.
+       * sim/fr30/ldm1.cgs: New testcase.
+       * sim/fr30/stm0.cgs: New testcase.
+       * sim/fr30/stm1.cgs: New testcase.
+
+Thu Dec  3 14:20:03 1998  Dave Brolley  <brolley@cygnus.com>
+
+       * sim/fr30/ld.cgs: Implement more loads.
+       * sim/fr30/call.cgs: New testcase.
+       * sim/fr30/testutils.inc (testr_h_dr): New macro.
+       (set_s_user,set_s_system): New macros.
+
+       * sim/fr30: New Directory.
+
+Wed Nov 18 10:50:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * common/bits-gen.c (main): Add BYTE_ORDER so that it matches
+       recent sim/common/sim-basics.h changes.
+       * common/Makefile.in: Update.
+       
 Fri Oct 30 00:37:31 1998  Felix Lee  <flee@cygnus.com>
 
        * lib/sim-defs.exp (sim_run): download target program to remote
@@ -644,12 +711,9 @@ Tue Feb 17 12:46:05 1998  Doug Evans  <devans@seba.cygnus.com>
        (arch): Define.
        (RUNTEST_FOR_TARGET): Delete.
        (RUNTEST): Fix.
-       (SCHEME,SCHEMEFLAGS,CGENDIR,CGENFLAGS): Define.
        (check): Depend on site.exp.  Run dejagnu.
        (site.exp): New target.
-       (cgen): New target.
-       * configure.in: Call AC_CHECK_PROG(SCHEME) if using cgen.
-       (arch): Define from target_cpu.
+       * configure.in (arch): Define from target_cpu.
        * configure: Regenerate.
 
 Wed Sep 17 10:21:26 1997  Andrew Cagney  <cagney@b1.cygnus.com>