/* TIc80 Simulator.
- Copyright (C) 1997 Free Software Foundation, Inc.
+ Copyright (C) 1997, 1998 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
sim_cpu_base base;
};
+#define CIA_GET(CPU) ((CPU)->cia)
+#define CIA_SET(CPU,VAL) ((CPU)->cia = (VAL))
+
#define GPR(N) ((CPU)->reg[N])
+#define GPR_SET(N, VAL) ((CPU)->reg[N] = (VAL))
#define ACC(N) ((CPU)->acc[N])
#define CR(N) ((CPU)->cr[tic80_index2cr ((N))])
#if defined(WITH_TRACE)
extern char *tic80_trace_alu3 PARAMS ((int, unsigned32, unsigned32, unsigned32));
+extern char *tic80_trace_cmp PARAMS ((int, unsigned32, unsigned32, unsigned32));
extern char *tic80_trace_alu2 PARAMS ((int, unsigned32, unsigned32));
-extern void tic80_trace_fpu3 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int,
- sim_fpu, sim_fpu, sim_fpu));
-extern void tic80_trace_fpu2 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int,
- sim_fpu, sim_fpu));
-extern void tic80_trace_fpu2i PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int,
- unsigned32, sim_fpu, sim_fpu));
+extern char *tic80_trace_shift PARAMS ((int, unsigned32, unsigned32, int, int, int, int, int));
+extern void tic80_trace_fpu3 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu *, sim_fpu *, sim_fpu *));
+extern void tic80_trace_fpu2 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu *, sim_fpu *));
+extern void tic80_trace_fpu1 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, sim_fpu *));
+extern void tic80_trace_fpu2i PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, unsigned32, sim_fpu *, sim_fpu *));
+extern void tic80_trace_fpu2cmp PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, unsigned32, sim_fpu *, sim_fpu *));
extern char *tic80_trace_nop PARAMS ((int));
extern char *tic80_trace_sink1 PARAMS ((int, unsigned32));
extern char *tic80_trace_sink2 PARAMS ((int, unsigned32, unsigned32));
extern char *tic80_trace_sink3 PARAMS ((int, unsigned32, unsigned32, unsigned32));
extern char *tic80_trace_cond_br PARAMS ((int, int, unsigned32, unsigned32));
extern char *tic80_trace_ucond_br PARAMS ((int, unsigned32));
-extern char *tic80_trace_ldst PARAMS ((int, int, int, int, unsigned32, unsigned32, unsigned32));
+extern void tic80_trace_ldst PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, int, int, int, unsigned32, unsigned32, unsigned32));
#define TRACE_ALU3(indx, result, input1, input2) \
do { \
} \
} while (0)
+#define TRACE_CMP(indx, result, input1, input2) \
+do { \
+ if (TRACE_ALU_P (CPU)) { \
+ trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
+ itable[indx].line_nr, "alu", \
+ tic80_trace_cmp (indx, result, input1, input2)); \
+ } \
+} while (0)
+
#define TRACE_ALU2(indx, result, input) \
do { \
if (TRACE_ALU_P (CPU)) { \
} \
} while (0)
-#define TRACE_FPU3(indx, result, input1, input2) \
+#define TRACE_SHIFT(indx, result, input, i, n, merge, endmask, rotate) \
+do { \
+ if (TRACE_ALU_P (CPU)) { \
+ trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
+ itable[indx].line_nr, "shift", \
+ tic80_trace_shift (indx, result, input, i, n, \
+ merge, endmask, rotate)); \
+ } \
+} while (0)
+
+#define TRACE_FPU3(result, input1, input2) \
do { \
if (TRACE_FPU_P (CPU)) { \
- tic80_trace_fpu3 (SD, CPU, cia, indx, result, input1, input2); \
+ tic80_trace_fpu3 (SD, CPU, cia, MY_INDEX, \
+ &result, &input1, &input2); \
} \
} while (0)
-#define TRACE_FPU2(indx, result, input) \
+#define TRACE_FPU2(result, input) \
do { \
if (TRACE_FPU_P (CPU)) { \
- tic80_trace_fpu2 (SD, CPU, cia, indx, result, input); \
+ tic80_trace_fpu2 (SD, CPU, cia, MY_INDEX, \
+ &result, &input); \
} \
} while (0)
-#define TRACE_FPU2I(indx, result, input1, input2) \
+#define TRACE_FPU1(result) \
do { \
if (TRACE_FPU_P (CPU)) { \
- tic80_trace_fpu2i (SD, CPU, cia, indx, result, input1, input2); \
+ tic80_trace_fpu1 (SD, CPU, cia, MY_INDEX, \
+ &result); \
+ } \
+} while (0)
+
+#define TRACE_FPU2I(result, input1, input2) \
+do { \
+ if (TRACE_FPU_P (CPU)) { \
+ tic80_trace_fpu2i (SD, CPU, cia, MY_INDEX, \
+ result, &input1, &input2); \
+ } \
+} while (0)
+
+#define TRACE_FPU2CMP(result, input1, input2) \
+do { \
+ if (TRACE_FPU_P (CPU)) { \
+ tic80_trace_fpu2cmp (SD, CPU, cia, MY_INDEX, \
+ result, &input1, &input2); \
} \
} while (0)
#define TRACE_UCOND_BR(indx, target) \
do { \
- if (TRACE_ALU_P (CPU)) { \
+ if (TRACE_BRANCH_P (CPU)) { \
trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
itable[indx].line_nr, "branch", \
tic80_trace_ucond_br (indx, target)); \
} \
} while (0)
-#define TRACE_LD(indx, result, m, s, addr1, addr2) \
+#define TRACE_LD(result, m, s, addr1, addr2) \
do { \
if (TRACE_MEMORY_P (CPU)) { \
- trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
- itable[indx].line_nr, "memory", \
- tic80_trace_ldst (indx, 0, m, s, result, \
- addr1, addr2)); \
+ tic80_trace_ldst (SD, CPU, cia, MY_INDEX, \
+ 0, m, s, result, addr1, addr2); \
} \
} while (0)
-#define TRACE_ST(indx, value, m, s, addr1, addr2) \
+#define TRACE_ST(value, m, s, addr1, addr2) \
do { \
if (TRACE_MEMORY_P (CPU)) { \
- trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \
- itable[indx].line_nr, "memory", \
- tic80_trace_ldst (indx, 1, m, s, value, \
- addr1, addr2)); \
+ tic80_trace_ldst (SD, CPU, cia, MY_INDEX, \
+ 1, m, s, value, addr1, addr2); \
} \
} while (0)
#else
#define TRACE_ALU3(indx, result, input1, input2)
#define TRACE_ALU2(indx, result, input)
+#define TRACE_FPU3(result, input1, input2)
+#define TRACE_FPU2(result, input)
+#define TRACE_FPU1(result)
+#define TRACE_FPU2I(result, input1, input2)
#define TRACE_NOP(indx)
#define TRACE_SINK1(indx, input)
#define TRACE_SINK2(indx, input1, input2)
#define TRACE_SINK3(indx, input1, input2, input3)
#define TRACE_COND_BR(indx, jump_p, cond, target)
#define TRACE_UCOND_BR(indx, target)
-#define TRACE_LD(indx, m, s, result, addr1, addr2)
-#define TRACE_ST(indx, m, s, value, addr1, addr2)
+#define TRACE_LD(m, s, result, addr1, addr2)
+#define TRACE_ST(m, s, value, addr1, addr2)
#endif