#include <unistd.h>
#endif
+#ifdef HAVE_STRING_H
+#include <string.h>
+#else
+#ifdef HAVE_STRINGS_H
+#include <strings.h>
+#endif
+#endif
+
+
+
+
+
/* FIXME - should be including a version of syscall.h that does not
pollute the name space */
#include "../../libgloss/v850/sys/syscall.h"
#ifdef DEBUG
static void trace_input PARAMS ((char *name, enum op_types type, int size));
static void trace_output PARAMS ((enum op_types result));
-static int init_text_p = 0;
-static asection *text;
-static bfd_vma text_start;
-static bfd_vma text_end;
-extern bfd *prog_bfd;
#ifndef SIZE_INSTRUCTION
#define SIZE_INSTRUCTION 6
char *p;
uint32 values[3];
int num_values, i;
- char *cond;
- asection *s;
const char *filename;
const char *functionname;
unsigned int linenumber;
- if ((v850_debug & DEBUG_TRACE) == 0)
+ if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
return;
buf[0] = '\0';
- if (!init_text_p)
- {
- init_text_p = 1;
- for (s = prog_bfd->sections; s; s = s->next)
- if (strcmp (bfd_get_section_name (prog_bfd, s), ".text") == 0)
- {
- text = s;
- text_start = bfd_get_section_vma (prog_bfd, s);
- text_end = text_start + bfd_section_size (prog_bfd, s);
- break;
- }
- }
- if (text && PC >= text_start && PC < text_end)
+ if (STATE_TEXT_SECTION (simulator)
+ && PC >= STATE_TEXT_START (simulator)
+ && PC < STATE_TEXT_END (simulator))
{
filename = (const char *)0;
functionname = (const char *)0;
linenumber = 0;
- if (bfd_find_nearest_line (prog_bfd, text, (struct symbol_cache_entry **)0, PC - text_start,
+ if (bfd_find_nearest_line (STATE_PROG_BFD (simulator),
+ STATE_TEXT_SECTION (simulator),
+ (struct symbol_cache_entry **)0,
+ PC - STATE_TEXT_START (simulator),
&filename, &functionname, &linenumber))
{
p = buf;
}
}
- (*v850_callback->printf_filtered) (v850_callback, "0x%.8x: %-*.*s %-*s",
- (unsigned)PC,
- SIZE_LOCATION, SIZE_LOCATION, buf,
- SIZE_INSTRUCTION, name);
+ trace_printf (simulator, STATE_CPU (simulator, 0),
+ "0x%.8x: %-*.*s %-*s",
+ (unsigned)PC,
+ SIZE_LOCATION, SIZE_LOCATION, buf,
+ SIZE_INSTRUCTION, name);
+#if 0
switch (type)
{
default:
break;
case OP_TRAP:
- sprintf (buf, "%d", OP[0]);
+ sprintf (buf, "%ld", OP[0]);
break;
case OP_REG:
- sprintf (buf, "r%d", OP[0]);
+ sprintf (buf, "r%ld", OP[0]);
break;
case OP_REG_REG:
case OP_REG_REG_CMP:
case OP_REG_REG_MOVE:
- sprintf (buf, "r%d,r%d", OP[0], OP[1]);
+ sprintf (buf, "r%ld,r%ld", OP[0], OP[1]);
break;
case OP_IMM_REG:
case OP_IMM_REG_CMP:
case OP_IMM_REG_MOVE:
- sprintf (buf, "%d,r%d", OP[0], OP[1]);
+ sprintf (buf, "%ld,r%ld", OP[0], OP[1]);
break;
case OP_COND_BR:
- sprintf (buf, "%d", SEXT9 (OP[0]));
+ sprintf (buf, "%ld", SEXT9 (OP[0]));
break;
case OP_LOAD16:
- sprintf (buf, "%d[r30],r%d", OP[1] * size, OP[0]);
+ sprintf (buf, "%ld[r30],r%ld", OP[1] * size, OP[0]);
break;
case OP_STORE16:
- sprintf (buf, "r%d,%d[r30]", OP[0], OP[1] * size);
+ sprintf (buf, "r%ld,%ld[r30]", OP[0], OP[1] * size);
break;
case OP_LOAD32:
- sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
+ sprintf (buf, "%ld[r%ld],r%ld", EXTEND16 (OP[2]) & ~0x1, OP[0], OP[1]);
break;
case OP_STORE32:
- sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
+ sprintf (buf, "r%ld,%ld[r%ld]", OP[1], EXTEND16 (OP[2] & ~0x1), OP[0]);
break;
case OP_JUMP:
- sprintf (buf, "%d,r%d", SEXT22 (OP[0]), OP[1]);
+ sprintf (buf, "%ld,r%ld", SEXT22 (OP[0]), OP[1]);
break;
case OP_IMM_REG_REG:
- sprintf (buf, "%d,r%d,r%d", SEXT16 (OP[0]), OP[1], OP[2]);
+ sprintf (buf, "%ld,r%ld,r%ld", EXTEND16 (OP[0]), OP[1], OP[2]);
break;
case OP_UIMM_REG_REG:
- sprintf (buf, "%d,r%d,r%d", OP[0] & 0xffff, OP[1], OP[2]);
+ sprintf (buf, "%ld,r%ld,r%ld", OP[0] & 0xffff, OP[1], OP[2]);
break;
case OP_BIT:
- sprintf (buf, "%d,%d[r%d]", OP[1] & 0x7, SEXT16 (OP[2]), OP[0]);
+ sprintf (buf, "%ld,%ld[r%ld]", OP[1] & 0x7, EXTEND16 (OP[2]), OP[0]);
break;
case OP_EX1:
- switch (OP[0] & 0xf)
- {
- default: cond = "?"; break;
- case 0x0: cond = "v"; break;
- case 0x1: cond = "c"; break;
- case 0x2: cond = "z"; break;
- case 0x3: cond = "nh"; break;
- case 0x4: cond = "s"; break;
- case 0x5: cond = "t"; break;
- case 0x6: cond = "lt"; break;
- case 0x7: cond = "le"; break;
- case 0x8: cond = "nv"; break;
- case 0x9: cond = "nc"; break;
- case 0xa: cond = "nz"; break;
- case 0xb: cond = "h"; break;
- case 0xc: cond = "ns"; break;
- case 0xd: cond = "sa"; break;
- case 0xe: cond = "ge"; break;
- case 0xf: cond = "gt"; break;
- }
-
- sprintf (buf, "%s,r%d", cond, OP[1]);
- break;
+ {
+ char *cond;
+ switch (OP[0] & 0xf)
+ {
+ default: cond = "?"; break;
+ case 0x0: cond = "v"; break;
+ case 0x1: cond = "c"; break;
+ case 0x2: cond = "z"; break;
+ case 0x3: cond = "nh"; break;
+ case 0x4: cond = "s"; break;
+ case 0x5: cond = "t"; break;
+ case 0x6: cond = "lt"; break;
+ case 0x7: cond = "le"; break;
+ case 0x8: cond = "nv"; break;
+ case 0x9: cond = "nc"; break;
+ case 0xa: cond = "nz"; break;
+ case 0xb: cond = "h"; break;
+ case 0xc: cond = "ns"; break;
+ case 0xd: cond = "sa"; break;
+ case 0xe: cond = "ge"; break;
+ case 0xf: cond = "gt"; break;
+ }
+ sprintf (buf, "%s,r%ld", cond, OP[1]);
+ break;
+ }
case OP_EX2:
strcpy (buf, "EX2");
case OP_LDSR:
case OP_STSR:
- sprintf (buf, "r%d,s%d", OP[0], OP[1]);
+ sprintf (buf, "r%ld,s%ld", OP[0], OP[1]);
break;
case OP_PUSHPOP1:
for (i = 0; i < 12; i++)
if (OP[3] & (1 << type1_regs[i]))
- strcat (buf, "r%d ", i + 20);
+ sprintf (strchr (buf, 0), "r%d ", i + 20);
break;
case OP_PUSHPOP2:
for (i = 0; i < 16; i++)
if (OP[3] & (1 << type2_regs[i]))
- strcat (buf, "r%d ", i + 16);
+ sprintf (strchr (buf, 0), "r%d ", i + 16);
if (OP[3] & (1 << 19))
strcat (buf, "F/EIPC, F/EIPSW " );
break;
case OP_PUSHPOP3:
for (i = 0; i < 15; i++)
if (OP[3] & (1 << type3_regs[i]))
- strcat (buf, "r%d ", i + 1);
+ sprintf (strchr (buf, 0), "r%d ", i + 1);
if (OP[3] & (1 << 3))
strcat (buf, "PSW " );
if (OP[3] & (1 << 19))
break;
case OP_BIT_CHANGE:
- sprintf (buf, "r%d, [r%d]", OP[1], OP[0] );
+ sprintf (buf, "r%ld, [r%ld]", OP[1], OP[0] );
break;
}
+#endif
- if ((v850_debug & DEBUG_VALUES) == 0)
+ if (!TRACE_ALU_P (STATE_CPU (simulator, 0)))
{
- (*v850_callback->printf_filtered) (v850_callback, "%s\n", buf);
+ trace_printf (simulator, STATE_CPU (simulator, 0),
+ "%s\n", buf);
}
else
{
- (*v850_callback->printf_filtered) (v850_callback, "%-*s", SIZE_OPERANDS, buf);
+#if 0
+ trace_printf (simulator, STATE_CPU (simulator, 0),
+ "%-*s", SIZE_OPERANDS, buf);
+#endif
switch (type)
{
default:
break;
case OP_LOAD32:
- values[0] = SEXT16 (OP[2]);
+ values[0] = EXTEND16 (OP[2]);
values[1] = State.regs[OP[0]];
num_values = 2;
break;
case OP_STORE32:
values[0] = State.regs[OP[1]];
- values[1] = SEXT16 (OP[2]);
+ values[1] = EXTEND16 (OP[2]);
values[2] = State.regs[OP[0]];
num_values = 3;
break;
break;
case OP_IMM_REG_REG:
- values[0] = SEXT16 (OP[0]) << size;
+ values[0] = EXTEND16 (OP[0]) << size;
values[1] = State.regs[OP[1]];
num_values = 2;
break;
}
for (i = 0; i < num_values; i++)
- (*v850_callback->printf_filtered) (v850_callback, "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
+ trace_printf (simulator, STATE_CPU (simulator, 0),
+ "%*s0x%.8lx", SIZE_VALUES - 10, "", values[i]);
while (i++ < 3)
- (*v850_callback->printf_filtered) (v850_callback, "%*s", SIZE_VALUES, "");
+ trace_printf (simulator, STATE_CPU (simulator, 0),
+ "%*s", SIZE_VALUES, "");
}
}
trace_output (result)
enum op_types result;
{
- if ((v850_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES))
+ if (TRACE_ALU_P (STATE_CPU (simulator, 0)))
{
switch (result)
{
case OP_LOAD16:
case OP_STSR:
- (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
- (unsigned long)State.regs[OP[0]]);
+ trace_printf (simulator, STATE_CPU (simulator, 0),
+ " :: 0x%.8lx", (unsigned long)State.regs[OP[0]]);
break;
case OP_REG_REG:
case OP_IMM_REG_MOVE:
case OP_LOAD32:
case OP_EX1:
- (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
- (unsigned long)State.regs[OP[1]]);
+ trace_printf (simulator, STATE_CPU (simulator, 0),
+ " :: 0x%.8lx", (unsigned long)State.regs[OP[1]]);
break;
case OP_IMM_REG_REG:
case OP_UIMM_REG_REG:
- (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
- (unsigned long)State.regs[OP[2]]);
+ trace_printf (simulator, STATE_CPU (simulator, 0),
+ " :: 0x%.8lx", (unsigned long)State.regs[OP[2]]);
break;
case OP_JUMP:
if (OP[1] != 0)
- (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
- (unsigned long)State.regs[OP[1]]);
+ trace_printf (simulator, STATE_CPU (simulator, 0),
+ " :: 0x%.8lx", (unsigned long)State.regs[OP[1]]);
break;
case OP_LDSR:
- (*v850_callback->printf_filtered) (v850_callback, " :: 0x%.8lx",
- (unsigned long)State.sregs[OP[1]]);
+ trace_printf (simulator, STATE_CPU (simulator, 0),
+ " :: 0x%.8lx", (unsigned long)State.sregs[OP[1]]);
break;
}
- (*v850_callback->printf_filtered) (v850_callback, "\n");
+ trace_printf (simulator, STATE_CPU (simulator, 0),
+ "\n");
}
}
#define trace_input(NAME, IN1, IN2)
#define trace_output(RESULT)
-//#define trace_input(NAME, IN1, IN2) fprintf (stderr, NAME "\n" );
+/* #define trace_input(NAME, IN1, IN2) fprintf (stderr, NAME "\n" ); */
#endif
/* end-sanitize-v850eq */
trace_input ("sld.b", OP_LOAD16, 1);
- State.regs[ OP[1] ] = SEXT8 (result);
+ State.regs[ OP[1] ] = EXTEND8 (result);
/* start-sanitize-v850eq */
#endif
/* end-sanitize-v850eq */
/* end-sanitize-v850eq */
trace_input ("sld.h", OP_LOAD16, 2);
- State.regs[ OP[1] ] = SEXT16 (result);
+ State.regs[ OP[1] ] = EXTEND16 (result);
/* start-sanitize-v850eq */
#endif
/* end-sanitize-v850eq */
trace_input ("ld.b", OP_LOAD32, 1);
- adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
+ adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
- State.regs[ OP[1] ] = SEXT8 (load_mem (adr, 1));
+ State.regs[ OP[1] ] = EXTEND8 (load_mem (adr, 1));
trace_output (OP_LOAD32);
trace_input ("ld.h", OP_LOAD32, 2);
- adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
+ adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
adr &= ~0x1;
- State.regs[ OP[1] ] = SEXT16 (load_mem (adr, 2));
+ State.regs[ OP[1] ] = EXTEND16 (load_mem (adr, 2));
trace_output (OP_LOAD32);
trace_input ("ld.w", OP_LOAD32, 4);
- adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
+ adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
adr &= ~0x3;
State.regs[ OP[1] ] = load_mem (adr, 4);
{
trace_input ("st.b", OP_STORE32, 1);
- store_mem (State.regs[ OP[0] ] + SEXT16 (OP[2]), 1, State.regs[ OP[1] ]);
+ store_mem (State.regs[ OP[0] ] + EXTEND16 (OP[2]), 1, State.regs[ OP[1] ]);
trace_output (OP_STORE32);
trace_input ("st.h", OP_STORE32, 2);
- adr = State.regs[ OP[0] ] + SEXT16 (OP[2]);
+ adr = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
adr &= ~1;
store_mem (adr, 2, State.regs[ OP[1] ]);
trace_input ("st.w", OP_STORE32, 4);
- adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
+ adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
adr &= ~3;
store_mem (adr, 4, State.regs[ OP[1] ]);
#ifdef ARCH_v850eq
trace_input ("sld.b", OP_LOAD16, 1);
- State.regs[ OP[1] ] = SEXT8 (result);
+ State.regs[ OP[1] ] = EXTEND8 (result);
#else
/* end-sanitize-v850eq */
trace_input ("sld.bu", OP_LOAD16, 1);
/* Compute the result. */
- op0 = SEXT16 (OP[2]);
+ op0 = EXTEND16 (OP[2]);
op1 = State.regs[ OP[0] ];
result = op0 + op1;
{
trace_input ("sxh", OP_REG, 0);
- State.regs[ OP[0] ] = SEXT16 (State.regs[ OP[0] ]);
+ State.regs[ OP[0] ] = EXTEND16 (State.regs[ OP[0] ]);
trace_output (OP_REG);
}
{
trace_input ("mulh", OP_REG_REG, 0);
- State.regs[ OP[1] ] = (SEXT16 (State.regs[ OP[1] ]) * SEXT16 (State.regs[ OP[0] ]));
+ State.regs[ OP[1] ] = (EXTEND16 (State.regs[ OP[1] ]) * EXTEND16 (State.regs[ OP[0] ]));
trace_output (OP_REG_REG);
}
{
trace_input ("mulh", OP_IMM_REG, 0);
- State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
+ State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[1] ]) * SEXT5 (OP[0]);
trace_output (OP_IMM_REG);
{
trace_input ("mulhi", OP_IMM_REG_REG, 0);
- State.regs[ OP[1] ] = SEXT16 (State.regs[ OP[0] ]) * SEXT16 (OP[2]);
+ State.regs[ OP[1] ] = EXTEND16 (State.regs[ OP[0] ]) * EXTEND16 (OP[2]);
trace_output (OP_IMM_REG_REG);
}
trace_input ("switch", OP_REG, 0);
adr = State.pc + 2 + (State.regs[ OP[0] ] << 1);
- State.pc = State.pc + 2 + (SEXT16 (load_mem (adr, 2)) << 1);
+ State.pc = State.pc + 2 + (EXTEND16 (load_mem (adr, 2)) << 1);
trace_output (OP_REG);
}
trace_input ("divh", OP_REG_REG, 0);
/* Compute the result. */
- temp = SEXT16 (State.regs[ OP[0] ]);
+ temp = EXTEND16 (State.regs[ OP[0] ]);
op0 = temp;
op1 = State.regs[OP[1]];
{
trace_input ("sxb", OP_REG, 0);
- State.regs[ OP[0] ] = SEXT8 (State.regs[ OP[0] ]);
+ State.regs[ OP[0] ] = EXTEND8 (State.regs[ OP[0] ]);
trace_output (OP_REG);
}
trace_input ("satsubi", OP_IMM_REG, 0);
/* Compute the result. */
- temp = SEXT16 (OP[2]);
+ temp = EXTEND16 (OP[2]);
op0 = temp;
op1 = State.regs[ OP[0] ];
result = op1 - op0;
/* start-sanitize-v850e */
if (OP[1] == 0)
{
- trace_input ("mov", OP_IMM32_REG, 4);
+ trace_input ("mov", OP_IMM_REG, 4);
State.regs[ OP[0] ] = load_mem (PC + 2, 4);
- trace_output (OP_IMM32_REG);
+ trace_output (OP_IMM_REG);
return 6;
}
{
trace_input ("movea", OP_IMM_REG_REG, 0);
- State.regs[ OP[1] ] = State.regs[ OP[0] ] + SEXT16 (OP[2]);
+ State.regs[ OP[1] ] = State.regs[ OP[0] ] + EXTEND16 (OP[2]);
trace_output (OP_IMM_REG_REG);
trace_input ("set1", OP_BIT, 0);
op0 = State.regs[ OP[0] ];
op1 = OP[1] & 0x7;
- temp = SEXT16 (OP[2]);
+ temp = EXTEND16 (OP[2]);
op2 = temp;
temp = load_mem (op0 + op2, 1);
PSW &= ~PSW_Z;
trace_input ("not1", OP_BIT, 0);
op0 = State.regs[ OP[0] ];
op1 = OP[1] & 0x7;
- temp = SEXT16 (OP[2]);
+ temp = EXTEND16 (OP[2]);
op2 = temp;
temp = load_mem (op0 + op2, 1);
PSW &= ~PSW_Z;
trace_input ("clr1", OP_BIT, 0);
op0 = State.regs[ OP[0] ];
op1 = OP[1] & 0x7;
- temp = SEXT16 (OP[2]);
+ temp = EXTEND16 (OP[2]);
op2 = temp;
temp = load_mem (op0 + op2, 1);
PSW &= ~PSW_Z;
trace_input ("tst1", OP_BIT, 0);
op0 = State.regs[ OP[0] ];
op1 = OP[1] & 0x7;
- temp = SEXT16 (OP[2]);
+ temp = EXTEND16 (OP[2]);
op2 = temp;
temp = load_mem (op0 + op2, 1);
PSW &= ~PSW_Z;
int
OP_FFFF ()
{
- State.exception = SIGTRAP;
- return -4;
+ sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
+ sim_stopped, SIGTRAP);
+ return 0;
}
/* di */
{
trace_input ("halt", OP_NONE, 0);
/* FIXME this should put processor into a mode where NMI still handled */
- State.exception = SIGQUIT;
trace_output (OP_NONE);
-
- return 4;
+ sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
+ sim_stopped, SIGTRAP);
+ return 0;
}
/* reti */
#ifdef SYS_exit
case SYS_exit:
if ((PARM1 & 0xffff0000) == 0xdead0000 && (PARM1 & 0xffff) != 0)
- State.exception = PARM1 & 0xffff; /* get signal encoded by kill */
+ /* get signal encoded by kill */
+ sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
+ sim_signalled, PARM1 & 0xffff);
else if (PARM1 == 0xdead)
- State.exception = SIGABRT; /* old libraries */
+ /* old libraries */
+ sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
+ sim_exited, SIGABRT);
else
- State.exception = SIG_V850_EXIT; /* PARM1 has exit status encoded */
+ /* PARM1 has exit status */
+ sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
+ sim_exited, PARM1);
break;
#endif
{
int temp;
- trace_input ("tst1", OP_BIT_LOAD, 1);
+ trace_input ("tst1", OP_BIT, 1);
temp = load_mem (State.regs[ OP[0] ], 1);
if ((temp & (1 << State.regs[ OP[1] & 0x7 ])) == 0)
PSW |= PSW_Z;
- trace_output (OP_BIT_LOAD);
+ trace_output (OP_BIT);
return 4;
}
imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
- divide_by = SEXT16 (State.regs[ OP[0] ]);
+ divide_by = EXTEND16 (State.regs[ OP[0] ]);
divide_this = State.regs[ OP[1] ] << imm5;
divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
/* Compute the result. */
divide_by = State.regs[ OP[0] ];
- divide_this = SEXT16 (State.regs[ OP[1] ]);
+ divide_this = EXTEND16 (State.regs[ OP[1] ]);
if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
{
imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
- divide_by = SEXT16 (State.regs[ OP[0] ]);
+ divide_by = EXTEND16 (State.regs[ OP[0] ]);
divide_this = State.regs[ OP[1] ];
divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
trace_input ("ld.hu", OP_LOAD32, 2);
- adr = State.regs[ OP[0] ] + SEXT16 (OP[2] & ~1);
+ adr = State.regs[ OP[0] ] + EXTEND16 (OP[2] & ~1);
adr &= ~0x1;
State.regs[ OP[1] ] = load_mem (adr, 2);
trace_input ("ld.bu", OP_LOAD32, 1);
adr = (State.regs[ OP[0] ]
- + (SEXT16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
+ + (EXTEND16 (OP[2] & ~1) | ((OP[3] >> 5) & 1)));
State.regs[ OP[1] ] = load_mem (adr, 1);
SP -= (OP[3] & 0x3e) << 1;
- EP = SEXT16 (load_mem (PC + 4, 2));
+ EP = EXTEND16 (load_mem (PC + 4, 2));
trace_output (OP_PUSHPOP1);
#ifdef ARCH_v850eq
trace_input ("sld.h", OP_LOAD16, 2);
- State.regs[ OP[1] ] = SEXT16 (result);
+ State.regs[ OP[1] ] = EXTEND16 (result);
#else
/* end-sanitize-v850eq */
trace_input ("sld.hu", OP_LOAD16, 2);
projects / deliverable / binutils-gdb.git / blobdiff