*v850e3v5
"cvtf.dl r<reg2e>, r<reg3e>"
{
- unsigned64 ans;
+ signed64 ans;
sim_fpu wop;
sim_fpu_status status;
*v850e3v5
"cvtf.dw r<reg2e>, r<reg3>"
{
- uint32 ans;
+ int32 ans;
sim_fpu wop;
sim_fpu_status status;
*v850e3v5
"cvtf.sw r<reg2>, r<reg3>"
{
- uint32 ans;
+ int32 ans;
sim_fpu wop;
sim_fpu_status status;
*v850e3v5
"trncf.dul r<reg2e>, r<reg3e>"
{
- signed64 ans;
+ unsigned64 ans;
sim_fpu wop;
sim_fpu_status status;
*v850e3v5
"trncf.dw r<reg2e>, r<reg3>"
{
- uint32 ans;
+ int32 ans;
sim_fpu wop;
sim_fpu_status status;
*v850e3v5
"trncf.sul r<reg2>, r<reg3e>"
{
- signed64 ans;
+ unsigned64 ans;
sim_fpu wop;
sim_fpu_status status;
*v850e3v5
"trncf.sw r<reg2>, r<reg3>"
{
- uint32 ans;
+ int32 ans;
sim_fpu wop;
sim_fpu_status status;