-:option::insn-bit-size:16
-:option::hi-bit-nr:15
+:option:::insn-bit-size:16
+:option:::hi-bit-nr:15
-:option::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
-# start-sanitize-v850e
-:option::format-names:XI,XII,XIII
-# end-sanitize-v850e
-# start-sanitize-v850eq
-:option::format-names:XIV,XV
-# end-sanitize-v850eq
-:option::format-names:Z
+:option:::format-names:I,II,III,IV,V,VI,VII,VIII,IX,X
+:option:::format-names:XI,XII,XIII
+:option:::format-names:XIV,XV
+:option:::format-names:Z
-:model::v850:v850:
+:model:::v850:v850:
-# start-sanitize-v850e
-:option::multi-sim:true
-:model::v850e:v850e:
-# end-sanitize-v850e
+:option:::multi-sim:true
+:model:::v850e:v850e:
+:option:::multi-sim:true
+:model:::v850e1:v850e1:
-# start-sanitize-v850eq
-:option::multi-sim:true
-:model::v850eq:v850eq:
-# end-sanitize-v850eq
+// Cache macros
+:cache:::unsigned:reg1:RRRRR:(RRRRR)
+:cache:::unsigned:reg2:rrrrr:(rrrrr)
+:cache:::unsigned:reg3:wwwww:(wwwww)
+:cache:::unsigned:disp4:dddd:(dddd)
+:cache:::unsigned:disp5:dddd:(dddd << 1)
+:cache:::unsigned:disp7:ddddddd:ddddddd
+:cache:::unsigned:disp8:ddddddd:(ddddddd << 1)
+:cache:::unsigned:disp8:dddddd:(dddddd << 2)
+:cache:::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
+:cache:::unsigned:disp16:dddddddddddddddd:EXTEND16 (dddddddddddddddd)
+:cache:::unsigned:disp16:ddddddddddddddd: EXTEND16 (ddddddddddddddd << 1)
+:cache:::unsigned:disp22:dddddd,ddddddddddddddd: SEXT32 ((dddddd << 16) + (ddddddddddddddd << 1), 22 - 1)
-// Cache macros
+:cache:::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
+:cache:::unsigned:imm6:iiiiii:iiiiii
+:cache:::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
+:cache:::unsigned:imm5:iiii:(32 - (iiii << 1))
+:cache:::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
+:cache:::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
+:cache:::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
+:cache:::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
+
+:cache:::unsigned:vector:iiiii:iiiii
-:cache::unsigned:reg1:RRRRR:(RRRRR)
-:cache::unsigned:reg2:rrrrr:(rrrrr)
-:cache::unsigned:reg3:wwwww:(wwwww)
-
-:cache::unsigned:disp4:dddd:(dddd)
-# start-sanitize-v850e
-:cache::unsigned:disp5:dddd:(dddd << 1)
-# end-sanitize-v850e
-:cache::unsigned:disp7:ddddddd:ddddddd
-:cache::unsigned:disp8:ddddddd:(ddddddd << 1)
-:cache::unsigned:disp8:dddddd:(dddddd << 2)
-:cache::unsigned:disp9:ddddd,ddd:SEXT32 ((ddddd << 4) + (ddd << 1), 9 - 1)
-:cache::unsigned:disp16:dddddddddddddddd:SEXT32 (dddddddddddddddd, 16 - 1)
-:cache::unsigned:disp16:ddddddddddddddd:SEXT32 (ddddddddddddddd << 1, 16 - 1)
-:cache::unsigned:disp22:dddddd,dddddddddddddddd:SEXT32 ((dddddd << 16) + (dddddddddddddddd << 1), 22 - 1)
-:cache::unsigned:disp22:dddddd,ddddddddddddddd:SEXT32 ((dddddd << 16) + (ddddddddddddddd << 2), 22 - 1)
-
-:cache::unsigned:imm5:iiiii:SEXT32 (iiiii, 4)
-:cache::unsigned:imm6:iiiiii:iiiiii
-:cache::unsigned:imm9:iiiii,IIII:SEXT ((IIII << 5) + iiiii, 9 - 1)
-# start-sanitize-v850eq
-:cache::unsigned:imm5:iiii:(32 - (iiii << 1))
-# end-sanitize-v850eq
-:cache::unsigned:simm16:iiiiiiiiiiiiiiii:EXTEND16 (iiiiiiiiiiiiiiii)
-:cache::unsigned:uimm16:iiiiiiiiiiiiiiii:iiiiiiiiiiiiiiii
-:cache::unsigned:imm32:iiiiiiiiiiiiiiii,IIIIIIIIIIIIIIII:(iiiiiiiiiiiiiiii < 16 + IIIIIIIIIIIIIIII)
-# start-sanitize-v850e
-:cache::unsigned:uimm32:iiiiiiiiiiiiiiii,dddddddddddddddd:((iiiiiiiiiiiiiiii << 16) + dddddddddddddddd)
-# end-sanitize-v850e
-
-:cache::unsigned:vector:iiiii:iiiii
-
-# start-sanitize-v850e
-:cache::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
-:cache::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
-# end-sanitize-v850e
-
-:cache::unsigned:bit3:bbb:bbb
+:cache:::unsigned:list12:L,LLLLLLLLLLL:((L << 11) + LLLLLLLLLLL)
+:cache:::unsigned:list18:LLLL,LLLLLLLLLLLL:((LLLL << 12) + LLLLLLLLLLLL)
+
+:cache:::unsigned:bit3:bbb:bbb
// What do we do with an illegal instruction?
-:internal:::illegal
+:internal::::illegal:
{
sim_io_eprintf (SD, "Illegal instruction at address 0x%lx\n",
(unsigned long) cia);
- sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIGILL);
+ sim_engine_halt (SD, CPU, NULL, cia, sim_signalled, SIM_SIGILL);
}
-// Bcond
-// ddddd,1011,ddd,cccc:III:::Bcond
-// "b<cond> disp9"
-
-ddddd,1011,ddd,0000:III:::bv
-"bv <disp9>"
-{
- COMPAT_1 (OP_580 ());
-}
-
-ddddd,1011,ddd,0001:III:::bl
-"bl <disp9>"
+// Map condition code to a string
+:%s::::cccc:int cccc
{
- COMPAT_1 (OP_581 ());
-}
-
-ddddd,1011,ddd,0010:III:::be
-"be <disp9>"
-{
- COMPAT_1 (OP_582 ());
-}
-
-ddddd,1011,ddd,0011:III:::bnh
-"bnh <disp9>"
-{
- COMPAT_1 (OP_583 ());
-}
-
-ddddd,1011,ddd,0100:III:::bn
-"bn <disp9>"
-{
- COMPAT_1 (OP_584 ());
-}
-
-ddddd,1011,ddd,0101:III:::br
-"br <disp9>"
-{
- COMPAT_1 (OP_585 ());
-}
+ switch (cccc)
+ {
+ case 0xf: return "gt";
+ case 0xe: return "ge";
+ case 0x6: return "lt";
-ddddd,1011,ddd,0110:III:::blt
-"blt <disp9>"
-{
- COMPAT_1 (OP_586 ());
-}
+ case 0x7: return "le";
-ddddd,1011,ddd,0111:III:::ble
-"ble <disp9>"
-{
- COMPAT_1 (OP_587 ());
-}
+ case 0xb: return "h";
+ case 0x9: return "nl";
+ case 0x1: return "l";
-ddddd,1011,ddd,1000:III:::bnv
-"bnv <disp9>"
-{
- COMPAT_1 (OP_588 ());
-}
+ case 0x3: return "nh";
-ddddd,1011,ddd,1001:III:::bnl
-"bnl <disp9>"
-{
- COMPAT_1 (OP_589 ());
-}
+ case 0x2: return "e";
-ddddd,1011,ddd,1010:III:::bne
-"bne <disp9>"
-{
- COMPAT_1 (OP_58A ());
-}
+ case 0xa: return "ne";
-ddddd,1011,ddd,1011:III:::bh
-"bh <disp9>"
-{
- COMPAT_1 (OP_58B ());
-}
-
-ddddd,1011,ddd,1100:III:::bp
-"bp <disp9>"
-{
- COMPAT_1 (OP_58C ());
-}
-
-ddddd,1011,ddd,1101:III:::bsa
-"bsa <disp9>"
-{
- COMPAT_1 (OP_58D ());
+ case 0x0: return "v";
+ case 0x8: return "nv";
+ case 0x4: return "n";
+ case 0xc: return "p";
+ /* case 0x1: return "c"; */
+ /* case 0x9: return "nc"; */
+ /* case 0x2: return "z"; */
+ /* case 0xa: return "nz"; */
+ case 0x5: return "r"; /* always */
+ case 0xd: return "sa";
+ }
+ return "(null)";
}
-ddddd,1011,ddd,1110:III:::bge
-"bge <disp9>"
-{
- COMPAT_1 (OP_58E ());
-}
-ddddd,1011,ddd,1111:III:::bgt
-"bgt <disp9>"
+// Bcond
+ddddd,1011,ddd,cccc:III:::Bcond
+"b%s<cccc> <disp9>"
{
- COMPAT_1 (OP_58F ());
+ int cond;
+ if ((ddddd == 0x00) && (ddd == 0x00) && (cccc == 0x05)) {
+ // Special case - treat "br *" like illegal instruction
+ sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
+ } else {
+ cond = condition_met (cccc);
+ if (cond)
+ nia = cia + disp9;
+ TRACE_BRANCH1 (cond);
+ }
}
-// start-sanitize-v850e
// BSH
rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"bsh r<reg2>, r<reg3>"
{
unsigned32 value;
TRACE_ALU_RESULT (GR[reg3]);
}
-
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// BSW
rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"bsw r<reg2>, r<reg3>"
{
#define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
TRACE_ALU_RESULT (GR[reg3]);
}
-
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// CALLT
0000001000,iiiiii:II:::callt
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"callt <imm6>"
{
unsigned32 adr;
}
-
-// end-sanitize-v850e
// CLR1
10,bbb,111110,RRRRR + dddddddddddddddd:VIII:::clr1
"clr1 <bit3>, <disp16>[r<reg1>]"
COMPAT_2 (OP_87C0 ());
}
-// start-sanitize-v850e
rrrrr,111111,RRRRR + 0000000011100100:IX:::clr1
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"clr1 r<reg2>, [r<reg1>]"
{
COMPAT_2 (OP_E407E0 ());
}
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// CTRET
0000011111100000 + 0000000101000100:X:::ctret
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"ctret"
{
nia = (CTPC & ~1);
TRACE_BRANCH1 (PSW);
}
-
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// CMOV
rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
-"cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
+*v850e1
+"cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
{
- COMPAT_2 (OP_32007E0 ());
+ int cond = condition_met (cccc);
+ TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
+ GR[reg3] = cond ? GR[reg1] : GR[reg2];
+ TRACE_ALU_RESULT (GR[reg3]);
}
-// end-sanitize-v850e
-// start-sanitize-v850e
rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
-"cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
+*v850e1
+"cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
{
- COMPAT_2 (OP_30007E0 ());
+ int cond = condition_met (cccc);
+ TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
+ GR[reg3] = cond ? imm5 : GR[reg2];
+ TRACE_ALU_RESULT (GR[reg3]);
}
-
-
-// end-sanitize-v850e
// CMP
rrrrr,001111,RRRRR:I:::cmp
"cmp r<reg1>, r<reg2>"
-// start-sanitize-v850e
// DISPOSE
// 0000011001,iiiii,L + LLLLLLLLLLL,00000:XIII:::dispose
// "dispose <imm5>, <list12>"
0000011001,iiiii,L + LLLLLLLLLLL,RRRRR:XIII:::dispose
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"dispose <imm5>, <list12>":RRRRR == 0
"dispose <imm5>, <list12>, [reg1]"
{
}
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// DIV
rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
*v850e
+*v850e1
"div r<reg1>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_2C007E0 ());
}
-
-
-// end-sanitize-v850e
// DIVH
rrrrr!0,000010,RRRRR!0:I:::divh
"divh r<reg1>, r<reg2>"
{
- COMPAT_1 (OP_40 ());
+ unsigned32 ov, s, z;
+ signed long int op0, op1, result;
+
+ trace_input ("divh", OP_REG_REG, 0);
+
+ PC = cia;
+ OP[0] = instruction_0 & 0x1f;
+ OP[1] = (instruction_0 >> 11) & 0x1f;
+
+ /* Compute the result. */
+ op0 = EXTEND16 (State.regs[OP[0]]);
+ op1 = State.regs[OP[1]];
+
+ if (op0 == 0xffffffff && op1 == 0x80000000)
+ {
+ result = 0x80000000;
+ ov = 1;
+ }
+ else if (op0 != 0)
+ {
+ result = op1 / op0;
+ ov = 0;
+ }
+ else
+ {
+ result = 0x0;
+ ov = 1;
+ }
+
+ /* Compute the condition codes. */
+ z = (result == 0);
+ s = (result & 0x80000000);
+
+ /* Store the result and condition codes. */
+ State.regs[OP[1]] = result;
+ PSW &= ~(PSW_Z | PSW_S | PSW_OV);
+ PSW |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0) | (ov ? PSW_OV : 0));
+
+ trace_output (OP_REG_REG);
+
+ PC += 2;
+ nia = PC;
}
-// start-sanitize-v850e
rrrrr,111111,RRRRR + wwwww,01010000000:XI:::divh
*v850e
+*v850e1
"divh r<reg1>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_28007E0 ());
}
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// DIVHU
rrrrr,111111,RRRRR + wwwww,01010000010:XI:::divhu
*v850e
+*v850e1
"divhu r<reg1>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_28207E0 ());
}
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// DIVU
rrrrr,111111,RRRRR + wwwww,01011000010:XI:::divu
*v850e
+*v850e1
"divu r<reg1>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_2C207E0 ());
}
-
-// end-sanitize-v850e
// EI
1000011111100000 + 0000000101100000:X:::ei
"ei"
-// start-sanitize-v850e
// HSW
rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"hsw r<reg2>, r<reg3>"
{
unsigned32 value;
-// end-sanitize-v850e
// JARL
rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
"jarl <disp22>, r<reg2>"
{
- COMPAT_2 (OP_780 ());
+ GR[reg2] = nia;
+ nia = cia + disp22;
+ TRACE_BRANCH1 (GR[reg2]);
}
00000000011,RRRRR:I:::jmp
"jmp [r<reg1>]"
{
- SAVE_1;
- trace_input ("jmp", OP_REG, 0);
- nia = State.regs[ reg1 ];
- trace_output (OP_REG);
+ nia = GR[reg1] & ~1;
+ TRACE_BRANCH0 ();
}
0000011110,dddddd + ddddddddddddddd,0:V:::jr
"jr <disp22>"
{
- COMPAT_2 (OP_780 ());
+ nia = cia + disp22;
+ TRACE_BRANCH0 ();
}
// LD
rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
-"ld.b <disp16>[r<reg1>, r<reg2>"
+"ld.b <disp16>[r<reg1>], r<reg2>"
{
COMPAT_2 (OP_700 ());
}
COMPAT_2 (OP_10720 ());
}
-// start-sanitize-v850e
rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"ld.bu <disp16>[r<reg1>], r<reg2>"
{
COMPAT_2 (OP_10780 ());
}
-// end-sanitize-v850e
-// start-sanitize-v850e
rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"ld.hu <disp16>[r<reg1>], r<reg2>"
{
COMPAT_2 (OP_107E0 ());
}
-// end-sanitize-v850e
// LDSR
regID,111111,RRRRR + 0000000000100000:IX:::ldsr
"ldsr r<reg1>, s<regID>"
COMPAT_1 (OP_200 ());
}
-// start-sanitize-v850e
00000110001,RRRRR + iiiiiiiiiiiiiiii + IIIIIIIIIIIIIIII:VI:::mov
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"mov <imm32>, r<reg1>"
{
SAVE_2;
-// end-sanitize-v850e
// MOVEA
rrrrr!0,110001,RRRRR + iiiiiiiiiiiiiiii:VI:::movea
"movea <simm16>, r<reg1>, r<reg2>"
-// start-sanitize-v850e
// MUL
rrrrr,111111,RRRRR + wwwww,01000100000:XI:::mul
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"mul r<reg1>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_22007E0 ());
}
-// end-sanitize-v850e
-// start-sanitize-v850e
rrrrr,111111,iiiii + wwwww,01001,IIII,00:XII:::mul
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"mul <imm9>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_24007E0 ());
}
-
-// end-sanitize-v850e
// MULH
rrrrr!0,000111,RRRRR:I:::mulh
"mulh r<reg1>, r<reg2>"
-// start-sanitize-v850e
// MULU
rrrrr,111111,RRRRR + wwwww,01000100010:XI:::mulu
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"mulu r<reg1>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_22207E0 ());
rrrrr,111111,iiiii + wwwww,01001,IIII,10:XII:::mulu
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"mulu <imm9>, r<reg2>, r<reg3>"
{
COMPAT_2 (OP_24207E0 ());
-// end-sanitize-v850e
// NOP
0000000000000000:I:::nop
"nop"
COMPAT_2 (OP_47C0 ());
}
-// start-sanitize-v850e
rrrrr,111111,RRRRR + 0000000011100010:IX:::not1
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"not1 r<reg2>, r<reg1>"
{
COMPAT_2 (OP_E207E0 ());
-// end-sanitize-v850e
// OR
rrrrr,001000,RRRRR:I:::or
"or r<reg1>, r<reg2>"
-// start-sanitize-v850e
// PREPARE
0000011110,iiiii,L + LLLLLLLLLLL,00001:XIII:::prepare
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"prepare <list12>, <imm5>"
{
int i;
0000011110,iiiii,L + LLLLLLLLLLL,00011:XIII:::prepare00
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"prepare <list12>, <imm5>, sp"
{
COMPAT_2 (OP_30780 ());
0000011110,iiiii,L + LLLLLLLLLLL,01011 + iiiiiiiiiiiiiiii:XIII:::prepare01
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"prepare <list12>, <imm5>, <uimm16>"
{
COMPAT_2 (OP_B0780 ());
0000011110,iiiii,L + LLLLLLLLLLL,10011 + iiiiiiiiiiiiiiii:XIII:::prepare10
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"prepare <list12>, <imm5>, <uimm16>"
{
COMPAT_2 (OP_130780 ());
0000011110,iiiii,L + LLLLLLLLLLL,11011 + iiiiiiiiiiiiiiii + dddddddddddddddd:XIII:::prepare11
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"prepare <list12>, <imm5>, <uimm32>"
{
COMPAT_2 (OP_1B0780 ());
-// end-sanitize-v850e
// RETI
0000011111100000 + 0000000101000000:X:::reti
"reti"
-// start-sanitize-v850e
// SASF
rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
-"sasf <cccc>, r<reg2>"
+*v850e1
+"sasf %s<cccc>, r<reg2>"
{
COMPAT_2 (OP_20007E0 ());
}
-// end-sanitize-v850e
// SATADD
rrrrr!0,000110,RRRRR:I:::satadd
"satadd r<reg1>, r<reg2>"
// SETF
rrrrr,1111110,cccc + 0000000000000000:IX:::setf
-"setf <cccc>, r<reg2>"
+"setf %s<cccc>, r<reg2>"
{
COMPAT_2 (OP_7E0 ());
}
COMPAT_2 (OP_7C0 ());
}
-// start-sanitize-v850e
rrrrr,111111,RRRRR + 0000000011100000:IX:::set1
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"set1 r<reg2>, [r<reg1>]"
{
COMPAT_2 (OP_E007E0 ());
-// end-sanitize-v850e
// SHL
rrrrr,111111,RRRRR + 0000000011000000:IX:::shl
"shl r<reg1>, r<reg2>"
// SLD
rrrrr,0110,ddddddd:IV:::sld.b
+"sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
"sld.b <disp7>[ep], r<reg2>"
{
- COMPAT_1 (OP_300 ());
+ unsigned32 addr = EP + disp7;
+ unsigned32 result = load_mem (addr, 1);
+ if (PSW & PSW_US)
+ {
+ GR[reg2] = result;
+ TRACE_LD_NAME ("sld.bu", addr, result);
+ }
+ else
+ {
+ result = EXTEND8 (result);
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
+ }
}
rrrrr,1000,ddddddd:IV:::sld.h
+"sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
"sld.h <disp8>[ep], r<reg2>"
{
- COMPAT_1 (OP_400 ());
+ unsigned32 addr = EP + disp8;
+ unsigned32 result = load_mem (addr, 2);
+ if (PSW & PSW_US)
+ {
+ GR[reg2] = result;
+ TRACE_LD_NAME ("sld.hu", addr, result);
+ }
+ else
+ {
+ result = EXTEND16 (result);
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
+ }
}
rrrrr,1010,dddddd,0:IV:::sld.w
"sld.w <disp8>[ep], r<reg2>"
{
- COMPAT_1 (OP_500 ());
+ unsigned32 addr = EP + disp8;
+ unsigned32 result = load_mem (addr, 4);
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
}
-// start-sanitize-v850e
rrrrr!0,0000110,dddd:IV:::sld.bu
+*v850e
+*v850e1
+"sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
"sld.bu <disp4>[ep], r<reg2>"
{
- unsigned long result;
-
- SAVE_1;
- result = load_mem (State.regs[30] + disp4, 1);
-
- /* start-sanitize-v850eq */
- if (PSW & PSW_US) {
- trace_input ("sld.b", OP_LOAD16, 1);
-
- State.regs[ reg2 ] = EXTEND8 (result);
- } else {
- /* end-sanitize-v850eq */
- trace_input ("sld.bu", OP_LOAD16, 1);
- State.regs[ reg2 ] = result;
- /* start-sanitize-v850eq */
- }
- /* end-sanitize-v850eq */
- trace_output (OP_LOAD16);
+ unsigned32 addr = EP + disp4;
+ unsigned32 result = load_mem (addr, 1);
+ if (PSW & PSW_US)
+ {
+ result = EXTEND8 (result);
+ GR[reg2] = result;
+ TRACE_LD_NAME ("sld.b", addr, result);
+ }
+ else
+ {
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
+ }
}
-// end-sanitize-v850e
-// start-sanitize-v850e
rrrrr!0,0000111,dddd:IV:::sld.hu
+*v850e
+*v850e1
+"sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
"sld.hu <disp5>[ep], r<reg2>"
{
- COMPAT_1 (OP_70 ());
+ unsigned32 addr = EP + disp5;
+ unsigned32 result = load_mem (addr, 2);
+ if (PSW & PSW_US)
+ {
+ result = EXTEND16 (result);
+ GR[reg2] = result;
+ TRACE_LD_NAME ("sld.h", addr, result);
+ }
+ else
+ {
+ GR[reg2] = result;
+ TRACE_LD (addr, result);
+ }
}
-// end-sanitize-v850e
-
-
// SST
rrrrr,0111,ddddddd:IV:::sst.b
"sst.b r<reg2>, <disp7>[ep]"
COMPAT_1 (OP_501 ());
}
-
-
// ST
rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
"st.b r<reg2>, <disp16>[r<reg1>]"
COMPAT_2 (OP_10760 ());
}
-
-
// STSR
rrrrr,111111,regID + 0000000001000000:IX:::stsr
"stsr s<regID>, r<reg2>"
TRACE_ALU_RESULT (GR[reg2]);
}
-
-
// SUB
rrrrr,001101,RRRRR:I:::sub
"sub r<reg1>, r<reg2>"
COMPAT_1 (OP_1A0 ());
}
-
-
// SUBR
rrrrr,001100,RRRRR:I:::subr
"subr r<reg1>, r<reg2>"
COMPAT_1 (OP_180 ());
}
-
-
-// start-sanitize-v850e
// SWITCH
00000000010,RRRRR:I:::switch
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"switch r<reg1>"
{
unsigned long adr;
trace_output (OP_REG);
}
-
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// SXB
00000000101,RRRRR:I:::sxb
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"sxb r<reg1>"
{
TRACE_ALU_INPUT1 (GR[reg1]);
TRACE_ALU_RESULT (GR[reg1]);
}
-
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// SXH
00000000111,RRRRR:I:::sxh
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"sxh r<reg1>"
{
TRACE_ALU_INPUT1 (GR[reg1]);
TRACE_ALU_RESULT (GR[reg1]);
}
-
-
-// end-sanitize-v850e
// TRAP
00000111111,iiiii + 0000000100000000:X:::trap
"trap <vector>"
COMPAT_2 (OP_10007E0 ());
}
-
-
// TST
rrrrr,001011,RRRRR:I:::tst
"tst r<reg1>, r<reg2>"
COMPAT_1 (OP_160 ());
}
-
-
// TST1
11,bbb,111110,RRRRR + dddddddddddddddd:VIII:::tst1
"tst1 <bit3>, <disp16>[r<reg1>]"
COMPAT_2 (OP_C7C0 ());
}
-// start-sanitize-v850e
rrrrr,111111,RRRRR + 0000000011100110:IX:::tst1
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"tst1 r<reg2>, [r<reg1>]"
{
COMPAT_2 (OP_E607E0 ());
}
-
-
-// end-sanitize-v850e
// XOR
rrrrr,001001,RRRRR:I:::xor
"xor r<reg1>, r<reg2>"
COMPAT_1 (OP_120 ());
}
-
-
// XORI
rrrrr,110101,RRRRR + iiiiiiiiiiiiiiii:VI:::xori
"xori <uimm16>, r<reg1>, r<reg2>"
COMPAT_2 (OP_6A0 ());
}
-
-
-// start-sanitize-v850e
// ZXB
00000000100,RRRRR:I:::zxb
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"zxb r<reg1>"
{
TRACE_ALU_INPUT1 (GR[reg1]);
TRACE_ALU_RESULT (GR[reg1]);
}
-
-
-// end-sanitize-v850e
-// start-sanitize-v850e
// ZXH
00000000110,RRRRR:I:::zxh
*v850e
-// start-sanitize-v850eq
-*v850eq
-// end-sanitize-v850eq
+*v850e1
"zxh r<reg1>"
{
TRACE_ALU_INPUT1 (GR[reg1]);
TRACE_ALU_RESULT (GR[reg1]);
}
-
-
-// end-sanitize-v850e
-// Special - breakpoint - illegal
-// Hopefully, in the future, this instruction will go away
-1111111111111111 + 1111111111111111:Z:::breakpoint
-*v850
-{
- sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
-}
-
-// start-sanitize-v850e
-// First field could be any nonzero value.
+// Right field must be zero so that it doesn't clash with DIVH
+// Left field must be non-zero so that it doesn't clash with SWITCH
11111,000010,00000:I:::break
+*v850
+*v850e
{
- sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIGTRAP);
-}
-
-// end-sanitize-v850e
-
-
-// start-sanitize-v850eq
-// DIVHN
-rrrrr,111111,RRRRR + wwwww,01010,iiii,00:XI:::divhn
-*v850eq
-"divhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
-{
- signed32 quotient;
- signed32 remainder;
- signed32 divide_by;
- signed32 divide_this;
- boolean overflow = false;
- SAVE_2;
-
- trace_input ("divhn", OP_IMM_REG_REG_REG, 0);
-
- divide_by = EXTEND16 (State.regs[ reg1 ]);
- divide_this = State.regs[ reg2 ];
-
- divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
-
- State.regs[ reg2 ] = quotient;
- State.regs[ reg3 ] = remainder;
-
- /* Set condition codes. */
- PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-
- if (overflow) PSW |= PSW_OV;
- if (quotient == 0) PSW |= PSW_Z;
- if (quotient < 0) PSW |= PSW_S;
-
- trace_output (OP_IMM_REG_REG_REG);
-}
-
-
-
-// DIVHUN
-rrrrr,111111,RRRRR + wwwww,01010,iiii,10:XI:::divhun
-*v850eq
-"divhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
-{
- signed32 quotient;
- signed32 remainder;
- signed32 divide_by;
- signed32 divide_this;
- boolean overflow = false;
- SAVE_2;
-
- trace_input ("divhun", OP_IMM_REG_REG_REG, 0);
-
- divide_by = State.regs[ reg1 ] & 0xffff;
- divide_this = State.regs[ reg2 ];
-
- divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
-
- State.regs[ reg2 ] = quotient;
- State.regs[ reg3 ] = remainder;
-
- /* Set condition codes. */
- PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-
- if (overflow) PSW |= PSW_OV;
- if (quotient == 0) PSW |= PSW_Z;
- if (quotient & 0x80000000) PSW |= PSW_S;
-
- trace_output (OP_IMM_REG_REG_REG);
-}
-
-
-
-// DIVN
-rrrrr,111111,RRRRR + wwwww,01011,iiii,00:XI:::divn
-*v850eq
-"divn <imm5>, r<reg1>, r<reg2>, r<reg3>"
-{
- signed32 quotient;
- signed32 remainder;
- signed32 divide_by;
- signed32 divide_this;
- boolean overflow = false;
- SAVE_2;
-
- trace_input ("divn", OP_IMM_REG_REG_REG, 0);
-
- divide_by = State.regs[ reg1 ];
- divide_this = State.regs[ reg2 ];
-
- divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
-
- State.regs[ reg2 ] = quotient;
- State.regs[ reg3 ] = remainder;
-
- /* Set condition codes. */
- PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-
- if (overflow) PSW |= PSW_OV;
- if (quotient == 0) PSW |= PSW_Z;
- if (quotient < 0) PSW |= PSW_S;
-
- trace_output (OP_IMM_REG_REG_REG);
-}
-
-
-
-// DIVUN
-rrrrr,111111,RRRRR + wwwww,01011,iiii,10:XI:::divun
-*v850eq
-"divun <imm5>, r<reg1>, r<reg2>, r<reg3>"
-{
- signed32 quotient;
- signed32 remainder;
- signed32 divide_by;
- signed32 divide_this;
- boolean overflow = false;
- SAVE_2;
-
- trace_input ("divun", OP_IMM_REG_REG_REG, 0);
-
- divide_by = State.regs[ reg1 ];
- divide_this = State.regs[ reg2 ];
-
- divun (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
-
- State.regs[ reg2 ] = quotient;
- State.regs[ reg3 ] = remainder;
-
- /* Set condition codes. */
- PSW &= ~(PSW_Z | PSW_S | PSW_OV);
-
- if (overflow) PSW |= PSW_OV;
- if (quotient == 0) PSW |= PSW_Z;
- if (quotient & 0x80000000) PSW |= PSW_S;
-
- trace_output (OP_IMM_REG_REG_REG);
-}
-
-
-
-// SDIVHN
-rrrrr,111111,RRRRR + wwwww,00110,iiii,00:XI:::sdivhn
-*v850eq
-"sdivhn <imm5>, r<reg1>, r<reg2>, r<reg3>"
-{
- COMPAT_2 (OP_18007E0 ());
-}
-
-
-
-// SDIVHUN
-rrrrr,111111,RRRRR + wwwww,00110,iiii,10:XI:::sdivhun
-*v850eq
-"sdivhun <imm5>, r<reg1>, r<reg2>, r<reg3>"
-{
- COMPAT_2 (OP_18207E0 ());
-}
-
-
-
-// SDIVN
-rrrrr,111111,RRRRR + wwwww,00111,iiii,00:XI:::sdivn
-*v850eq
-"sdivn <imm5>, r<reg1>, r<reg2>, r<reg3>"
-{
- COMPAT_2 (OP_1C007E0 ());
-}
-
-
-
-// SDIVUN
-rrrrr,111111,RRRRR + wwwww,00111,iiii,10:XI:::sdivun
-*v850eq
-"sdivun <imm5>, r<reg1>, r<reg2>, r<reg3>"
-{
- COMPAT_2 (OP_1C207E0 ());
-}
-
-
-
-// PUSHML
-000001111110,LLLL + LLLLLLLLLLLL,S,001:XIV:::pushml
-*v850eq
-"pushml <list18>"
-{
- int i;
- SAVE_2;
-
- trace_input ("pushml", OP_PUSHPOP3, 0);
-
- /* Store the registers with lower number registers being placed at
- higher addresses. */
-
- for (i = 0; i < 15; i++)
- if ((OP[3] & (1 << type3_regs[ i ])))
- {
- SP -= 4;
- store_mem (SP & ~ 3, 4, State.regs[ i + 1 ]);
- }
-
- if (OP[3] & (1 << 3))
- {
- SP -= 4;
-
- store_mem (SP & ~ 3, 4, PSW);
- }
-
- if (OP[3] & (1 << 19))
- {
- SP -= 8;
-
- if ((PSW & PSW_NP) && ((PSW & PSW_EP) == 0))
- {
- store_mem ((SP + 4) & ~ 3, 4, FEPC);
- store_mem ( SP & ~ 3, 4, FEPSW);
- }
- else
- {
- store_mem ((SP + 4) & ~ 3, 4, EIPC);
- store_mem ( SP & ~ 3, 4, EIPSW);
- }
- }
-
- trace_output (OP_PUSHPOP2);
+ sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
}
-
-
-// PUSHHML
-000001111110,LLLL + LLLLLLLLLLLL,S,011:XIV:::pushmh
-*v850eq
-"pushhml <list18>"
+11111,000010,00000:I:::dbtrap
+*v850e1
+"dbtrap"
{
- COMPAT_2 (OP_307E0 ());
+ DBPC = cia + 2;
+ DBPSW = PSW;
+ PSW = PSW | (PSW_NP | PSW_EP | PSW_ID);
+ PC = 0x00000060;
+ nia = 0x00000060;
+ TRACE_BRANCH0 ();
}
-
-
-// POPML
-000001111111,LLLL + LLLLLLLLLLLL,S,001:XIV:::popml
-*v850eq
-"popml <list18>"
+// New breakpoint: 0x7E0 0x7E0
+00000,111111,00000 + 00000,11111,100000:X:::ilgop
{
- COMPAT_2 (OP_107F0 ());
+ sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
}
-
-
-// POPMH
-000001111111,LLLL + LLLLLLLLLLLL,S,011:XIV:::popmh
-*v850eq
-"popmh <list18>"
+// Return from debug trap: 0x146007e0
+0000011111100000 + 0000000101000110:X:::dbret
+*v850e1
+"dbret"
{
- COMPAT_2 (OP_307F0 ());
+ nia = DBPC;
+ PSW = DBPSW;
+ TRACE_BRANCH1 (PSW);
}
-
-
-// end-sanitize-v850eq
projects / deliverable / binutils-gdb.git / blobdiff