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ASoc: DaVinci: i2s, minor cleanup
[deliverable/linux.git] / sound / soc / davinci / davinci-i2s.c
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index b1ea52fc83c7b58a3090957c8351393c816696ea..f7d7e4c30764f99f0d8660a7629979d5eeb00dd5 100644 (file)
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -85,14 +85,6 @@
 #define DAVINCI_MCBSP_PCR_FSRM         (1 << 10)
 #define DAVINCI_MCBSP_PCR_FSXM         (1 << 11)
 
-#define MOD_REG_BIT(val, mask, set) do { \
-       if (set) { \
-               val |= mask; \
-       } else { \
-               val &= ~mask; \
-       } \
-} while (0)
-
 enum {
        DAVINCI_MCBSP_WORD_8 = 0,
        DAVINCI_MCBSP_WORD_12,
@@ -112,6 +104,7 @@ static struct davinci_pcm_dma_params davinci_i2s_pcm_in = {
 
 struct davinci_mcbsp_dev {
        void __iomem                    *base;
+       u32                             pcr;
        struct clk                      *clk;
        struct davinci_pcm_dma_params   *dma_params[2];
 };
@@ -127,19 +120,36 @@ static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg)
        return __raw_readl(dev->base + reg);
 }
 
-static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
+static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback)
+{
+       u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP;
+       /* The clock needs to toggle to complete reset.
+        * So, fake it by toggling the clk polarity.
+        */
+       davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m);
+       davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr);
+}
+
+static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev,
+               struct snd_pcm_substream *substream)
 {
        struct snd_soc_pcm_runtime *rtd = substream->private_data;
-       struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
        struct snd_soc_device *socdev = rtd->socdev;
        struct snd_soc_platform *platform = socdev->card->platform;
-       u32 w;
+       int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
+       u32 spcr;
        int ret;
-
+       u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST;
+       spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
+       if (spcr & mask) {
+               /* start off disabled */
+               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG,
+                               spcr & ~mask);
+               toggle_clock(dev, playback);
+       }
        /* Start the sample generator and enable transmitter/receiver */
-       w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
-       MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST, 1);
-       davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
+       spcr |= DAVINCI_MCBSP_SPCR_GRST;
+       davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 
        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
                /* Stop the DMA to avoid data loss */
@@ -152,17 +162,18 @@ static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
                }
 
                /* Enable the transmitter */
-               w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
-               MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
-               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
+               spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
+               spcr |= DAVINCI_MCBSP_SPCR_XRST;
+               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 
                /* wait for any unexpected frame sync error to occur */
                udelay(100);
 
                /* Disable the transmitter to clear any outstanding XSYNCERR */
-               w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
-               MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
-               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
+               spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
+               spcr &= ~DAVINCI_MCBSP_SPCR_XRST;
+               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
+               toggle_clock(dev, playback);
 
                /* Restart the DMA */
                if (platform->pcm_ops->trigger) {
@@ -172,40 +183,35 @@ static void davinci_mcbsp_start(struct snd_pcm_substream *substream)
                                printk(KERN_DEBUG "Playback DMA start failed\n");
                }
                /* Enable the transmitter */
-               w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
-               MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 1);
-               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
+               spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
+               spcr |= DAVINCI_MCBSP_SPCR_XRST;
+               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 
        } else {
 
                /* Enable the reciever */
-               w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
-               MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 1);
-               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
+               spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
+               spcr |= DAVINCI_MCBSP_SPCR_RRST;
+               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
        }
 
 
        /* Start frame sync */
-       w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
-       MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_FRST, 1);
-       davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
+       spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
+       spcr |= DAVINCI_MCBSP_SPCR_FRST;
+       davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 }
 
-static void davinci_mcbsp_stop(struct snd_pcm_substream *substream)
+static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback)
 {
-       struct snd_soc_pcm_runtime *rtd = substream->private_data;
-       struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
-       u32 w;
+       u32 spcr;
 
        /* Reset transmitter/receiver and sample rate/frame sync generators */
-       w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
-       MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_GRST |
-                      DAVINCI_MCBSP_SPCR_FRST, 0);
-       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
-               MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_XRST, 0);
-       else
-               MOD_REG_BIT(w, DAVINCI_MCBSP_SPCR_RRST, 0);
-       davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
+       spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
+       spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST);
+       spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST;
+       davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
+       toggle_clock(dev, playback);
 }
 
 static int davinci_i2s_startup(struct snd_pcm_substream *substream,
@@ -343,6 +349,7 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
                return -EINVAL;
        }
        davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
+       dev->pcr = pcr;
        davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr);
        davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
        davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
@@ -358,25 +365,26 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
        struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
        struct snd_interval *i = NULL;
        int mcbsp_word_length;
-       u32 w;
+       unsigned int rcr, xcr, srgr;
+       u32 spcr;
 
        /* general line settings */
-       w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
+       spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
        if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
-               w |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
-               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
+               spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
+               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
        } else {
-               w |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
-               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, w);
+               spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE;
+               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
        }
 
        i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
-       w = DAVINCI_MCBSP_SRGR_FSGM;
-       MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1), 1);
+       srgr = DAVINCI_MCBSP_SRGR_FSGM;
+       srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
 
        i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
-       MOD_REG_BIT(w, DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1), 1);
-       davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, w);
+       srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
+       davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
 
        /* Determine xfer data type */
        switch (params_format(params)) {
@@ -398,16 +406,16 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
        }
 
        if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
-               w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
-               MOD_REG_BIT(w, DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
-                              DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length), 1);
-               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, w);
+               rcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_RCR_REG);
+               rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
+                              DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
+               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
 
        } else {
-               w = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
-               MOD_REG_BIT(w, DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
-                              DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length), 1);
-               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, w);
+               xcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_XCR_REG);
+               xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
+                               DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
+               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
 
        }
        return 0;
@@ -416,18 +424,21 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
                               struct snd_soc_dai *dai)
 {
+       struct snd_soc_pcm_runtime *rtd = substream->private_data;
+       struct davinci_mcbsp_dev *dev = rtd->dai->cpu_dai->private_data;
        int ret = 0;
+       int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 
        switch (cmd) {
        case SNDRV_PCM_TRIGGER_START:
        case SNDRV_PCM_TRIGGER_RESUME:
        case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
-               davinci_mcbsp_start(substream);
+               davinci_mcbsp_start(dev, substream);
                break;
        case SNDRV_PCM_TRIGGER_STOP:
        case SNDRV_PCM_TRIGGER_SUSPEND:
        case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-               davinci_mcbsp_stop(substream);
+               davinci_mcbsp_stop(dev, playback);
                break;
        default:
                ret = -EINVAL;
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