X-Git-Url: http://drtracing.org/?a=blobdiff_plain;ds=sidebyside;f=cpu%2Fm32c.cpu;h=ab65fc13626731ce6d2a03fc0fbaf4ede1f1115e;hb=22aa1d51198689f5f3f01a874b405bf4449cbfb0;hp=a70124ea6de92b0e2fd6a700222e121e2abb3ca8;hpb=458f77708df3947fe746f7a1e2d59d4077da4ea4;p=deliverable%2Fbinutils-gdb.git diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu index a70124ea6d..ab65fc1362 100644 --- a/cpu/m32c.cpu +++ b/cpu/m32c.cpu @@ -1,6 +1,6 @@ ; Renesas M32C CPU description. -*- Scheme -*- ; -; Copyright 2005 Free Software Foundation, Inc. +; Copyright 2005, 2006, 2007, 2009 Free Software Foundation, Inc. ; ; Contributed by Red Hat Inc; developed under contract from Renesas. ; @@ -8,7 +8,7 @@ ; ; This program is free software; you can redistribute it and/or modify ; it under the terms of the GNU General Public License as published by -; the Free Software Foundation; either version 2 of the License, or +; the Free Software Foundation; either version 3 of the License, or ; (at your option) any later version. ; ; This program is distributed in the hope that it will be useful, @@ -18,7 +18,8 @@ ; ; You should have received a copy of the GNU General Public License ; along with this program; if not, write to the Free Software -; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. +; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +; MA 02110-1301, USA. (include "simplify.inc") @@ -139,6 +140,13 @@ ) ) +(define-attr + (type enum) + (name RL_TYPE) + (values NONE JUMP 1ADDR 2ADDR) + (default NONE) + ) + ; Macros to simplify MACH attribute specification. (define-pmacro all-isas () (ISA m16c,m32c)) @@ -150,6 +158,11 @@ (define-pmacro (machine size) (MACH (.sym m size c)) (ISA (.sym m size c))) + +(define-pmacro RL_JUMP (RL_TYPE JUMP)) +(define-pmacro RL_1ADDR (RL_TYPE 1ADDR)) +(define-pmacro RL_2ADDR (RL_TYPE 2ADDR)) + ;============================================================= ; Fields @@ -227,7 +240,7 @@ ; r1l 10'b 11'b ; r1h 11'b 01'b (df f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract ) ; QI mode gr encoding for m32c is different than for m16c. The hardware @@ -239,7 +252,7 @@ ; r1l 10'b 11'b ; r1h 11'b 01'b (df f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract ) ; HI mode gr encoding for m32c is different than for m16c. The hardware @@ -303,11 +316,11 @@ ; r1l 10'b 11'b ; r1h 11'b 01'b (df f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract ) (df f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract ) ; HI mode gr encoding for m32c is different than for m16c. The hardware @@ -423,42 +436,42 @@ (df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert + (and (srl value 8) #xff) + (sll (and value #xff) 8))) ; insert ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract + (and UHI (srl UHI value 8) #xff) + (sll UHI (and UHI value #xff) 8))) ; extract ) (df f-dsp-8-s16 "8 bit signed" (all-isas) 8 16 INT ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; insert ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; extract ) (df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert + (and (srl value 8) #xff) + (sll (and value #xff) 8))) ; insert ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract + (and UHI (srl UHI value 8) #xff) + (sll UHI (and UHI value #xff) 8))) ; extract ) (df f-dsp-16-s16 "16 bit signed" (all-isas) 16 16 INT ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; insert ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; extract ) (dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT @@ -491,79 +504,82 @@ (df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert + (and (srl value 8) #xff) + (sll (and value #xff) 8))) ; insert ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract + (and UHI (srl UHI value 8) #xff) + (sll UHI (and UHI value #xff) 8))) ; extract ) (df f-dsp-32-s16 "16 bit signed" (all-isas) 32 16 INT ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; insert ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; extract ) (df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert + (and (srl value 8) #xff) + (sll (and value #xff) 8))) ; insert ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract + (and UHI (srl UHI value 8) #xff) + (sll UHI (and UHI value #xff) 8))) ; extract ) (df f-dsp-40-s16 "16 bit signed" (all-isas) 40 16 INT ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; insert ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; extract ) (df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert + (and (srl value 8) #xff) + (sll (and value #xff) 8))) ; insert ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract + (and UHI (srl UHI value 8) #xff) + (sll UHI (and UHI value #xff) 8))) ; extract ) (df f-dsp-48-s16 "16 bit signed" (all-isas) 48 16 INT ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; insert ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; extract ) (df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert + (and (srl value 8) #xff) + (sll (and value #xff) 8))) ; insert ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract + (and UHI (srl UHI value 8) #xff) + (sll UHI (and UHI value #xff) 8))) ; extract ) (df f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT - ((value pc) (or SI - (or (srl value 16) (and value #xff00)) - (sll (ext INT (trunc QI (and value #xff))) 16))) - ((value pc) (or SI - (or (srl value 16) (and value #xff00)) - (sll (ext INT (trunc QI (and value #xff))) 16))) + ((value pc) (sub SI (xor (or SI (or (and (srl value 16) #xff) + (and value #xff00)) + (sll (and value #xff) 16)) + #x800000) #x800000)) + ((value pc) (sub SI (xor (or SI + (or (and (srl value 16) #xff) + (and value #xff00)) + (sll (and value #xff) 16)) + #x800000) #x800000)) ) (df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT @@ -604,12 +620,25 @@ (or USI (and (srl value 16) #x0000ff) (and value #x00ff00)) - (and (sll value 16) #xff0000))) ; insert + (and (sll value 16) #xff0000))) ; insert + ((value pc) (or USI + (or USI + (and USI (srl value 16) #x0000ff) + (and USI value #x00ff00)) + (and USI (sll value 16) #xff0000))) ; extract +) + +(df f-dsp-40-u20 "20 bit unsigned" (all-isas) 40 20 UINT + ((value pc) (or USI + (or USI + (and (srl value 16) #x0000ff) + (and value #x00ff00)) + (and (sll value 16) #x0f0000))) ; insert ((value pc) (or USI (or USI - (and USI (srl UHI value 16) #x0000ff) - (and USI value #x00ff00)) - (and USI (sll UHI value 16) #xff0000))) ; extract + (and USI (srl value 16) #x0000ff) + (and USI value #x00ff00)) + (and USI (sll value 16) #x0f0000))) ; extract ) (df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT @@ -617,12 +646,12 @@ (or USI (and (srl value 16) #x0000ff) (and value #x00ff00)) - (and (sll value 16) #xff0000))) ; insert + (and (sll value 16) #xff0000))) ; insert ((value pc) (or USI (or USI - (and USI (srl UHI value 16) #x0000ff) - (and USI value #x00ff00)) - (and USI (sll UHI value 16) #xff0000))) ; extract + (and USI (srl value 16) #x0000ff) + (and USI value #x00ff00)) + (and USI (sll value 16) #xff0000))) ; extract ) (dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT @@ -637,6 +666,17 @@ ) ) +(dnmf f-dsp-48-u20 "20 bit unsigned" (all-isas) UINT + (f-dsp-48-u16 f-dsp-64-u8) + (sequence () ; insert + (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u20) 16) #x0f)) + (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u20) #xffff)) + ) + (sequence () ; extract + (set (ifield f-dsp-48-u20) (or (and (ifield f-dsp-48-u16) #xffff) + (and (sll (ifield f-dsp-64-u8) 16) #x0f0000))) + ) +) (dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT (f-dsp-48-u16 f-dsp-64-u8) (sequence () ; insert @@ -680,22 +720,22 @@ (ext INT (or SI (or SI - (and (srl value 24) #x000000ff) - (and (srl value 8) #x0000ff00)) + (and (srl value 24) #x00ff) + (and (srl value 8) #xff00)) (or SI - (and (sll value 8) #x00ff0000) - (and (sll value 24) #xff000000))))) + (sll (and value #xff00) 8) + (sll (and value #x00ff) 24))))) ;; extract ((value pc) (ext INT (or SI (or SI - (and (srl value 24) #x000000ff) - (and (srl value 8) #x0000ff00)) + (and (srl value 24) #x00ff) + (and (srl value 8) #xff00)) (or SI - (and (sll value 8) #x00ff0000) - (and (sll value 24) #xff000000))))) + (sll (and value #xff00) 8) + (sll (and value #x00ff) 24))))) ) (dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT @@ -706,7 +746,7 @@ ) (sequence () ; extract (set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff) - (and (sll (ifield f-dsp-64-u16) 16) #xffff0000))) + (sll (and (ifield f-dsp-64-u16) #xffff) 16))) ) ) @@ -718,7 +758,7 @@ ) (sequence () ; extract (set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff) - (and (sll (ifield f-dsp-64-u16) 16) #xffff0000))) + (sll (and (ifield f-dsp-64-u16) #xffff) 16))) ) ) @@ -741,12 +781,12 @@ (df f-dsp-64-s16 " 16 bit signed" (all-isas) 64 16 INT ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; insert ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; extract ) ;------------------------------------------------------------- @@ -787,7 +827,7 @@ (set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3)) ) (sequence () ; extract - (set (ifield f-bitbase32-16-s11-unprefixed) (or (sll (ifield f-dsp-16-s8) 3) + (set (ifield f-bitbase32-16-s11-unprefixed) (or (mul (ifield f-dsp-16-s8) 8) (ifield f-bitno32-unprefixed))) ) ) @@ -809,7 +849,7 @@ (set (ifield f-dsp-16-s16) (sra INT (ifield f-bitbase32-16-s19-unprefixed) 3)) ) (sequence () ; extract - (set (ifield f-bitbase32-16-s19-unprefixed) (or (sll (ifield f-dsp-16-s16) 3) + (set (ifield f-bitbase32-16-s19-unprefixed) (or (mul (ifield f-dsp-16-s16) 8) (ifield f-bitno32-unprefixed))) ) ) @@ -845,7 +885,7 @@ (set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3)) ) (sequence () ; extract - (set (ifield f-bitbase32-24-s11-prefixed) (or (sll (ifield f-dsp-24-s8) 3) + (set (ifield f-bitbase32-24-s11-prefixed) (or (mul (ifield f-dsp-24-s8) 8) (ifield f-bitno32-prefixed))) ) ) @@ -873,7 +913,7 @@ ) (sequence () ; extract (set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3) - (or (sll (ifield f-dsp-32-s8) 11) + (or (mul (ifield f-dsp-32-s8) 2048) (ifield f-bitno32-prefixed)))) ) ) @@ -919,9 +959,12 @@ ) (df f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT ((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8) - (srl (and (sub value (add pc 1)) #xffff) 8))) - ((value pc) (add SI (or (srl (and value #xffff) 8) - (sra (sll (and value #xff) 24) 16)) (add pc 1))) + (srl (and (sub value (add pc 1)) #xff00) 8))) + ((value pc) (add SI (sub (xor (or (srl (and value #xff00) 8) + (sll (and value #xff) 8)) + #x8000) + #x8000) + (add pc 1))) ) (df f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT ((value pc) (or SI @@ -1032,7 +1075,7 @@ (indices keyword "" (("r2r0" 0) ("r3r1" 1))) (get (index) (or SI (and (reg h-gr index) #xffff) - (and (sll (reg h-gr (add index 2)) 16) #xffff0000))) + (sll (and (reg h-gr (add index 2)) #xffff) 16))) (set (index newval) (sequence () (set (reg h-gr index) (and newval #xffff)) (set (reg h-gr (add index 2)) (srl newval 16))))) @@ -1865,6 +1908,10 @@ h-sint DFLT f-dsp-40-s16 ((parse "signed16")) () () ) +(define-full-operand Dsp-40-u20 "unsigned 20 bit displacement at offset 40 bits" (all-isas) + h-uint DFLT f-dsp-40-u20 + ((parse "unsigned20")) () () +) (define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas) h-uint DFLT f-dsp-40-u24 ((parse "unsigned24")) () () @@ -1885,6 +1932,10 @@ h-sint DFLT f-dsp-48-s16 ((parse "signed16")) () () ) +(define-full-operand Dsp-48-u20 "unsigned 24 bit displacement at offset 40 bits" (all-isas) + h-uint DFLT f-dsp-48-u20 + ((parse "unsigned24")) () () +) (define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas) h-uint DFLT f-dsp-48-u24 ((parse "unsigned24")) () () @@ -1896,7 +1947,7 @@ ) (define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas) h-sint DFLT f-imm-8-s4 - ((parse "signed4n")) () () + ((parse "signed4n") (print "signed4n")) () () ) (define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas) h-shimm DFLT f-imm-8-s4 @@ -2014,6 +2065,10 @@ h-sint DFLT f-imm3-S ((parse "imm3_S")) () () ) +(define-full-operand Bit3-S "3 bit bit number" (m32c-isa) + h-sint DFLT f-imm3-S + ((parse "bit3_S")) () () +) ;------------------------------------------------------------- ; Bit numbers @@ -2097,11 +2152,11 @@ (dnop Lab-8-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-8-8) (dnop Lab-8-16 "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16) -(dnop Lab-8-24 "24 bit label" (all-isas) h-iaddr f-lab-8-24) +(dnop Lab-8-24 "24 bit label" (all-isas RELAX) h-iaddr f-lab-8-24) (dnop Lab-16-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-16-8) -(dnop Lab-24-8 "8 bit label" (all-isas) h-iaddr f-lab-24-8) -(dnop Lab-32-8 "8 bit label" (all-isas) h-iaddr f-lab-32-8) -(dnop Lab-40-8 "8 bit label" (all-isas) h-iaddr f-lab-40-8) +(dnop Lab-24-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-24-8) +(dnop Lab-32-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-32-8) +(dnop Lab-40-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-40-8) ;------------------------------------------------------------- ; Condition code bits @@ -2193,6 +2248,9 @@ (define-pmacro (mem16 mode address) (mem mode (and #xffff address))) +(define-pmacro (mem20 mode address) + (mem mode (and #xfffff address))) + (define-pmacro (mem32 mode address) (mem mode (and #xffffff address))) @@ -2425,6 +2483,19 @@ (getter (mem16 xmode (add Dsp-16-u16 Src16An))) (setter (set (mem16 xmode (add Dsp-16-u16 Src16An)) newval)) ) + (define-derived-operand + (name (.sym src16-16-20-An-relative- xmode)) + (comment (.str "m16c dsp:20[An] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Src16An Dsp-16-u20)) + (syntax "${Dsp-16-u20}[$Src16An]") + (base-ifield f-8-4) + (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u20 Src16An)) + (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0))) + (getter (mem20 xmode (add Dsp-16-u20 Src16An))) + (setter (set (mem20 xmode (add Dsp-16-u20 Src16An)) newval)) + ) ) ) @@ -3141,6 +3212,19 @@ (getter (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An))) (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)) newval)) ) + (define-derived-operand + (name (.sym dst16- offset -20-An-relative- xmode)) + (comment (.str "m16c dsp:20[An] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Dst16An (.sym Dsp- offset -u20))) + (syntax (.str "${Dsp-" offset "-u20}[$Dst16An]")) + (base-ifield f-12-4) + (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u20) Dst16An)) + (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) + (getter (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An))) + (setter (set (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An)) newval)) + ) ) ) @@ -4711,6 +4795,25 @@ (.sym dst16-16-16-absolute- xmode) ) ) + (define-anyof-operand + (name (.sym dst16-16-16sa- xmode)) + (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-16-16-SB-relative- xmode) + (.sym dst16-16-16-absolute- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst16-16-20ar- xmode)) + (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-16-20-An-relative- xmode) + ) + ) ) ) @@ -5079,6 +5182,17 @@ (.sym dst32-16-16-absolute-Unprefixed- xmode) ) ) + (define-anyof-operand + (name (.sym dst32-16-16sa-Unprefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-16-16-SB-relative-Unprefixed- xmode) + (.sym dst32-16-16-FB-relative-Unprefixed- xmode) + (.sym dst32-16-16-absolute-Unprefixed- xmode) + ) + ) (define-anyof-operand (name (.sym dst32-16-24-Unprefixed- xmode)) (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) @@ -5859,7 +5973,7 @@ (define-pmacro (unary-insn-defn-g mach group mode wstr op encoding sem opg) (dni (.sym op mach wstr - group) (.str op wstr opg " dst" mach "-" group "-" mode) - ((machine mach)) + ((machine mach) RL_1ADDR) (.str op wstr opg " ${dst" mach "-" group "-" mode "}") encoding (sem mode (.sym dst mach - group - mode)) @@ -6075,7 +6189,7 @@ (define-pmacro (binary-arith-imm-dst-defn mach src dstgroup dmode wstr op suffix encoding sem) (dni (.sym op mach wstr - imm-G - dstgroup) (.str op wstr " " mach "-imm-G-" dstgroup "-" dmode) - ((machine mach)) + ((machine mach) RL_1ADDR) (.str op wstr "$"suffix " #${" src "},${dst" mach "-" dstgroup "-" dmode "}") encoding (sem dmode src (.sym dst mach - dstgroup - dmode)) @@ -6185,7 +6299,7 @@ (define-pmacro (binary-arith-imm4-dst-defn mach src dstgroup mode wstr op encoding sem) (dni (.sym op mach wstr - imm4-Q - dstgroup) (.str op wstr " " mach "-imm4-Q-" dstgroup "-" mode) - ((machine mach)) + ((machine mach) RL_1ADDR) (.str op wstr "$Q #${" src "},${dst" mach "-" dstgroup "-" mode "}") encoding (sem mode src (.sym dst mach - dstgroup - mode)) @@ -6261,7 +6375,7 @@ (define-pmacro (binary-arith-src-dst-defn mach srcgroup dstgroup smode dmode wstr op suffix encoding sem) (dni (.sym op mach wstr - srcgroup - dstgroup) (.str op wstr " dst" mach "-" srcgroup "-" dstgroup "-" dmode) - ((machine mach)) + ((machine mach) RL_2ADDR) (.str op wstr "$" suffix " ${src" mach "-" srcgroup "-" smode "},${dst" mach "-" dstgroup "-" dmode "}") encoding (sem dmode (.sym src mach - srcgroup - smode) (.sym dst mach - dstgroup - dmode)) @@ -6575,7 +6689,7 @@ (define-pmacro (arith-jnz-imm4-dst-defn mach src dstgroup label mode wstr op encoding sem) (dni (.sym op mach wstr - imm4 - dstgroup) (.str op wstr " " mach "-imm4-" dstgroup "-" label "-" mode) - ((machine mach)) + (RL_JUMP RELAXABLE (machine mach)) (.str op wstr " #${" src "},${dst" mach "-" dstgroup "-" mode "},${" label "}") encoding (sem mode src (.sym dst mach - dstgroup - mode) label) @@ -6589,10 +6703,10 @@ (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8) sem) (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-16-8) + (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-32-8) sem) (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-16-8) + (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-24-8) sem) ) ) @@ -7231,7 +7345,7 @@ (dni (.sym op 16.b-imm8) (.str op ".b #imm8") ((machine 16)) - (.str op ".b #${Imm-16-QI}") + (.str op ".b #${Imm-16-QI},r0l") (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc1) Imm-16-QI) ((.sym op -sem) QI Imm-16-QI R0l) ()) @@ -7239,7 +7353,7 @@ (dni (.sym op 16.w-imm16) (.str op ".b #imm16") ((machine 16)) - (.str op ".w #${Imm-16-HI}") + (.str op ".w #${Imm-16-HI},r0") (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc1) Imm-16-HI) ((.sym op -sem) HI Imm-16-HI R0) ()) @@ -7550,7 +7664,16 @@ (set zbit (inv dst)) (set cbit dst) ) -(bitdst-insn btst (f-0-4 7) (f-4-4 #xE) (f-8-4 #xB) (f-0-2 1) (f-2-2 1) (f-4-1 1) #xD #x0 #x0 btst-sem) +(bitdst16-defn btst (f-0-4 7) (f-4-4 #xE) (f-8-4 #xB) (f-0-2 1) (f-2-2 1) (f-4-1 1) btst-sem) + +(bit-insn-defn 32 btst G bit32-16-Unprefixed + (+ (f-0-4 #xD) bit32-16-Unprefixed (f-7-1 #x0) (f-10-3 #x0)) + btst-sem) + +(dni btst.s "btst:s" ((machine 32)) + "btst:s ${Bit3-S},${Dsp-8-u16}" + (+ (f-0-2 #x0) (f-4-3 #x5) Bit3-S Dsp-8-u16) + () ()) ;------------------------------------------------------------- ; btstc @@ -8058,7 +8181,7 @@ (dni jcnd16-5 "jCnd label" - (RELAXABLE (machine 16)) + (RL_JUMP RELAXABLE (machine 16)) "j$cond16j5 ${Lab-8-8}" (+ (f-0-4 #x6) (f-4-1 1) cond16j5 Lab-8-8) (jcnd16-sem cond16j5 Lab-8-8) @@ -8067,7 +8190,7 @@ (dni jcnd16 "jCnd label" - (RELAXABLE (machine 16)) + (RL_JUMP RELAXABLE (machine 16)) "j$cond16j ${Lab-16-8}" (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xC) cond16j Lab-16-8) (jcnd16-sem cond16j Lab-16-8) @@ -8076,7 +8199,7 @@ (dni jcnd32 "jCnd label" - (RELAXABLE (machine 32)) + (RL_JUMP RELAXABLE (machine 32)) "j$cond32j ${Lab-8-8}" (+ (f-0-1 1) (f-4-3 5) cond32j Lab-8-8) (jcnd32-sem cond32j Lab-8-8) @@ -8088,25 +8211,25 @@ ;------------------------------------------------------------- ; jmp.s label3 (m16 #1) -(dni jmp16.s "jmp.s Lab-5-3" (RELAXABLE (machine 16)) +(dni jmp16.s "jmp.s Lab-5-3" (RL_JUMP RELAXABLE (machine 16)) ("jmp.s ${Lab-5-3}") (+ (f-0-4 6) (f-4-1 0) Lab-5-3) (sequence () (set pc Lab-5-3)) ()) ; jmp.b label8 (m16 #2) -(dni jmp16.b "jmp.b Lab-8-8" (RELAXABLE (machine 16)) +(dni jmp16.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 16)) ("jmp.b ${Lab-8-8}") (+ (f-0-4 #xF) (f-4-4 #xE) Lab-8-8) (sequence () (set pc Lab-8-8)) ()) ; jmp.w label16 (m16 #3) -(dni jmp16.w "jmp.w Lab-8-16" (RELAXABLE (machine 16)) +(dni jmp16.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16)) ("jmp.w ${Lab-8-16}") (+ (f-0-4 #xF) (f-4-4 4) Lab-8-16) (sequence () (set pc Lab-8-16)) ()) ; jmp.a label24 (m16 #4) -(dni jmp16.a "jmp.a Lab-8-24" ((machine 16)) +(dni jmp16.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16)) ("jmp.a ${Lab-8-24}") (+ (f-0-4 #xF) (f-4-4 #xC) Lab-8-24) (sequence () (set pc Lab-8-24)) @@ -8133,32 +8256,32 @@ ; jmp.s label3 (m32 #1) (dni jmp32.s "jmp.s label" - (RELAXABLE (machine 32)) + (RL_JUMP RELAXABLE (machine 32)) "jmp.s ${Lab32-jmp-s}" (+ (f-0-2 1) (f-4-3 5) Lab32-jmp-s) (set pc Lab32-jmp-s) () ) ; jmp.b label8 (m32 #2) -(dni jmp32.b "jmp.b Lab-8-8" (RELAXABLE (machine 32)) +(dni jmp32.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 32)) ("jmp.b ${Lab-8-8}") (+ (f-0-4 #xB) (f-4-4 #xB) Lab-8-8) (set pc Lab-8-8) ()) ; jmp.w label16 (m32 #3) -(dni jmp32.w "jmp.w Lab-8-16" (RELAXABLE (machine 32)) +(dni jmp32.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 32)) ("jmp.w ${Lab-8-16}") (+ (f-0-4 #xC) (f-4-4 #xE) Lab-8-16) (set pc Lab-8-16) ()) ; jmp.a label24 (m32 #4) -(dni jmp32.a "jmp.a Lab-8-24" ((machine 32)) +(dni jmp32.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 32)) ("jmp.a ${Lab-8-24}") (+ (f-0-4 #xC) (f-4-4 #xC) Lab-8-24) (set pc Lab-8-24) ()) ; jmp.s imm8 (m32 #1) -(dni jmps32 "jmps Imm-8-QI" ((machine 32)) +(dni jmps32 "jmps Imm-8-QI" (RL_JUMP (machine 32)) ("jmps #${Imm-8-QI}") (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI) (set pc Imm-8-QI) @@ -8190,13 +8313,13 @@ ) ; jsr.w label16 (m16 #1) -(dni jsr16.w "jsr.w Lab-8-16" (RELAXABLE (machine 16)) +(dni jsr16.w "jsr.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16)) ("jsr.w ${Lab-8-16}") (+ (f-0-4 #xF) (f-4-4 5) Lab-8-16) (jsr16-sem 3 Lab-8-16) ()) ; jsr.a label24 (m16 #2) -(dni jsr16.a "jsr.a Lab-8-24" ((machine 16)) +(dni jsr16.a "jsr.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16)) ("jsr.a ${Lab-8-24}") (+ (f-0-4 #xF) (f-4-4 #xD) Lab-8-24) (jsr16-sem 4 Lab-8-24) @@ -8206,14 +8329,14 @@ (begin (dni (.sym jsri16 mode - op16) (.str "jsri." mode " " op16) - ((machine 16)) + (RL_1ADDR (machine 16)) (.str "jsri." mode " ${" op16 "}") (+ op16-1 op16-2 op16-3 op16) (op16-sem len op16) ()) (dni (.sym jsri32 mode - op32) (.str "jsri." mode " " op32) - ((machine 32)) + (RL_1ADDR (machine 32)) (.str "jsri." mode " ${" op32 "}") (+ op32-1 op32-2 op32-3 op32-4 op32) (op32-sem len op32) @@ -8221,39 +8344,38 @@ ) ) ; jsri.w dst (m16 #1 m32 #1)) +(jsri-defn w dst16-16-20ar-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem + dst32-16-24-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) +(jsri-defn w dst16-16-16sa-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem + dst32-16-16sa-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) (jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3) -(jsri-defn w dst16-16-16-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem - dst32-16-16-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) (jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2) -(dni jsri32.w "jsr.w dst32-16-24-Unprefixed-HI" ((machine 32)) - ("jsri.w ${dst32-16-24-Unprefixed-HI}") - (+ (f-0-4 #xC) (f-7-1 1) dst32-16-24-Unprefixed-HI (f-10-2 #x1) (f-12-4 #xF)) - (jsr32-sem 6 dst32-16-24-Unprefixed-HI) - ()) ; jsri.a (m16 #2 m32 #2) +(jsri-defn a dst16-16-20ar-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem + dst32-16-24-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) (jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3) -(jsri-defn a dst16-16-16-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem - dst32-16-16-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) +(jsri-defn a dst16-16-16sa-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem + dst32-16-16sa-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) (jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2) -(dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" ((machine 32)) - ("jsri.w ${dst32-16-24-Unprefixed-SI}") +(dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32)) + ("jsri.a ${dst32-16-24-Unprefixed-SI}") (+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1)) (jsr32-sem 6 dst32-16-24-Unprefixed-SI) ()) ; jsr.w label16 (m32 #1) -(dni jsr32.w "jsr.w label" (RELAXABLE (machine 32)) +(dni jsr32.w "jsr.w label" (RL_JUMP RELAXABLE (machine 32)) ("jsr.w ${Lab-8-16}") (+ (f-0-4 #xC) (f-4-4 #xF) Lab-8-16) (jsr32-sem 3 Lab-8-16) ()) ; jsr.a label16 (m32 #2) -(dni jsr32.a "jsr.a label" ((machine 32)) +(dni jsr32.a "jsr.a label" (RL_JUMP (machine 32)) ("jsr.a ${Lab-8-24}") (+ (f-0-4 #xC) (f-4-4 #xD) Lab-8-24) (jsr32-sem 4 Lab-8-24) @@ -8542,6 +8664,7 @@ ; ??? semantics ; ldintb <==> ldc #imm,intbh ; ldc #imm,intbl + (dni ldipl16.imm "ldipl #imm" ((machine 16)) ("ldipl #${Imm-13-u3}") (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xA) (f-12-1 0) Imm-13-u3) @@ -8897,6 +9020,17 @@ ; mul.BW src,dst (binary-arith-src-dst mul G (f-0-4 #x7) (f-4-3 4) #x1 #xC mul-sem) +(dni mul_l "mul.l src,r2r0" ((machine 32)) + ("mul.l ${dst32-24-Prefixed-SI},r2r0") + (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x1) (f-20-4 #xf) + dst32-24-Prefixed-SI) + () ()) + +(dni mulu_l "mulu.l src,r2r0" ((machine 32)) + ("mulu.l ${dst32-24-Prefixed-SI},r2r0") + (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x0) (f-20-4 #xf) + dst32-24-Prefixed-SI) + () ()) ;------------------------------------------------------------- ; mulex - multiple extend sign (m32) ;------------------------------------------------------------- @@ -9009,6 +9143,8 @@ (binary-arith32-s-imm-dst HI .w 1 or #x1 #x2 or-sem) ; or.BW src,dst (m16 #3 m32 #3) (binary-arith-src-dst or G (f-0-4 #x9) (f-4-3 4) #x1 #x5 or-sem) +; or.b:S src,r0[lh] (m16) +(binary-arith16-b-S-src2 or (f-0-4 1) (f-4-1 1) or-sem) ;------------------------------------------------------------- ; pop - restore register/memory @@ -9034,7 +9170,7 @@ (define-pmacro (pop-sem32 mode dest) (pop-sem-mach 32 mode dest)) ; pop.BW:G (m16 #1) -(unary-insn-mach 16 pop (f-0-4 7) (f-4-3 2) (f-8-4 #xD) pop-sem16) +(unary-insn-mach-g 16 pop (f-0-4 7) (f-4-3 2) (f-8-4 #xD) pop-sem16 $G) ; pop.BW:G (m32 #1) (unary-insn-mach 32 pop #xB #x2 #xF pop-sem32) @@ -9345,7 +9481,7 @@ ()) (dni push32.b.imm "push.b #Imm-8-QI" ((machine 32)) - ("push.b #Imm-8-QI") + ("push.b #${Imm-8-QI}") (+ (f-0-4 #xA) (f-4-4 #xE) Imm-8-QI) (push-sem32 QI Imm-8-QI) ()) @@ -10194,7 +10330,7 @@ ()) (dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16)) ("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}") - (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u16 Imm-32-QI) + (+ (f-0-4 #xD) (f-4-4 #xF) Imm-8-QI Dsp-16-u16 Imm-32-QI) (stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16)) ()) ; stzx.BW #imm,dst (m32)