X-Git-Url: http://drtracing.org/?a=blobdiff_plain;ds=sidebyside;f=include%2Fopcode%2FChangeLog;h=63fe454e5288f89a25dbe16b9e6c9d21a7e2dcc6;hb=886a250647ac0c608f20a7007fc2167a70f64e20;hp=b927a2c34461740d9eb94cab4928ea2f70689c6c;hpb=18870af79b2034040e6009fc2719759ca6ec75e9;p=deliverable%2Fbinutils-gdb.git diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index b927a2c344..63fe454e52 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,541 @@ +2015-10-07 Claudiu Zissulescu + Cupertino Miranda + + * arc-func.h: New file. + * arc.h: Likewise. + +2015-10-02 Yao Qi + + * aarch64.h (aarch64_zero_register_p): Move the declaration + to column one. + +2015-10-02 Yao Qi + + * aarch64.h (aarch64_decode_insn): Declare it. + +2015-09-29 Dominik Vogt + + * s390.h (S390_INSTR_FLAG_HTM): New flag. + (S390_INSTR_FLAG_VX): New flag. + (S390_INSTR_FLAG_FACILITY_MASK): New flag mask. + +2015-09-23 Nick Clifton + + * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left + shifting. + +2015-09-22 Nick Clifton + + * rx.h (enum RX_Size): Add RX_Bad_Size entry. + +2015-09-09 Daniel Santos + + * visium.h (gen_reg_table): Make static. + (fp_reg_table): Likewise. + (cc_table): Likewise. + +2015-07-20 Matthew Wahab + + * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ. + (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2. + (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ. + (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2. + +2015-07-03 Alan Modra + + * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define. + +2015-07-01 Sandra Loosemore + Cesar Philippidis + + * nios2.h (enum iw_format_type): Add R2 formats. + (enum overflow_type): Add signed_immed12_overflow and + enumeration_overflow for R2. + (struct nios2_opcode): Document new argument letters for R2. + (REG_3BIT, REG_LDWM, REG_POP): Define. + (includes): Include nios2r2.h. + (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare. + (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare. + (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare. + (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare. + (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare. + (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): + Declare. + * nios2r2.h: New file. + +2015-06-19 Peter Bergner + + * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New. + (ppc_optional_operand_value): New inline function. + +2015-06-04 Matthew Wahab + + * aarch64.h (AARCH64_V8_1): New. + +2015-06-03 Matthew Wahab + + * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New. + (ARM_ARCH_V8_1A): New. + (ARM_ARCH_V8_1A_FP): New. + (ARM_ARCH_V8_1A_SIMD): New. + (ARM_ARCH_V8_1A_CRYPTOV1): New. + (ARM_FEATURE_CORE): New. + +2015-06-02 Matthew Wahab + + * arm.h (ARM_EXT2_PAN): New. + (ARM_FEATURE_CORE_HIGH): New. + +2015-06-02 Matthew Wahab + + * arm.h (ARM_FEATURE_ALL): New. + +2015-06-02 Matthew Wahab + + * aarch64.h (AARCH64_FEATURE_RDMA): New. + +2015-06-02 Matthew Wahab + + * aarch64.h (AARCH64_FEATURE_LOR): New. + +2015-06-01 Matthew Wahab + + * aarch64.h (AARCH64_FEATURE_PAN): New. + (aarch64_sys_reg_supported_p): Declare. + (aarch64_pstatefield_supported_p): Declare. + +2015-04-30 DJ Delorie + + * rl78.h (RL78_Dis_Isa): New. + (rl78_decode_opcode): Add ISA parameter. + +2015-03-24 Terry Guo + + * arm.h (arm_feature_set): Extended to provide more available bits. + (ARM_ANY): Updated to follow above new definition. + (ARM_CPU_HAS_FEATURE): Likewise. + (ARM_CPU_IS_ANY): Likewise. + (ARM_MERGE_FEATURE_SETS): Likewise. + (ARM_CLEAR_FEATURE): Likewise. + (ARM_FEATURE): Likewise. + (ARM_FEATURE_COPY): New macro. + (ARM_FEATURE_EQUAL): Likewise. + (ARM_FEATURE_ZERO): Likewise. + (ARM_FEATURE_CORE_EQUAL): Likewise. + (ARM_FEATURE_LOW): Likewise. + (ARM_FEATURE_CORE_LOW): Likewise. + (ARM_FEATURE_CORE_COPROC): Likewise. + +2015-02-19 Pedro Alves + + * cgen.h [__cplusplus]: Wrap in extern "C". + * msp430-decode.h [__cplusplus]: Likewise. + * nios2.h [__cplusplus]: Likewise. + * rl78.h [__cplusplus]: Likewise. + * rx.h [__cplusplus]: Likewise. + * tilegx.h [__cplusplus]: Likewise. + +2015-01-28 James Bowman + + * ft32.h: New file. + +2015-01-16 Andreas Krebbel + + * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13. + +2015-01-01 Alan Modra + + Update year range in copyright notice of all files. + +2014-12-27 Anthony Green + + * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from + MOXIE_F1_AiB4 and MOXIE_F1_ABi2. + +2014-12-06 Eric Botcazou + + * visium.h: New file. + +2014-11-28 Sandra Loosemore + + * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete. + (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete. + (NIOS2_INSN_OPTARG): Renumber. + +2014-11-06 Sandra Loosemore + + * nios2.h (nios2_find_opcode_hash): Add mach parameter to + declaration. Fix obsolete comment. + +2014-10-23 Sandra Loosemore + + * nios2.h (enum iw_format_type): New. + (struct nios2_opcode): Update comments. Add size and format fields. + (NIOS2_INSN_OPTARG): New. + (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New. + (struct nios2_reg): Add regtype field. + (GET_INSN_FIELD, SET_INSN_FIELD): Delete. + (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete. + (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete. + (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete. + (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete. + (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete. + (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete. + (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete. + (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete. + (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete. + (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete. + (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete. + (OP_MASK_OP, OP_SH_OP): Delete. + (OP_MASK_IOP, OP_SH_IOP): Delete. + (OP_MASK_IRD, OP_SH_IRD): Delete. + (OP_MASK_IRT, OP_SH_IRT): Delete. + (OP_MASK_IRS, OP_SH_IRS): Delete. + (OP_MASK_ROP, OP_SH_ROP): Delete. + (OP_MASK_RRD, OP_SH_RRD): Delete. + (OP_MASK_RRT, OP_SH_RRT): Delete. + (OP_MASK_RRS, OP_SH_RRS): Delete. + (OP_MASK_JOP, OP_SH_JOP): Delete. + (OP_MASK_IMM26, OP_SH_IMM26): Delete. + (OP_MASK_RCTL, OP_SH_RCTL): Delete. + (OP_MASK_IMM5, OP_SH_IMM5): Delete. + (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete. + (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete. + (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete. + (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete. + (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete. + (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete. + (OP_, OPX_, OP_MATCH_, OPX_MATCH_): Delete. + (OP_MASK_, OP_MASK): Delete. + (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete. + (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete. + Include nios2r1.h to define new instruction opcode constants + and accessors. + (nios2_builtin_opcodes): Rename to nios2_r1_opcodes. + (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes. + (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes. + (NUMOPCODES, NUMREGISTERS): Delete. + * nios2r1.h: New file. + +2014-10-17 Jose E. Marchesi + + * sparc.h (HWCAP2_VIS3B): Documentation improved. + +2014-10-09 Jose E. Marchesi + + * sparc.h (sparc_opcode): new field `hwcaps2'. + (HWCAP2_FJATHPLUS): New define. + (HWCAP2_VIS3B): Likewise. + (HWCAP2_ADP): Likewise. + (HWCAP2_SPARC5): Likewise. + (HWCAP2_MWAIT): Likewise. + (HWCAP2_XMPMUL): Likewise. + (HWCAP2_XMONT): Likewise. + (HWCAP2_NSEC): Likewise. + (HWCAP2_FJATHHPC): Likewise. + (HWCAP2_FJDES): Likewise. + (HWCAP2_FJAES): Likewise. + Document the new operand kind `{', corresponding to the mcdper + ancillary state register. + Document the new operand kind }, which represents frsd floating + point registers (double precision) which must be the same than + frs1 in its containing instruction. + +2014-09-16 Kuan-Lin Chen + + * nds32.h: Add new opcode declaration. + +2014-09-15 Andrew Bennett + Matthew Fortune + + * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT, + OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6 + instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B, + +I, +O, +R, +:, +\, +", +; + (mips_check_prev_operand): New struct. + (INSN2_FORBIDDEN_SLOT): New define. + (INSN_ISA32R6): New define. + (INSN_ISA64R6): New define. + (INSN_UPTO32R6): New define. + (INSN_UPTO64R6): New define. + (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6. + (ISA_MIPS32R6): New define. + (ISA_MIPS64R6): New define. + (CPU_MIPS32R6): New define. + (CPU_MIPS64R6): New define. + (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6. + +2014-09-03 Jiong Wang + + * aarch64.h (AARCH64_FEATURE_LSE): New feature added. + (aarch64_opnd): Add AARCH64_OPND_PAIRREG. + (aarch64_insn_class): Add lse_atomic. + (F_LSE_SZ): New field added. + (opcode_has_special_coder): Recognize F_LSE_SZ. + +2014-08-26 Maciej W. Rozycki + + * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B' + over to `+J'. + +2014-07-29 Matthew Fortune + + * mips.h (INSN_LOAD_COPROC_DELAY): Rename to... + (INSN_LOAD_COPROC): New define. + (INSN_COPROC_MOVE_DELAY): Rename to... + (INSN_COPROC_MOVE): New define. + +2014-07-01 Barney Stratford + Senthil Kumar Selvaraj + Pitchumani Sivanupandi + Soundararajan + + * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA. + (AVR_ISA_2xxxa): Define ISA without LPM. + (AVR_ISA_AVRTINY): Define avrtiny arch ISA. + Add doc for contraint used in 16 bit lds/sts. + Adjust ISA group for icall, ijmp, pop and push. + Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints. + +2014-05-19 Nick Clifton + + * msp430.h (struct msp430_operand_s): Add vshift field. + +2014-05-07 Andrew Bennett + + * mips.h (INSN_ISA_MASK): Updated. + (INSN_ISA32R3): New define. + (INSN_ISA32R5): New define. + (INSN_ISA64R3): New define. + (INSN_ISA64R5): New define. + (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32 + INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered. + (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and + mips64r5. + (INSN_UPTO32R3): New define. + (INSN_UPTO32R5): New define. + (INSN_UPTO64R3): New define. + (INSN_UPTO64R5): New define. + (ISA_MIPS32R3): New define. + (ISA_MIPS32R5): New define. + (ISA_MIPS64R3): New define. + (ISA_MIPS64R5): New define. + (CPU_MIPS32R3): New define. + (CPU_MIPS32R5): New define. + (CPU_MIPS64R3): New define. + (CPU_MIPS64R5): New define. + +2014-05-01 Richard Sandiford + + * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values. + +2014-04-22 Christian Svensson + + * or32.h: Delete. + +2014-03-05 Alan Modra + + Update copyright years. + +2013-12-16 Andrew Bennett + + * mips.h: Updated description of +o, +u, +v and +w for MIPS and + microMIPS. + +2013-12-13 Kuan-Lin Chen + Wei-Cheng Wang + + * nds32.h: New file for Andes NDS32. + +2013-12-07 Mike Frysinger + + * bfin.h: Remove +x file mode. + +2013-11-20 Yufeng Zhang + + * aarch64.h (aarch64_pstatefields): Change element type to + aarch64_sys_reg. + +2013-11-18 Renlin Li + + * arm.h (ARM_AEXT_V7VE): New define. + (ARM_ARCH_V7VE): New define. + (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed. + +2013-11-18 Yufeng Zhang + + Revert + + 2013-11-15 Yufeng Zhang + + * aarch64.h (aarch64_sys_reg_readonly_p): New declaration. + (aarch64_sys_reg_writeonly_p): Ditto. + +2013-11-15 Yufeng Zhang + + * aarch64.h (aarch64_sys_reg_readonly_p): New declaration. + (aarch64_sys_reg_writeonly_p): Ditto. + +2013-11-05 Yufeng Zhang + + * aarch64.h (aarch64_sys_reg): New typedef. + (aarch64_sys_regs): Change to define with the new type. + (aarch64_sys_reg_deprecated_p): Declare. + +2013-11-05 Yufeng Zhang + + * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND. + (enum aarch64_opnd): Add AARCH64_OPND_COND1. + +2013-10-14 Chao-ying Fu + + * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX. + (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL. + For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, + +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. + For MIPS, update extension character sequences after +. + (ASE_MSA): New define. + (ASE_MSA64): New define. + For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, + +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|. + For microMIPS, update extension character sequences after +. + +2013-08-23 Yuri Chornoivan + + PR binutils/15834 + * i960.h: Fix typos. + +2013-08-19 Richard Sandiford + + * mips.h: Remove references to "+I" and imm2_expr. + +2013-08-19 Richard Sandiford + + * mips.h (M_DEXT, M_DINS): Delete. + +2013-08-19 Richard Sandiford + + * mips.h (OP_OPTIONAL_REG): New mips_operand_type. + (mips_optional_operand_p): New function. + +2013-08-04 Jürgen Urban + Richard Sandiford + + * mips.h: Document new VU0 operand characters. + (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types. + (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R) + (OP_REG_R5900_ACC): New mips_reg_operand_types. + (INSN2_VU0_CHANNEL_SUFFIX): New macro. + (mips_vu0_channel_mask): Declare. + +2013-08-03 Richard Sandiford + + * mips.h (mips_pcrel_operand): Inherit from mips_int_operand. + (mips_int_operand_min, mips_int_operand_max): New functions. + (mips_decode_pcrel_operand): Use mips_decode_int_operand. + +2013-08-01 Richard Sandiford + + * mips.h (mips_decode_reg_operand): New function. + (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL) + (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4) + (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI): + New macros. + (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D) + (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T) + (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S) + (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z) + (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D) + (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD) + (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG) + (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP) + (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP) + (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other + macros to cover the gaps. + (INSN2_MOD_SP): Replace with... + (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros. + (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z) + (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y) + (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z) + (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X): + Delete. + +2013-08-01 Richard Sandiford + + * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31) + (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH) + (MIPS16_INSN_COND_BRANCH): Delete. + +2013-07-24 Anna Tikhonova + Kirill Yukhin + Michael Zolotukhin + + * i386.h (BND_PREFIX_OPCODE): New. + +2013-07-14 Richard Sandiford + + * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and + OP_SAVE_RESTORE_LIST. + (decode_mips16_operand): Declare. + +2013-07-14 Richard Sandiford + + * mips.h (mips_operand_type, mips_reg_operand_type): New enums. + (mips_operand, mips_int_operand, mips_mapped_int_operand) + (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand) + (mips_pcrel_operand): New structures. + (mips_insert_operand, mips_extract_operand, mips_signed_operand) + (mips_decode_int_operand, mips_decode_pcrel_operand): New functions. + (decode_mips_operand, decode_micromips_operand): Declare. + +2013-07-14 Richard Sandiford + + * mips.h: Document MIPS16 "I" opcode. + +2013-07-07 Richard Sandiford + + * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB) + (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB) + (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A) + (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB) + (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB) + (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB) + (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB) + (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB) + (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A) + (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A) + (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB) + (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete. + (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A): + Rename to... + (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB) + (M_USD_AB): ...these. + +2013-07-07 Richard Sandiford + + * mips.h: Remove documentation of "[" and "]". Update documentation + of "k" and the MDMX formats. + +2013-07-07 Richard Sandiford + + * mips.h: Update documentation of "+s" and "+S". + +2013-07-07 Richard Sandiford + + * mips.h: Document "+i". + +2013-07-07 Richard Sandiford + + * mips.h: Remove "mi" documentation. Update "mh" documentation. + (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI): + Delete. + (INSN2_WRITE_GPR_MHI): Rename to... + (INSN2_WRITE_GPR_MH): ...this. + +2013-07-07 Richard Sandiford + + * mips.h: Remove documentation of "+D" and "+T". + 2013-06-26 Richard Sandiford * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT. @@ -117,7 +655,7 @@ * aarch64.h (AARCH64_FEATURE_CRC): New macro. 2013-02-06 Sandra Loosemore - Andrew Jenner + Andrew Jenner Based on patches from Altera Corporation. @@ -979,7 +1517,7 @@ 2008-04-28 Adam Nemet - * mips.h (INSN_MACRO): Move it up to the the pinfo macros. + * mips.h (INSN_MACRO): Move it up to the pinfo macros. (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros. 2008-04-14 Edmar Wienskoski @@ -1753,7 +2291,7 @@ For older changes see ChangeLog-9103 -Copyright (C) 2004-2012 Free Software Foundation, Inc. +Copyright (C) 2004-2015 Free Software Foundation, Inc. Copying and distribution of this file, with or without modification, are permitted in any medium without royalty provided the copyright