X-Git-Url: http://drtracing.org/?a=blobdiff_plain;ds=sidebyside;f=opcodes%2FChangeLog;h=19e27af1d39eb18cbe89c61be20aa587e63c7dc4;hb=dc821c5f9ae5208ad1ec438718f75e224f856deb;hp=10d9e638e8a2510a848d986fe67cabba7d2ec55e;hpb=f143cb5fc655e1ed0a6e15e6ba33af0d79ba1802;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 10d9e638e8..19e27af1d3 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,52 @@ +2017-12-18 Jan Beulich + + * i386-gen.c (operand_type_shorthands): New. + (opcode_modifiers): Replace Reg with just Reg. + (set_bitfield_from_cpu_flag_init): Rename to + set_bitfield_from_shorthand. Drop value parameter. Process + operand_type_shorthands. + (set_bitfield): Adjust call accordingly. + * i386-opc.h (enum of operand types): Replace Reg with just + Reg. + (union i386_operand_type): Replace reg with just reg. + * i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw, + vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into + separate register and memory forms. + * i386-reg.tbl (al): Drop Byte. + (ax): Drop Word. + (eax): Drop Dword. + (rax): Drop Qword. + * i386-init.h, i386-tbl.h: Re-generate. + +2017-12-15 Dimitar Dimitrov + + * disassemble.c (disassemble_init_for_target): Don't put PRU + between powerpc and rs6000 cases. + +2017-12-15 Jan Beulich + + * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov, + movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror, + sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto, + stos, sub, test, xor): Drop CheckRegSize from variants not + allowing for two (or more) register operands. + * i386-tbl.h: Re-generate. + +2017-12-13 Jim Wilson + + PR 22599 + * riscv-opc.c (riscv_opcodes) : New. + +2017-12-13 Dimitar Dimitrov + + * disassemble.c: Enable disassembler_needs_relocs for PRU. + +2017-12-11 Petr Pavlu + Renlin Li + + * aarch64-dis.c (print_insn_aarch64): Move symbol section check ... + (get_sym_code_type): Here. + 2017-12-03 Alan Modra * ppc-opc.c (extract_li20): Rewrite.