X-Git-Url: http://drtracing.org/?a=blobdiff_plain;ds=sidebyside;f=opcodes%2FChangeLog;h=2328f18f5e2acbc3a5faca6df341c80838aea94e;hb=b83b4b138298d2a6bfab11f533d7e315c0a1c97b;hp=5027e9a573fb6b7db4b749d94e1068a363f2caa6;hpb=031254f2111f945ce6a1b8827e1a58ed7141fefe;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5027e9a573..2328f18f5e 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,104 @@
+2019-05-01  Sudakshina Das  <sudi.das@arm.com>
+
+	* aarch64-asm-2.c: Regenerated.
+	* aarch64-dis-2.c: Regenerated.
+	* aarch64-opc-2.c: Regenerated.
+	* aarch64-opc.c (operand_general_constraint_met_p): Add case for
+	AARCH64_OPND_TME_UIMM16.
+	(aarch64_print_operand): Likewise.
+	* aarch64-tbl.h (QL_IMM_NIL): New.
+	(TME): New.
+	(_TME_INSN): New.
+	(struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
+
+2019-04-29  John Darrington  <john@darrington.wattle.id.au>
+
+        * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
+
+2019-04-26  Andrew Bennett  <andrew.bennett@imgtec.com>
+	    Faraz Shahbazker  <fshahbazker@wavecomp.com>
+
+	* mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
+
+2019-04-24  John Darrington  <john@darrington.wattle.id.au>
+
+        * s12z-opc.h: Add extern "C" bracketing to help
+	users who wish to use this interface in c++ code.
+
+2019-04-24  John Darrington  <john@darrington.wattle.id.au>
+
+	* s12z-opc.c (bm_decode): Handle bit map operations with the
+	"reserved0" mode.
+
+2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* arm-dis.c (coprocessor_opcodes): Document new %J and %K format
+	specifier.  Add entries for VLDR and VSTR of system registers.
+	(print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
+	coprocessor instructions on Armv8.1-M Mainline targets.  Add handling
+	of %J and %K format specifier.
+
+2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* arm-dis.c (coprocessor_opcodes): Document new %C format control code.
+	Add new entries for VSCCLRM instruction.
+	(print_insn_coprocessor): Handle new %C format control code.
+
+2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* arm-dis.c (enum isa): New enum.
+	(struct sopcode32): New structure.
+	(coprocessor_opcodes): change type of entries to struct sopcode32 and
+	set isa field of all current entries to ANY.
+	(print_insn_coprocessor): Change type of insn to struct sopcode32.
+	Only match an entry if its isa field allows the current mode.
+
+2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
+
+	* arm-dis.c (thumb_opcodes): Document %n control code.  Add entry for
+	CLRM.
+	(print_insn_thumb32): Add logic to print %n CLRM register list.
+
+2019-04-15  Sudakshina Das  <sudi.das@arm.com>
+
+	* arm-dis.c (print_insn_thumb32): Updated to accept new %P
+	and %Q patterns.
+
+2019-04-15  Sudakshina Das  <sudi.das@arm.com>
+
+	* arm-dis.c (thumb32_opcodes): New instruction bfcsel.
+	(print_insn_thumb32): Edit the switch case for %Z.
+
+2019-04-15  Sudakshina Das  <sudi.das@arm.com>
+
+	* arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
+
+2019-04-15  Sudakshina Das  <sudi.das@arm.com>
+
+	* arm-dis.c (thumb32_opcodes): New instruction bfl.
+
+2019-04-15  Sudakshina Das  <sudi.das@arm.com>
+
+	* arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
+
+2019-04-15  Sudakshina Das  <sudi.das@arm.com>
+
+	* arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
+	Arm register with r13 and r15 unpredictable.
+	(thumb32_opcodes): New instructions for bfx and bflx.
+
+2019-04-15  Sudakshina Das  <sudi.das@arm.com>
+
+	* arm-dis.c (thumb32_opcodes): New instructions for bf.
+
+2019-04-15  Sudakshina Das  <sudi.das@arm.com>
+
+	* arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
+
+2019-04-15  Sudakshina Das  <sudi.das@arm.com>
+
+	* arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
+
 2019-04-15  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 
 	* arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.