X-Git-Url: http://drtracing.org/?a=blobdiff_plain;ds=sidebyside;f=opcodes%2FChangeLog;h=4c748af9be1e6c1d12c2d46d0d3ec7d012c2000c;hb=920d2ddccb72a366140ed28283165b274f7a9045;hp=2b93ed22864789bedf7cb5a4681cf62294c04788;hpb=da8d7d665521e5b3f67f87341400441a5d0643d5;p=deliverable%2Fbinutils-gdb.git

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2b93ed2286..4c748af9be 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,59 @@
+2016-11-02  Igor Tsimbalist  <igor.v.tsimbalist@intel.com>
+
+	* i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
+	PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
+	* i386-dis-evex.h (evex_table): Updated.
+	* i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
+	CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
+	(cpu_flags): Add CpuAVX512_4FMAPS.
+	(opcode_modifiers): Add ImplicitQuadGroup modifier.
+	* i386-opc.h (AVX512_4FMAP): New.
+	(i386_cpu_flags): Add cpuavx512_4fmaps.
+	(ImplicitQuadGroup): New.
+	(i386_opcode_modifier): Add implicitquadgroup.
+	* i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
+	* i386-init.h: Regenerate.
+	* i386-tbl.h: Ditto.
+
+2016-11-01  Palmer Dabbelt  <palmer@dabbelt.com>
+	    Andrew Waterman <andrew@sifive.com>
+
+	Add support for RISC-V architecture.
+	* configure.ac: Add entry for bfd_riscv_arch.
+	* configure: Regenerate.
+	* disassemble.c (disassembler): Add support for riscv.
+	(disassembler_usage): Likewise.
+	* riscv-dis.c: New file.
+	* riscv-opc.c: New file.
+
+2016-10-21  H.J. Lu  <hongjiu.lu@intel.com>
+
+	* i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
+	(prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
+	(rm_table): Update the RM_0FAE_REG_7 entry.
+	* i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
+	(cpu_flags): Remove CpuPCOMMIT.
+	* i386-opc.h (CpuPCOMMIT): Removed.
+	(i386_cpu_flags): Remove cpupcommit.
+	* i386-opc.tbl: Remove pcommit.
+	* i386-init.h: Regenerated.
+	* i386-tbl.h: Likewise.
+
+2016-10-20  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutis/20705
+	* i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
+	the highest bit in VEX.vvvv for the 3-byte VEX prefix in
+	32-bit mode.  Don't check vex.register_specifier in 32-bit
+	mode.
+	(OP_VEX): Check for invalid mask registers.
+
+2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
+
+	PR binutis/20699
+	* i386-dis.c (OP_E_memory): Check addr32flag in stead of
+	sizeflag.
+
 2016-10-18  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR binutis/20704