X-Git-Url: http://drtracing.org/?a=blobdiff_plain;ds=sidebyside;f=opcodes%2FChangeLog;h=571dd3de3ecf18daf26c7ccc78afb559f34dbbdc;hb=c507f10b0711f24e1b82b8bd096e605317cf77fe;hp=d17ee102202344ec0da6d69cf7d8eded5dd5e8ec;hpb=39f286cd585226ad98c2cd94ee0f96988b3696ce;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index d17ee10220..571dd3de3e 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,6 +1,695 @@ +2019-05-16 Andre Vieira + Michael Collison + + * arm-dis.c (enum mve_instructions): Add new instructions. + (enum mve_unpredictable): Add new reasons. + (enum mve_undefined): Likewise. + (is_mve_okay_in_it): Handle new isntructions. + (is_mve_encoding_conflict): Likewise. + (is_mve_undefined): Likewise. + (is_mve_unpredictable): Likewise. + (print_mve_vmov_index): Likewise. + (print_simd_imm8): Likewise. + (print_mve_undefined): Likewise. + (print_mve_unpredictable): Likewise. + (print_mve_size): Likewise. + (print_insn_mve): Likewise. + +2019-05-16 Andre Vieira + Michael Collison + + * arm-dis.c (enum mve_instructions): Add new instructions. + (enum mve_unpredictable): Add new reasons. + (enum mve_undefined): Likewise. + (is_mve_encoding_conflict): Handle new instructions. + (is_mve_undefined): Likewise. + (is_mve_unpredictable): Likewise. + (print_mve_undefined): Likewise. + (print_mve_unpredictable): Likewise. + (print_mve_rounding_mode): Likewise. + (print_mve_vcvt_size): Likewise. + (print_mve_size): Likewise. + (print_insn_mve): Likewise. + +2019-05-16 Andre Vieira + Michael Collison + + * arm-dis.c (enum mve_instructions): Add new instructions. + (enum mve_unpredictable): Add new reasons. + (enum mve_undefined): Likewise. + (is_mve_undefined): Handle new instructions. + (is_mve_unpredictable): Likewise. + (print_mve_undefined): Likewise. + (print_mve_unpredictable): Likewise. + (print_mve_size): Likewise. + (print_insn_mve): Likewise. + +2019-05-16 Andre Vieira + Michael Collison + + * arm-dis.c (enum mve_instructions): Add new instructions. + (enum mve_undefined): Add new reasons. + (insns): Add new instructions. + (is_mve_encoding_conflict): + (print_mve_vld_str_addr): New print function. + (is_mve_undefined): Handle new instructions. + (is_mve_unpredictable): Likewise. + (print_mve_undefined): Likewise. + (print_mve_size): Likewise. + (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions. + (print_insn_mve): Handle new operands. + +2019-05-16 Andre Vieira + Michael Collison + + * arm-dis.c (enum mve_instructions): Add new instructions. + (enum mve_unpredictable): Add new reasons. + (is_mve_encoding_conflict): Handle new instructions. + (is_mve_unpredictable): Likewise. + (mve_opcodes): Add new instructions. + (print_mve_unpredictable): Handle new reasons. + (print_mve_register_blocks): New print function. + (print_mve_size): Handle new instructions. + (print_insn_mve): Likewise. + +2019-05-16 Andre Vieira + Michael Collison + + * arm-dis.c (enum mve_instructions): Add new instructions. + (enum mve_unpredictable): Add new reasons. + (enum mve_undefined): Likewise. + (is_mve_encoding_conflict): Handle new instructions. + (is_mve_undefined): Likewise. + (is_mve_unpredictable): Likewise. + (coprocessor_opcodes): Move NEON VDUP from here... + (neon_opcodes): ... to here. + (mve_opcodes): Add new instructions. + (print_mve_undefined): Handle new reasons. + (print_mve_unpredictable): Likewise. + (print_mve_size): Handle new instructions. + (print_insn_neon): Handle vdup. + (print_insn_mve): Handle new operands. + +2019-05-16 Andre Vieira + Michael Collison + + * arm-dis.c (enum mve_instructions): Add new instructions. + (enum mve_unpredictable): Add new values. + (mve_opcodes): Add new instructions. + (vec_condnames): New array with vector conditions. + (mve_predicatenames): New array with predicate suffixes. + (mve_vec_sizename): New array with vector sizes. + (enum vpt_pred_state): New enum with vector predication states. + (struct vpt_block): New struct type for vpt blocks. + (vpt_block_state): Global struct to keep track of state. + (mve_extract_pred_mask): New helper function. + (num_instructions_vpt_block): Likewise. + (mark_outside_vpt_block): Likewise. + (mark_inside_vpt_block): Likewise. + (invert_next_predicate_state): Likewise. + (update_next_predicate_state): Likewise. + (update_vpt_block_state): Likewise. + (is_vpt_instruction): Likewise. + (is_mve_encoding_conflict): Add entries for new instructions. + (is_mve_unpredictable): Likewise. + (print_mve_unpredictable): Handle new cases. + (print_instruction_predicate): Likewise. + (print_mve_size): New function. + (print_vec_condition): New function. + (print_insn_mve): Handle vpt blocks and new print operands. + +2019-05-16 Andre Vieira + + * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors + 8, 14 and 15 for Armv8.1-M Mainline. + +2019-05-16 Andre Vieira + Michael Collison + + * arm-dis.c (enum mve_instructions): New enum. + (enum mve_unpredictable): Likewise. + (enum mve_undefined): Likewise. + (struct mopcode32): New struct. + (is_mve_okay_in_it): New function. + (is_mve_architecture): Likewise. + (arm_decode_field): Likewise. + (arm_decode_field_multiple): Likewise. + (is_mve_encoding_conflict): Likewise. + (is_mve_undefined): Likewise. + (is_mve_unpredictable): Likewise. + (print_mve_undefined): Likewise. + (print_mve_unpredictable): Likewise. + (print_insn_coprocessor_1): Use arm_decode_field_multiple. + (print_insn_mve): New function. + (print_insn_thumb32): Handle MVE architecture. + (select_arm_features): Force thumb for Armv8.1-m Mainline. + +2019-05-10 Nick Clifton + + PR 24538 + * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the + end of the table prematurely. + +2019-05-10 Faraz Shahbazker + + * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB + macros for R6. + +2019-05-11 Alan Modra + + * ppc-dis.c (print_insn_powerpc) Don't skip optional operands + when -Mraw is in effect. + +2019-05-09 Matthew Malcomson + + * aarch64-dis-2.c: Regenerate. + * aarch64-tbl.h (OP_SVE_BBU): New variant set. + (OP_SVE_BBB): New variant set. + (OP_SVE_DDDD): New variant set. + (OP_SVE_HHH): New variant set. + (OP_SVE_HHHU): New variant set. + (OP_SVE_SSS): New variant set. + (OP_SVE_SSSU): New variant set. + (OP_SVE_SHH): New variant set. + (OP_SVE_SBBU): New variant set. + (OP_SVE_DSS): New variant set. + (OP_SVE_DHHU): New variant set. + (OP_SVE_VMV_HSD_BHS): New variant set. + (OP_SVE_VVU_HSD_BHS): New variant set. + (OP_SVE_VVVU_SD_BH): New variant set. + (OP_SVE_VVVU_BHSD): New variant set. + (OP_SVE_VVV_QHD_DBS): New variant set. + (OP_SVE_VVV_HSD_BHS): New variant set. + (OP_SVE_VVV_HSD_BHS2): New variant set. + (OP_SVE_VVV_BHS_HSD): New variant set. + (OP_SVE_VV_BHS_HSD): New variant set. + (OP_SVE_VVV_SD): New variant set. + (OP_SVE_VVU_BHS_HSD): New variant set. + (OP_SVE_VZVV_SD): New variant set. + (OP_SVE_VZVV_BH): New variant set. + (OP_SVE_VZV_SD): New variant set. + (aarch64_opcode_table): Add sve2 instructions. + +2019-05-09 Matthew Malcomson + + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking + for SVE_SHLIMM_UNPRED_22. + (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. + * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 + operand. + +2019-05-09 Matthew Malcomson + + * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle + sve_size_tsz_bhs iclass encode. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle + sve_size_tsz_bhs iclass decode. + +2019-05-09 Matthew Malcomson + + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking + for SVE_Zm4_11_INDEX. + (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. + (fields): Handle SVE_i2h field. + * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. + * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand. + +2019-05-09 Matthew Malcomson + + * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle + sve_shift_tsz_bhsd iclass encode. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle + sve_shift_tsz_bhsd iclass decode. + +2019-05-09 Matthew Malcomson + + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + * aarch64-asm.c (aarch64_ins_sve_shrimm): + (aarch64_encode_variant_using_iclass): Handle + sve_shift_tsz_hsd iclass encode. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle + sve_shift_tsz_hsd iclass decode. + * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking + for SVE_SHRIMM_UNPRED_22. + (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. + * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 + operand. + +2019-05-09 Matthew Malcomson + + * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle + sve_size_013 iclass encode. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle + sve_size_013 iclass decode. + +2019-05-09 Matthew Malcomson + + * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle + sve_size_bh iclass encode. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle + sve_size_bh iclass decode. + +2019-05-09 Matthew Malcomson + + * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle + sve_size_sd2 iclass encode. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle + sve_size_sd2 iclass decode. + * aarch64-opc.c (fields): Handle SVE_sz2 field. + * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field. + +2019-05-09 Matthew Malcomson + + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking + for SVE_ADDR_ZX. + (aarch64_print_operand): Add printing for SVE_ADDR_ZX. + * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand. + +2019-05-09 Matthew Malcomson + + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking + for SVE_Zm3_11_INDEX. + (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. + (fields): Handle SVE_i3l and SVE_i3h2 fields. + * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 + fields. + * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand. + +2019-05-09 Matthew Malcomson + + * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle + sve_size_hsd2 iclass encode. + * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle + sve_size_hsd2 iclass decode. + * aarch64-opc.c (fields): Handle SVE_size field. + * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field. + +2019-05-09 Matthew Malcomson + + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking + for SVE_IMM_ROT3. + (aarch64_print_operand): Add printing for SVE_IMM_ROT3. + (fields): Handle SVE_rot3 field. + * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. + * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand. + +2019-05-09 Matthew Malcomson + + * aarch64-opc.c (verify_constraints): Check for movprfx for sve2 + instructions. + +2019-05-09 Matthew Malcomson + + * aarch64-tbl.h + (aarch64_feature_sve2, aarch64_feature_sve2aes, + aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, + aarch64_feature_sve2bitperm): New feature sets. + (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros + for feature set addresses. + (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, + SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros. + +2019-05-06 Andrew Bennett + Faraz Shahbazker + + * mips-dis.c (mips_calculate_combination_ases): Add ISA + argument and set ASE_EVA_R6 appropriately. + (set_default_mips_dis_options): Pass ISA to above. + (parse_mips_dis_option): Likewise. + * mips-opc.c (EVAR6): New macro. + (mips_builtin_opcodes): Add llwpe, scwpe. + +2019-05-01 Sudakshina Das + + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + * aarch64-opc.c (operand_general_constraint_met_p): Add case for + AARCH64_OPND_TME_UIMM16. + (aarch64_print_operand): Likewise. + * aarch64-tbl.h (QL_IMM_NIL): New. + (TME): New. + (_TME_INSN): New. + (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel. + +2019-04-29 John Darrington + + * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. + +2019-04-26 Andrew Bennett + Faraz Shahbazker + + * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp. + +2019-04-24 John Darrington + + * s12z-opc.h: Add extern "C" bracketing to help + users who wish to use this interface in c++ code. + +2019-04-24 John Darrington + + * s12z-opc.c (bm_decode): Handle bit map operations with the + "reserved0" mode. + +2019-04-15 Thomas Preud'homme + + * arm-dis.c (coprocessor_opcodes): Document new %J and %K format + specifier. Add entries for VLDR and VSTR of system registers. + (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in + coprocessor instructions on Armv8.1-M Mainline targets. Add handling + of %J and %K format specifier. + +2019-04-15 Thomas Preud'homme + + * arm-dis.c (coprocessor_opcodes): Document new %C format control code. + Add new entries for VSCCLRM instruction. + (print_insn_coprocessor): Handle new %C format control code. + +2019-04-15 Thomas Preud'homme + + * arm-dis.c (enum isa): New enum. + (struct sopcode32): New structure. + (coprocessor_opcodes): change type of entries to struct sopcode32 and + set isa field of all current entries to ANY. + (print_insn_coprocessor): Change type of insn to struct sopcode32. + Only match an entry if its isa field allows the current mode. + +2019-04-15 Thomas Preud'homme + + * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for + CLRM. + (print_insn_thumb32): Add logic to print %n CLRM register list. + +2019-04-15 Sudakshina Das + + * arm-dis.c (print_insn_thumb32): Updated to accept new %P + and %Q patterns. + +2019-04-15 Sudakshina Das + + * arm-dis.c (thumb32_opcodes): New instruction bfcsel. + (print_insn_thumb32): Edit the switch case for %Z. + +2019-04-15 Sudakshina Das + + * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern. + +2019-04-15 Sudakshina Das + + * arm-dis.c (thumb32_opcodes): New instruction bfl. + +2019-04-15 Sudakshina Das + + * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern. + +2019-04-15 Sudakshina Das + + * arm-dis.c (print_insn_thumb32): Add '%S' to print an + Arm register with r13 and r15 unpredictable. + (thumb32_opcodes): New instructions for bfx and bflx. + +2019-04-15 Sudakshina Das + + * arm-dis.c (thumb32_opcodes): New instructions for bf. + +2019-04-15 Sudakshina Das + + * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern. + +2019-04-15 Sudakshina Das + + * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern. + +2019-04-15 Thomas Preud'homme + + * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline. + +2019-04-12 John Darrington + + s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with + "optr". ("operator" is a reserved word in c++). + +2019-04-11 Sudakshina Das + + * aarch64-opc.c (aarch64_print_operand): Add case for + AARCH64_OPND_Rt_SP. + (verify_constraints): Likewise. + * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. + (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions + to accept Rt|SP as first operand. + (AARCH64_OPERANDS): Add new Rt_SP. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2019-04-11 Sudakshina Das + + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Likewise. + * aarch64-opc-2.c: Likewise. + * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm. + +2019-04-09 Robert Suchanek + + * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. + +2019-04-08 H.J. Lu + + * i386-opc.tbl: Consolidate AVX512 BF16 entries. + * i386-init.h: Regenerated. + +2019-04-07 Alan Modra + + * ppc-dis.c (print_insn_powerpc): Use a tiny state machine + op_separator to control printing of spaces, comma and parens + rather than need_comma, need_paren and spaces vars. + +2019-04-07 Alan Modra + + PR 24421 + * arm-dis.c (print_insn_coprocessor): Correct bracket placement. + (print_insn_neon, print_insn_arm): Likewise. + +2019-04-05 Xuepeng Guo + + * i386-dis-evex.h (evex_table): Updated to support BF16 + instructions. + * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 + and EVEX_W_0F3872_P_3. + * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. + (cpu_flags): Add bitfield for CpuAVX512_BF16. + * i386-opc.h (enum): Add CpuAVX512_BF16. + (i386_cpu_flags): Add bitfield for cpuavx512_bf16. + * i386-opc.tbl: Add AVX512 BF16 instructions. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2019-04-05 Alan Modra + + * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK. + (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics + to favour printing of "-" branch hint when using the "y" bit. + Allow BH field on bc{ctr,lr,tar}{,l}{-,+}. + +2019-04-05 Alan Modra + + * ppc-dis.c (print_insn_powerpc): Delay printing spaces after + opcode until first operand is output. + +2019-04-04 Peter Bergner + + PR gas/24349 + * ppc-opc.c (valid_bo_pre_v2): Add comments. + (valid_bo_post_v2): Add support for 'at' branch hints. + (insert_bo): Only error on branch on ctr. + (get_bo_hint_mask): New function. + (insert_boe): Add new 'branch_taken' formal argument. Add support + for inserting 'at' branch hints. + (extract_boe): Add new 'branch_taken' formal argument. Add support + for extracting 'at' branch hints. + (insert_bom, extract_bom, insert_bop, extract_bop): New functions. + (BOE): Delete operand. + (BOM, BOP): New operands. + (RM): Update value. + (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. + (powerpc_opcodes) : Replace BOE with BOM. + (powerpc_opcodes) : Replace BOE with BOP. + : New extended mnemonics. + +2019-03-28 Alan Modra + + PR 24390 + * ppc-opc.c (BTF): Define. + (powerpc_opcodes): Use for mtfsb*. + * ppc-dis.c (print_insn_powerpc): Print fields with both + PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. + +2019-03-25 Tamar Christina + + * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols. + (mapping_symbol_for_insn): Implement new algorithm. + (print_insn): Remove duplicate code. + +2019-03-25 Tamar Christina + + * aarch64-dis.c (print_insn_aarch64): + Implement override. + +2019-03-25 Tamar Christina + + * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search + order. + +2019-03-25 Tamar Christina + + * aarch64-dis.c (last_stop_offset): New. + (print_insn_aarch64): Use stop_offset. + +2019-03-19 H.J. Lu + + PR gas/24359 + * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to + CPU_ANY_AVX2_FLAGS. + * i386-init.h: Regenerated. + +2019-03-18 H.J. Lu + + PR gas/24348 + * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, + vmovdqu16, vmovdqu32 and vmovdqu64. + * i386-tbl.h: Regenerated. + +2019-03-12 Andreas Krebbel + + * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand + from vstrszb, vstrszh, and vstrszf. + +2019-03-12 Andreas Krebbel + + * s390-opc.txt: Add instruction descriptions. + +2019-02-08 Jim Wilson + + * riscv-opc.c (riscv_opcodes) : Use Cz to compress 3 operand form. + : Likewise. + +2019-02-07 Tamar Christina + + * arm-dis.c (arm_opcodes): Redefine hlt to armv1. + +2019-02-07 Tamar Christina + + PR binutils/23212 + * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. + * aarch64-opc.c (verify_elem_sd): New. + (fields): Add FLD_sz entr. + * aarch64-tbl.h (_SIMD_INSN): New. + (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and + fmulx scalar and vector by element isns. + +2019-02-07 Nick Clifton + + * po/sv.po: Updated Swedish translation. + +2019-01-31 Andreas Krebbel + + * s390-mkopc.c (main): Accept arch13 as cpu string. + * s390-opc.c: Add new instruction formats and instruction opcode + masks. + * s390-opc.txt: Add new arch13 instructions. + +2019-01-25 Sudakshina Das + + * aarch64-tbl.h (QL_LDST_AT): Update macro. + (aarch64_opcode): Change encoding for stg, stzg + st2g and st2zg. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2019-01-25 Sudakshina Das + + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Likewise. + * aarch64-opc-2.c: Likewise. + * aarch64-tbl.h (aarch64_opcode): Add new stzgm. + +2019-01-25 Sudakshina Das + Ramana Radhakrishnan + + * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. + * aarch64-asm.h (ins_addr_simple_2): Likeiwse. + * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. + * aarch64-dis.h (ext_addr_simple_2): Likewise. + * aarch64-opc.c (operand_general_constraint_met_p): Remove + case for ldstgv_indexed. + (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. + * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. + (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. + * aarch64-asm-2.c: Regenerated. + * aarch64-dis-2.c: Regenerated. + * aarch64-opc-2.c: Regenerated. + +2019-01-23 Nick Clifton + + * po/pt_BR.po: Updated Brazilian Portuguese translation. + +2019-01-21 Nick Clifton + + * po/de.po: Updated German translation. + * po/uk.po: Updated Ukranian translation. + +2019-01-20 Chenghua Xu + * mips-dis.c (mips_arch_choices): Fix typo in + gs464, gs464e and gs264e descriptors. + +2019-01-19 Nick Clifton + + * configure: Regenerate. + * po/opcodes.pot: Regenerate. + +2018-06-24 Nick Clifton + + 2.32 branch created. + 2019-01-09 John Darrington - * s12z-dis.c (opr_emit_disassembly): Do not omit an index if it is + * s12z-dis.c (print_insn_s12z): Do not dereference an operand + if it is null. + -dis.c (opr_emit_disassembly): Do not omit an index if it is zero. 2019-01-09 Andrew Paprocki