X-Git-Url: http://drtracing.org/?a=blobdiff_plain;ds=sidebyside;f=opcodes%2FChangeLog;h=92b7c4de1b9b1b2d401a03406e05f739ca231ca4;hb=79bffa3b90933d33390cb28b810bea5980a5e42a;hp=99c7a93000283b65836d2c18aaad3a46417c0af2;hpb=7b6d09fbc60b12c196b25a9ebbb77ddc24e06334;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 99c7a93000..92b7c4de1b 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,494 @@ +2015-11-11 Alan Modra + Peter Bergner + + * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. + Add PPC_OPCODE_VSX3 to the vsx entry. + (powerpc_init_dialect): Set default dialect to power9. + * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, + insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, + extract_l1 insert_xtq6, extract_xtq6): New static functions. + (insert_esync): Test for illegal L operand value. + (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, + XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, + XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, + XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, + PPCVSX3): New defines. + (powerpc_opcodes) : Use XBF_MASK. + : Use XBFRARB_MASK. + : New instructions. + : Disable on POWER9. + : Add additional operands. + +2015-11-02 Nick Clifton + + * rx-decode.opc (rx_decode_opcode): Decode extra NOP + instructions. + * rx-decode.c: Regenerate. + +2015-11-02 Nick Clifton + + * rx-decode.opc (rx_disp): If the displacement is zero, set the + type to RX_Operand_Zero_Indirect. + * rx-decode.c: Regenerate. + * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect. + +2015-10-28 Yao Qi + + * aarch64-dis.c (aarch64_decode_insn): Add one argument + noaliases_p. Update comments. Pass noaliases_p rather than + no_aliases to aarch64_opcode_decode. + (print_insn_aarch64_word): Pass no_aliases to + aarch64_decode_insn. + +2015-10-27 Vinay + + PR binutils/19159 + * rl78-decode.opc (MOV): Added offset to DE register in index + addressing mode. + * rl78-decode.c: Regenerate. + +2015-10-27 Vinay Kumar + + PR binutils/19158 + * rl78-decode.opc: Add 's' print operator to instructions that + access system registers. + * rl78-decode.c: Regenerate. + * rl78-dis.c (print_insn_rl78_common): Decode all system + registers. + +2015-10-27 Vinay Kumar + + PR binutils/19157 + * rl78-decode.opc: Add 'a' print operator to mov instructions + using stack pointer plus index addressing. + * rl78-decode.c: Regenerate. + +2015-10-14 Andreas Krebbel + + * s390-opc.c: Fix comment. + * s390-opc.txt: Change instruction type for troo, trot, trto, and + trtt to RRF_U0RER since the second parameter does not need to be a + register pair. + +2015-10-08 Nick Clifton + + * arc-dis.c (print_insn_arc): Initiallise insn array. + +2015-10-07 Yao Qi + + * aarch64-dis.c (aarch64_ext_sysins_op): Access field + 'name' rather than 'template'. + * aarch64-opc.c (aarch64_print_operand): Likewise. + +2015-10-07 Claudiu Zissulescu + + * arc-dis.c: Revamped file for ARC support + * arc-dis.h: Likewise. + * arc-ext.c: Likewise. + * arc-ext.h: Likewise. + * arc-opc.c: Likewise. + * arc-fxi.h: New file. + * arc-regs.h: Likewise. + * arc-tbl.h: Likewise. + +2015-10-02 Yao Qi + + * aarch64-dis.c (disas_aarch64_insn): Remove static. Change + argument insn type to aarch64_insn. Rename to ... + (aarch64_decode_insn): ... it. + (print_insn_aarch64_word): Caller updated. + +2015-10-02 Yao Qi + + * aarch64-dis.c (disas_aarch64_insn): Remove argument PC. + (print_insn_aarch64_word): Caller updated. + +2015-09-29 Dominik Vogt + + * s390-mkopc.c (main): Parse htm and vx flag. + * s390-opc.txt: Mark instructions from the hardware transactional + memory and vector facilities with the "htm"/"vx" flag. + +2015-09-28 Nick Clifton + + * po/de.po: Updated German translation. + +2015-09-28 Tom Rix + + * ppc-opc.c (PPC500): Mark some opcodes as invalid + +2015-09-23 Nick Clifton + + * bfin-dis.c (fmtconst): Remove unnecessary call to the abs + function. + * tic30-dis.c (print_branch): Likewise. + * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed + value before left shifting. + * fr30-ibld.c (fr30_cgen_extract_operand): Likewise. + * hppa-dis.c (print_insn_hppa): Likewise. + * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static + array. + * msp430-dis.c (msp430_singleoperand): Likewise. + (msp430_doubleoperand): Likewise. + (print_insn_msp430): Likewise. + * nds32-asm.c (parse_operand): Likewise. + * sh-opc.h (MASK): Likewise. + * v850-dis.c (get_operand_value): Likewise. + +2015-09-22 Nick Clifton + + * rx-decode.opc (bwl): Use RX_Bad_Size. + (sbwl): Likewise. + (ubwl): Likewise. Rename to ubw. + (uBWL): Rename to uBW. + Replace all references to uBWL with uBW. + * rx-decode.c: Regenerate. + * rx-dis.c (size_names): Add entry for RX_Bad_Size. + (opsize_names): Likewise. + (print_insn_rx): Detect and report RX_Bad_Size. + +2015-09-22 Anton Blanchard + + * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl. + +2015-08-25 Jose E. Marchesi + + * sparc-dis.c (print_insn_sparc): Handle the privileged register + %pmcdper. + +2015-08-24 Jan Stancek + + * i386-dis.c (print_insn): Fix decoding of three byte operands. + +2015-08-21 Alexander Fomin + + PR binutils/18257 + * i386-dis.c: Use MOD_TABLE for most of mask instructions. + (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1, + MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, + MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, + MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, + MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, + MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, + MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, + MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, + MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, + MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, + MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, + MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, + MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, + MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, + MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, + MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, + MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, + MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, + MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, + MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0, + MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0, + MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0, + MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, + MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, + MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, + MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, + MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0, + MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0, + MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0, + MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0. + (vex_w_table): Replace terminals with MOD_TABLE entries for + most of mask instructions. + +2015-08-17 Alan Modra + + * cgen.sh: Trim trailing space from cgen output. + * ia64-gen.c (print_dependency_table): Don't generate trailing space. + (print_dis_table): Likewise. + * opc2c.c (dump_lines): Likewise. + (orig_filename): Warning fix. + * ia64-asmtab.c: Regenerate. + +2015-08-13 Andre Vieira + + * arm-dis.c (print_insn_arm): Disassembling for all targets V6 + and higher with ARM instruction set will now mark the 26-bit + versions of teq,tst,cmn and cmp as UNPREDICTABLE. + (arm_opcodes): Fix for unpredictable nop being recognized as a + teq. + +2015-08-12 Simon Dardis + + * micromips-opc.c (micromips_opcodes): Re-order table so that move + based on 'or' is first. + * mips-opc.c (mips_builtin_opcodes): Ditto. + +2015-08-11 Nick Clifton + + PR 18800 + * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT + instruction. + +2015-08-10 Robert Suchanek + + * mips-opc.c (mips_builtin_opcodes): Add "sigrie". + +2015-08-07 Amit Pawar + + * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS. + * i386-init.h: Regenerated. + +2015-07-30 H.J. Lu + + PR binutils/13571 + * i386-dis.c (MOD_0FC3): New. + (PREFIX_0FC3): Renamed to ... + (PREFIX_MOD_0_0FC3): This. + (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3. + (prefix_table): Replace Ma with Ev on movntiS. + (mod_table): Add MOD_0FC3. + +2015-07-27 H.J. Lu + + * configure: Regenerated. + +2015-07-23 Alan Modra + + PR 18708 + * i386-dis.c (get64): Avoid signed integer overflow. + +2015-07-22 Alexander Fomin + + PR binutils/18631 + * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with + "EXEvexHalfBcstXmmq" for the second operand. + (EVEX_W_0F79_P_2): Likewise. + (EVEX_W_0F7A_P_2): Likewise. + (EVEX_W_0F7B_P_2): Likewise. + +2015-07-16 Alessandro Marzocchi + + * arm-dis.c (print_insn_coprocessor): Added support for quarter + float bitfield format. + (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new + quarter float bitfield format. + +2015-07-14 H.J. Lu + + * configure: Regenerated. + +2015-07-03 Alan Modra + + * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*. + * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add + PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry. + +2015-07-01 Sandra Loosemore + Cesar Philippidis + + * nios2-dis.c (nios2_extract_opcode): New. + (nios2_disassembler_state): New. + (nios2_find_opcode_hash): Use mach parameter to select correct + disassembler state. + (nios2_print_insn_arg): Extend to support new R2 argument letters + and formats. + (print_insn_nios2): Check for 16-bit instruction at end of memory. + * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes. + (NIOS2_NUM_OPCODES): Rename to... + (NIOS2_NUM_R1_OPCODES): This. + (nios2_r2_opcodes): New. + (NIOS2_NUM_R2_OPCODES): New. + (nios2_num_r2_opcodes): New. + (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New. + (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New. + (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New. + (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New. + (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New. + +2015-06-30 Amit Pawar + + * i386-dis.c (OP_Mwaitx): New. + (rm_table): Add monitorx/mwaitx. + * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS + and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS. + (operand_type_init): Add CpuMWAITX. + * i386-opc.h (CpuMWAITX): New. + (i386_cpu_flags): Add cpumwaitx. + * i386-opc.tbl: Add monitorx and mwaitx. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2015-06-22 Peter Bergner + + * ppc-opc.c (insert_ls): Test for invalid LS operands. + (insert_esync): New function. + (LS, WC): Use insert_ls. + (ESYNC): Use insert_esync. + +2015-06-22 Nick Clifton + + * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the + requested region lies beyond it. + * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when + looking for 32-bit insns. + * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading + data. + * sh-dis.c (print_insn_sh): Likewise. + * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading + blocks of instructions. + * vax-dis.c (print_insn_vax): Check that the requested address + does not clash with the stop_vma. + +2015-06-19 Peter Bergner + + * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value. + * ppc-opc.c (FXM4): Add non-zero optional value. + (TBR): Likewise. + (SXL): Likewise. + (insert_fxm): Handle new default operand value. + (extract_fxm): Likewise. + (insert_tbr): Likewise. + (extract_tbr): Likewise. + +2015-06-16 Matthew Wahab + + * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1". + +2015-06-16 Szabolcs Nagy + + * arm-dis.c (print_insn_coprocessor): Avoid negative shift. + +2015-06-12 Peter Bergner + + * ppc-opc.c: Add comment accidentally removed by old commit. + (MTMSRD_L): Delete. + +2015-06-04 Peter Bergner + + * ppc-opc.c: (powerpc_opcodes) : New extended mnemonic. + +2015-06-04 Nick Clifton + + PR 18474 + * msp430-dis.c (msp430_nooperands): Fix check for emulated insns. + +2015-06-02 Matthew Wahab + + * arm-dis.c (arm_opcodes): Add "setpan". + (thumb_opcodes): Add "setpan". + +2015-06-02 Matthew Wahab + + * arm-dis.c (select_arm_features): Rework to avoid used of redefined + macros. + +2015-06-02 Matthew Wahab + + * aarch64-tbl.h (aarch64_feature_rdma): New. + (RDMA): New. + (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions. + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + +2015-06-02 Matthew Wahab + + * aarch64-tbl.h (aarch64_feature_lor): New. + (LOR): New. + (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr", + "stllrb", "stllrh". + * aarch64-asm-2.c: Regenerate. + * aarch64-dis-2.c: Regenerate. + * aarch64-opc-2.c: Regenerate. + +2015-06-01 Matthew Wahab + + * aarch64-opc.c (F_ARCHEXT): New. + (aarch64_sys_regs): Add "pan". + (aarch64_sys_reg_supported_p): New. + (aarch64_pstatefields): Add "pan". + (aarch64_pstatefield_supported_p): New. + +2015-06-01 Jan Beulich + + * i386-tbl.h: Regenerate. + +2015-06-01 Jan Beulich + + * i386-dis.c (print_insn): Swap rounding mode specifier and + general purpose register in Intel mode. + +2015-06-01 Jan Beulich + + * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. + * i386-tbl.h: Regenerate. + +2015-05-18 H.J. Lu + + * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp. + * i386-init.h: Regenerated. + +2015-05-15 H.J. Lu + + PR binutis/18386 + * i386-dis.c: Add comments for '@'. + (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9. + (enum x86_64_isa): New. + (isa64): Likewise. + (print_i386_disassembler_options): Add amd64 and intel64. + (print_insn): Handle amd64 and intel64. + (putop): Handle '@'. + (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit. + * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64. + * i386-opc.h (AMD64): New. + (CpuIntel64): Likewise. + (i386_cpu_flags): Add cpuamd64 and cpuintel64. + * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64. + Mark direct call/jmp without Disp16|Disp32 as Intel64. + * i386-init.h: Regenerated. + * i386-tbl.h: Likewise. + +2015-05-14 Peter Bergner + + * ppc-opc.c (IH) New define. + (powerpc_opcodes) : Do not enable for POWER7. + : Add RS operand for POWER7. + : Add IH operand for POWER6. + +2015-05-11 H.J. Lu + + * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit + direct branch. + (jmp): Likewise. + * i386-tbl.h: Regenerated. + 2015-05-11 H.J. Lu * configure.ac: Support bfd_iamcu_arch. @@ -11,6 +502,19 @@ * i386-init.h: Likewise. * i386-tbl.h: Likewise. +2015-05-08 H.J. Lu + + PR binutis/18386 + * i386-dis.c (X86_64_E8): New. + (X86_64_E9): Likewise. + Update comments on 'T', 'U', 'V'. Add comments for '^'. + (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9. + (x86_64_table): Add X86_64_E8 and X86_64_E9. + (mod_table): Replace {T|} with ^ on Jcall/Jmp. + (putop): Handle '^'. + (OP_J): Ignore the operand size prefix in 64-bit. Don't check + REX_W. + 2015-04-30 DJ Delorie * disassemble.c (disassembler): Choose suitable disassembler based