X-Git-Url: http://drtracing.org/?a=blobdiff_plain;ds=sidebyside;f=opcodes%2Faarch64-opc.c;h=61547b403df47a3d23361019799b00e285290969;hb=36bd8ea7f06126d3e73d9644325c4bbfbd5c89f4;hp=1f85294e3bf992d95e48375d8021be401785f17d;hpb=0a57e14ffa4c2900f64780375282dc5dc493e250;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 1f85294e3b..61547b403d 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -296,6 +296,7 @@ const aarch64_field fields[] = { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */ { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */ { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */ + { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */ { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */ { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */ { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */ @@ -711,6 +712,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] = {8, 1, 0x3, "d", OQK_OPD_VARIANT}, {16, 1, 0x4, "q", OQK_OPD_VARIANT}, {4, 1, 0x0, "4b", OQK_OPD_VARIANT}, + {4, 1, 0x0, "2h", OQK_OPD_VARIANT}, {1, 4, 0x0, "4b", OQK_OPD_VARIANT}, {1, 8, 0x0, "8b", OQK_OPD_VARIANT}, @@ -1519,6 +1521,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SVE_Zm3_INDEX: case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: size = get_operand_fields_width (get_operand_from_code (type)); shift = get_operand_specific_data (&aarch64_operands[type]); @@ -1896,6 +1899,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, break; case AARCH64_OPND_SVE_ADDR_RI_S4x16: + case AARCH64_OPND_SVE_ADDR_RI_S4x32: min_value = -8; max_value = 7; goto sve_imm_offset; @@ -2529,6 +2533,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SVE_SHLIMM_PRED: case AARCH64_OPND_SVE_SHLIMM_UNPRED: + case AARCH64_OPND_SVE_SHLIMM_UNPRED_22: size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier); if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1)) { @@ -2540,10 +2545,12 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, case AARCH64_OPND_SVE_SHRIMM_PRED: case AARCH64_OPND_SVE_SHRIMM_UNPRED: - size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier); + case AARCH64_OPND_SVE_SHRIMM_UNPRED_22: + num = (type == AARCH64_OPND_SVE_SHRIMM_UNPRED_22) ? 2 : 1; + size = aarch64_get_qualifier_esize (opnds[idx - num].qualifier); if (!value_in_range_p (opnd->imm.value, 1, 8 * size)) { - set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size); + set_imm_out_of_range_error (mismatch_detail, idx, 1, 8*size); return 0; } break; @@ -3055,7 +3062,12 @@ print_immediate_offset_address (char *buf, size_t size, if (opnd->addr.writeback) { if (opnd->addr.preind) - snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm); + { + if (opnd->type == AARCH64_OPND_ADDR_SIMM10 && !opnd->addr.offset.imm) + snprintf (buf, size, "[%s]!", base); + else + snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm); + } else snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm); } @@ -3319,6 +3331,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SVE_Zm3_INDEX: case AARCH64_OPND_SVE_Zm3_22_INDEX: case AARCH64_OPND_SVE_Zm3_11_INDEX: + case AARCH64_OPND_SVE_Zm4_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno, @@ -3350,8 +3363,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_SIMM5: case AARCH64_OPND_SVE_SHLIMM_PRED: case AARCH64_OPND_SVE_SHLIMM_UNPRED: + case AARCH64_OPND_SVE_SHLIMM_UNPRED_22: case AARCH64_OPND_SVE_SHRIMM_PRED: case AARCH64_OPND_SVE_SHRIMM_UNPRED: + case AARCH64_OPND_SVE_SHRIMM_UNPRED_22: case AARCH64_OPND_SVE_SIMM5: case AARCH64_OPND_SVE_SIMM5B: case AARCH64_OPND_SVE_SIMM6: @@ -3627,6 +3642,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_ADDR_SIMM13: case AARCH64_OPND_ADDR_OFFSET: case AARCH64_OPND_SVE_ADDR_RI_S4x16: + case AARCH64_OPND_SVE_ADDR_RI_S4x32: case AARCH64_OPND_SVE_ADDR_RI_S4xVL: case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL: case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL: @@ -3955,13 +3971,14 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */ { "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */ { "tco", CPENC(3,3,C4,C2,7), F_ARCHEXT }, - { "tfsre0_el1", CPENC(3,0,C6,C6,1), F_ARCHEXT }, - { "tfsr_el1", CPENC(3,0,C6,C5,0), F_ARCHEXT }, - { "tfsr_el2", CPENC(3,4,C6,C5,0), F_ARCHEXT }, - { "tfsr_el3", CPENC(3,6,C6,C6,0), F_ARCHEXT }, - { "tfsr_el12", CPENC(3,5,C6,C6,0), F_ARCHEXT }, + { "tfsre0_el1", CPENC(3,0,C5,C6,1), F_ARCHEXT }, + { "tfsr_el1", CPENC(3,0,C5,C6,0), F_ARCHEXT }, + { "tfsr_el2", CPENC(3,4,C5,C6,0), F_ARCHEXT }, + { "tfsr_el3", CPENC(3,6,C5,C6,0), F_ARCHEXT }, + { "tfsr_el12", CPENC(3,5,C5,C6,0), F_ARCHEXT }, { "rgsr_el1", CPENC(3,0,C1,C0,5), F_ARCHEXT }, { "gcr_el1", CPENC(3,0,C1,C0,6), F_ARCHEXT }, + { "gmid_el1", CPENC(3,1,C0,C0,4), F_ARCHEXT | F_REG_READ }, /* RO */ { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 }, { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */ { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 }, @@ -4427,13 +4444,14 @@ aarch64_sys_reg_supported_p (const aarch64_feature_set features, /* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG. */ if ((reg->value == CPENC (3, 3, C4, C2, 7) - || reg->value == CPENC (3, 0, C6, C6, 1) - || reg->value == CPENC (3, 0, C6, C5, 0) - || reg->value == CPENC (3, 4, C6, C5, 0) - || reg->value == CPENC (3, 6, C6, C6, 0) - || reg->value == CPENC (3, 5, C6, C6, 0) + || reg->value == CPENC (3, 0, C5, C6, 1) + || reg->value == CPENC (3, 0, C5, C6, 0) + || reg->value == CPENC (3, 4, C5, C6, 0) + || reg->value == CPENC (3, 6, C5, C6, 0) + || reg->value == CPENC (3, 5, C5, C6, 0) || reg->value == CPENC (3, 0, C1, C0, 5) - || reg->value == CPENC (3, 0, C1, C0, 6)) + || reg->value == CPENC (3, 0, C1, C0, 6) + || reg->value == CPENC (3, 1, C0, C0, 4)) && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))) return FALSE; @@ -4957,11 +4975,6 @@ verify_constraints (const struct aarch64_inst *inst, case AARCH64_OPND_Vm: case AARCH64_OPND_Sn: case AARCH64_OPND_Sm: - case AARCH64_OPND_Rn: - case AARCH64_OPND_Rm: - case AARCH64_OPND_Rn_SP: - case AARCH64_OPND_Rt_SP: - case AARCH64_OPND_Rm_SP: if (inst_op.reg.regno == blk_dest.reg.regno) { num_op_used++;