X-Git-Url: http://drtracing.org/?a=blobdiff_plain;ds=sidebyside;f=opcodes%2Faarch64-opc.c;h=adc34e29b9c70b6d18cc4b014f8bd6dbaae205c6;hb=a5721ba270ddf860e0e5a45bba456214e8eac2be;hp=47c50797fb5068c221d093827cadfe8bb21bd9ab;hpb=047cd301d40288d13e44f3322541ac28ebe06078;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 47c50797fb..adc34e29b9 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -264,6 +264,9 @@ const aarch64_field fields[] = { 31, 1 }, /* b5: in the test bit and branch instructions. */ { 19, 5 }, /* b40: in the test bit and branch instructions. */ { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */ + { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */ + { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */ + { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */ { 17, 1 }, /* SVE_N: SVE equivalent of N. */ { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */ { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */ @@ -299,7 +302,11 @@ const aarch64_field fields[] = { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */ { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */ { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */ + { 22, 1 }, /* SVE_sz: 1-bit element size select. */ + { 16, 4 }, /* SVE_tsz: triangular size select. */ { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */ + { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */ + { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */ { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */ { 22, 1 } /* SVE_xs_22: UXTW/SXTW select (bit 22). */ }; @@ -327,18 +334,18 @@ aarch64_get_operand_desc (enum aarch64_opnd type) /* Table of all conditional affixes. */ const aarch64_cond aarch64_conds[16] = { - {{"eq"}, 0x0}, - {{"ne"}, 0x1}, - {{"cs", "hs"}, 0x2}, - {{"cc", "lo", "ul"}, 0x3}, - {{"mi"}, 0x4}, - {{"pl"}, 0x5}, + {{"eq", "none"}, 0x0}, + {{"ne", "any"}, 0x1}, + {{"cs", "hs", "nlast"}, 0x2}, + {{"cc", "lo", "ul", "last"}, 0x3}, + {{"mi", "first"}, 0x4}, + {{"pl", "nfrst"}, 0x5}, {{"vs"}, 0x6}, {{"vc"}, 0x7}, - {{"hi"}, 0x8}, - {{"ls"}, 0x9}, - {{"ge"}, 0xa}, - {{"lt"}, 0xb}, + {{"hi", "pmore"}, 0x8}, + {{"ls", "plast"}, 0x9}, + {{"ge", "tcont"}, 0xa}, + {{"lt", "tstop"}, 0xb}, {{"gt"}, 0xc}, {{"le"}, 0xd}, {{"al"}, 0xe}, @@ -1907,7 +1914,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12) { set_other_error (mismatch_detail, idx, - _("shift amount expected to be 0 or 12")); + _("shift amount must be 0 or 12")); return 0; } if (!value_fit_unsigned_field_p (opnd->imm.value, 12)) @@ -1930,7 +1937,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, if (!value_aligned_p (opnd->shifter.amount, 16)) { set_other_error (mismatch_detail, idx, - _("shift amount should be a multiple of 16")); + _("shift amount must be a multiple of 16")); return 0; } if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16)) @@ -2167,7 +2174,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx, if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16) { set_other_error (mismatch_detail, idx, - _("shift amount expected to be 0 or 16")); + _("shift amount must be 0 or 16")); return 0; } break; @@ -2857,20 +2864,20 @@ print_immediate_offset_address (char *buf, size_t size, if (opnd->addr.writeback) { if (opnd->addr.preind) - snprintf (buf, size, "[%s,#%d]!", base, opnd->addr.offset.imm); + snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm); else - snprintf (buf, size, "[%s],#%d", base, opnd->addr.offset.imm); + snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm); } else { if (opnd->shifter.operator_present) { assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL); - snprintf (buf, size, "[%s,#%d,mul vl]", + snprintf (buf, size, "[%s, #%d, mul vl]", base, opnd->addr.offset.imm); } else if (opnd->addr.offset.imm) - snprintf (buf, size, "[%s,#%d]", base, opnd->addr.offset.imm); + snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm); else snprintf (buf, size, "[%s]", base); } @@ -2905,15 +2912,15 @@ print_register_offset_address (char *buf, size_t size, if (print_extend_p) { if (print_amount_p) - snprintf (tb, sizeof (tb), ",%s #%" PRIi64, shift_name, + snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name, opnd->shifter.amount); else - snprintf (tb, sizeof (tb), ",%s", shift_name); + snprintf (tb, sizeof (tb), ", %s", shift_name); } else tb[0] = '\0'; - snprintf (buf, size, "[%s,%s%s]", base, offset, tb); + snprintf (buf, size, "[%s, %s%s]", base, offset, tb); } /* Generate the string representation of the operand OPNDS[IDX] for OPCODE @@ -2933,7 +2940,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, const aarch64_opnd_info *opnds, int idx, int *pcrel_p, bfd_vma *address) { - int i; + unsigned int i, num_conds; const char *name = NULL; const aarch64_opnd_info *opnd = opnds + idx; enum aarch64_modifier_kind kind; @@ -3299,6 +3306,17 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_COND: case AARCH64_OPND_COND1: snprintf (buf, size, "%s", opnd->cond->names[0]); + num_conds = ARRAY_SIZE (opnd->cond->names); + for (i = 1; i < num_conds && opnd->cond->names[i]; ++i) + { + size_t len = strlen (buf); + if (i == 1) + snprintf (buf + len, size - len, " // %s = %s", + opnd->cond->names[0], opnd->cond->names[i]); + else + snprintf (buf + len, size - len, ", %s", + opnd->cond->names[i]); + } break; case AARCH64_OPND_ADDR_ADRP: @@ -3415,7 +3433,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_ADDR_UIMM12: name = get_64bit_int_reg_name (opnd->addr.base_regno, 1); if (opnd->addr.offset.imm) - snprintf (buf, size, "[%s,#%d]", name, opnd->addr.offset.imm); + snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm); else snprintf (buf, size, "[%s]", name); break;