X-Git-Url: http://drtracing.org/?a=blobdiff_plain;ds=sidebyside;f=opcodes%2Fi386-opc.h;h=ba04ce47ad17b58675abeee918542bf658aca513;hb=1f334aeb2268db153f01143e9b0ac01448ecaa56;hp=b5eb33308ba8d5ade899df67958e3cdeea51b022;hpb=a00464085799717f03cfee95a3de4d4f0fd58c64;p=deliverable%2Fbinutils-gdb.git diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h index b5eb33308b..ba04ce47ad 100644 --- a/opcodes/i386-opc.h +++ b/opcodes/i386-opc.h @@ -1,6 +1,5 @@ /* Declarations for Intel 80386 opcode table - Copyright 2007, 2008, 2009, 2010, 2012 - Free Software Foundation, Inc. + Copyright (C) 2007-2016 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -94,10 +93,27 @@ enum CpuAVX, /* AVX2 support required */ CpuAVX2, + /* Intel AVX-512 Foundation Instructions support required */ + CpuAVX512F, + /* Intel AVX-512 Conflict Detection Instructions support required */ + CpuAVX512CD, + /* Intel AVX-512 Exponential and Reciprocal Instructions support + required */ + CpuAVX512ER, + /* Intel AVX-512 Prefetch Instructions support required */ + CpuAVX512PF, + /* Intel AVX-512 VL Instructions support required. */ + CpuAVX512VL, + /* Intel AVX-512 DQ Instructions support required. */ + CpuAVX512DQ, + /* Intel AVX-512 BW Instructions support required. */ + CpuAVX512BW, /* Intel L1OM support required */ CpuL1OM, /* Intel K1OM support required */ CpuK1OM, + /* Intel IAMCU support required */ + CpuIAMCU, /* Xsave/xrstor New Instructions support required */ CpuXsave, /* Xsaveopt New Instructions support required */ @@ -158,6 +174,48 @@ enum CpuSMAP, /* SHA instructions required. */ CpuSHA, + /* VREX support required */ + CpuVREX, + /* CLFLUSHOPT instruction required */ + CpuClflushOpt, + /* XSAVES/XRSTORS instruction required */ + CpuXSAVES, + /* XSAVEC instruction required */ + CpuXSAVEC, + /* PREFETCHWT1 instruction required */ + CpuPREFETCHWT1, + /* SE1 instruction required */ + CpuSE1, + /* CLWB instruction required */ + CpuCLWB, + /* Intel AVX-512 IFMA Instructions support required. */ + CpuAVX512IFMA, + /* Intel AVX-512 VBMI Instructions support required. */ + CpuAVX512VBMI, + /* Intel AVX-512 4FMAPS Instructions support required. */ + CpuAVX512_4FMAPS, + /* Intel AVX-512 4VNNIW Instructions support required. */ + CpuAVX512_4VNNIW, + /* mwaitx instruction required */ + CpuMWAITX, + /* Clzero instruction required */ + CpuCLZERO, + /* OSPKE instruction required */ + CpuOSPKE, + /* RDPID instruction required */ + CpuRDPID, + /* PTWRITE instruction required */ + CpuPTWRITE, + /* MMX register support required */ + CpuRegMMX, + /* XMM register support required */ + CpuRegXMM, + /* YMM register support required */ + CpuRegYMM, + /* ZMM register support required */ + CpuRegZMM, + /* Mask register support required */ + CpuRegMask, /* 64bit support required */ Cpu64, /* Not supported in the 64bit mode */ @@ -212,8 +270,16 @@ typedef union i386_cpu_flags unsigned int cpusse4_2:1; unsigned int cpuavx:1; unsigned int cpuavx2:1; + unsigned int cpuavx512f:1; + unsigned int cpuavx512cd:1; + unsigned int cpuavx512er:1; + unsigned int cpuavx512pf:1; + unsigned int cpuavx512vl:1; + unsigned int cpuavx512dq:1; + unsigned int cpuavx512bw:1; unsigned int cpul1om:1; unsigned int cpuk1om:1; + unsigned int cpuiamcu:1; unsigned int cpuxsave:1; unsigned int cpuxsaveopt:1; unsigned int cpuaes:1; @@ -244,6 +310,27 @@ typedef union i386_cpu_flags unsigned int cpuprfchw:1; unsigned int cpusmap:1; unsigned int cpusha:1; + unsigned int cpuvrex:1; + unsigned int cpuclflushopt:1; + unsigned int cpuxsaves:1; + unsigned int cpuxsavec:1; + unsigned int cpuprefetchwt1:1; + unsigned int cpuse1:1; + unsigned int cpuclwb:1; + unsigned int cpuavx512ifma:1; + unsigned int cpuavx512vbmi:1; + unsigned int cpuavx512_4fmaps:1; + unsigned int cpuavx512_4vnniw:1; + unsigned int cpumwaitx:1; + unsigned int cpuclzero:1; + unsigned int cpuospke:1; + unsigned int cpurdpid:1; + unsigned int cpuptwrite:1; + unsigned int cpuregmmx:1; + unsigned int cpuregxmm:1; + unsigned int cpuregymm:1; + unsigned int cpuregzmm:1; + unsigned int cpuregmask:1; unsigned int cpu64:1; unsigned int cpuno64:1; #ifdef CpuUnused @@ -415,14 +502,74 @@ enum /* Instruction with vector SIB byte: 1: 128bit vector register. 2: 256bit vector register. + 3: 512bit vector register. */ #define VecSIB128 1 #define VecSIB256 2 +#define VecSIB512 3 VecSIB, /* SSE to AVX support required */ SSE2AVX, /* No AVX equivalent */ NoAVX, + + /* insn has EVEX prefix: + 1: 512bit EVEX prefix. + 2: 128bit EVEX prefix. + 3: 256bit EVEX prefix. + 4: Length-ignored (LIG) EVEX prefix. + */ +#define EVEX512 1 +#define EVEX128 2 +#define EVEX256 3 +#define EVEXLIG 4 + EVex, + + /* AVX512 masking support: + 1: Zeroing-masking. + 2: Merging-masking. + 3: Both zeroing and merging masking. + */ +#define ZEROING_MASKING 1 +#define MERGING_MASKING 2 +#define BOTH_MASKING 3 + Masking, + + /* Input element size of vector insn: + 0: 32bit. + 1: 64bit. + */ + VecESize, + + /* Broadcast factor. + 0: No broadcast. + 1: 1to16 broadcast. + 2: 1to8 broadcast. + */ +#define NO_BROADCAST 0 +#define BROADCAST_1TO16 1 +#define BROADCAST_1TO8 2 +#define BROADCAST_1TO4 3 +#define BROADCAST_1TO2 4 + Broadcast, + + /* Static rounding control is supported. */ + StaticRounding, + + /* Supress All Exceptions is supported. */ + SAE, + + /* Copressed Disp8*N attribute. */ + Disp8MemShift, + + /* Default mask isn't allowed. */ + NoDefMask, + + /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4. + It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). + */ + ImplicitQuadGroup, + /* Compatible with old (<= 2.8.1) versions of gcc */ OldGcc, /* AT&T mnemonic. */ @@ -431,6 +578,10 @@ enum ATTSyntax, /* Intel syntax. */ IntelSyntax, + /* AMD64. */ + AMD64, + /* Intel64. */ + Intel64, /* The last bitfield in i386_opcode_modifier. */ Opcode_Modifier_Max }; @@ -487,10 +638,21 @@ typedef struct i386_opcode_modifier unsigned int vecsib:2; unsigned int sse2avx:1; unsigned int noavx:1; + unsigned int evex:3; + unsigned int masking:2; + unsigned int vecesize:1; + unsigned int broadcast:3; + unsigned int staticrounding:1; + unsigned int sae:1; + unsigned int disp8memshift:3; + unsigned int nodefmask:1; + unsigned int implicitquadgroup:1; unsigned int oldgcc:1; unsigned int attmnemonic:1; unsigned int attsyntax:1; unsigned int intelsyntax:1; + unsigned int amd64:1; + unsigned int intel64:1; } i386_opcode_modifier; /* Position of operand_type bits. */ @@ -513,6 +675,10 @@ enum RegXMM, /* AVX registers */ RegYMM, + /* AVX512 registers */ + RegZMM, + /* Vector Mask registers */ + RegMask, /* Control register */ Control, /* Debug register */ @@ -592,6 +758,8 @@ enum Xmmword, /* YMMWORD memory. */ Ymmword, + /* ZMMWORD memory. */ + Zmmword, /* Unspecified memory size. */ Unspecified, /* Any memory size. */ @@ -603,6 +771,9 @@ enum /* Bound register. */ RegBND, + /* Vector 8bit displacement */ + Vec_Disp8, + /* The last bitfield in i386_operand_type. */ OTMax }; @@ -628,6 +799,8 @@ typedef union i386_operand_type unsigned int regmmx:1; unsigned int regxmm:1; unsigned int regymm:1; + unsigned int regzmm:1; + unsigned int regmask:1; unsigned int control:1; unsigned int debug:1; unsigned int test:1; @@ -662,10 +835,12 @@ typedef union i386_operand_type unsigned int tbyte:1; unsigned int xmmword:1; unsigned int ymmword:1; + unsigned int zmmword:1; unsigned int unspecified:1; unsigned int anysize:1; unsigned int vec_imm4:1; unsigned int regbnd:1; + unsigned int vec_disp8:1; #ifdef OTUnused unsigned int unused:(OTNumOfBits - OTUnused); #endif @@ -727,6 +902,7 @@ typedef struct unsigned char reg_flags; #define RegRex 0x1 /* Extended register. */ #define RegRex64 0x2 /* Extended 8 bit register. */ +#define RegVRex 0x4 /* Extended vector register. */ unsigned char reg_num; #define RegRip ((unsigned char ) ~0) #define RegEip (RegRip - 1)