X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Fcputype.h;h=54a1f1d76b14516901380a13cdfc0801bc373630;hb=bc581770cfdd8c17ea17d324dc05e2f9c599e7ca;hp=b3e656c6fb78e20fb58fb2d361e4a2b968bfe8b7;hpb=cf5046323ea254be72535648a9d090b18b8510f3;p=deliverable%2Flinux.git

diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index b3e656c6fb78..54a1f1d76b14 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -63,6 +63,11 @@ static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
 	return read_cpuid(CPUID_CACHETYPE);
 }
 
+static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
+{
+	return read_cpuid(CPUID_TCM);
+}
+
 /*
  * Intel's XScale3 core supports some v6 features (supersections, L2)
  * but advertises itself as v5 as it does not support the v6 ISA.  For