X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=bfd%2Freloc.c;h=f1d09a5ab07381823808b510f0e3da093d1fd68c;hb=48d502e18e90fd25600d9d7f8191b09218e22603;hp=9bffaa365885fe675528ac50a22b435a2b9413c2;hpb=28d39d1a3a0fa205e5223b183c3df93264865dc5;p=deliverable%2Fbinutils-gdb.git diff --git a/bfd/reloc.c b/bfd/reloc.c index 9bffaa3658..f1d09a5ab0 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c @@ -1,6 +1,6 @@ /* BFD support for handling relocation entries. Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2004 + 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. Written by Cygnus Support. @@ -18,7 +18,7 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* SECTION @@ -255,11 +255,12 @@ CODE_FRAGMENT . {* Do not complain on overflow. *} . complain_overflow_dont, . -. {* Complain if the bitfield overflows, whether it is considered -. as signed or unsigned. *} +. {* Complain if the value overflows when considered as a signed +. number one bit larger than the field. ie. A bitfield of N bits +. is allowed to represent -2**n to 2**n-1. *} . complain_overflow_bitfield, . -. {* Complain if the value overflows when considered as signed +. {* Complain if the value overflows when considered as a signed . number. *} . complain_overflow_signed, . @@ -496,14 +497,14 @@ bfd_check_overflow (enum complain_overflow how, bfd_vma fieldmask, addrmask, signmask, ss, a; bfd_reloc_status_type flag = bfd_reloc_ok; - a = relocation; - /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not, we'll be permissive: extra bits in the field mask will automatically extend the address mask for purposes of the overflow check. */ fieldmask = N_ONES (bitsize); + signmask = ~fieldmask; addrmask = N_ONES (addrsize) | fieldmask; + a = (relocation & addrmask) >> rightshift;; switch (how) { @@ -513,19 +514,8 @@ bfd_check_overflow (enum complain_overflow how, case complain_overflow_signed: /* If any sign bits are set, all sign bits must be set. That is, A must be a valid negative address after shifting. */ - a = (a & addrmask) >> rightshift; signmask = ~ (fieldmask >> 1); - ss = a & signmask; - if (ss != 0 && ss != ((addrmask >> rightshift) & signmask)) - flag = bfd_reloc_overflow; - break; - - case complain_overflow_unsigned: - /* We have an overflow if the address does not fit in the field. */ - a = (a & addrmask) >> rightshift; - if ((a & ~ fieldmask) != 0) - flag = bfd_reloc_overflow; - break; + /* Fall thru */ case complain_overflow_bitfield: /* Bitfields are sometimes signed, sometimes unsigned. We @@ -533,9 +523,14 @@ bfd_check_overflow (enum complain_overflow how, of n bits is allowed to store -2**n to 2**n-1. Thus overflow if the value has some, but not all, bits set outside the field. */ - a >>= rightshift; - ss = a & ~ fieldmask; - if (ss != 0 && ss != (((bfd_vma) -1 >> rightshift) & ~ fieldmask)) + ss = a & signmask; + if (ss != 0 && ss != ((addrmask >> rightshift) & signmask)) + flag = bfd_reloc_overflow; + break; + + case complain_overflow_unsigned: + /* We have an overflow if the address does not fit in the field. */ + if ((a & signmask) != 0) flag = bfd_reloc_overflow; break; @@ -623,8 +618,7 @@ bfd_perform_relocation (bfd *abfd, } /* Is the address of the relocation really within the section? */ - if (reloc_entry->address > (input_section->_cooked_size - / bfd_octets_per_byte (abfd))) + if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) return bfd_reloc_outofrange; /* Work out which section the relocation is targeted at and the @@ -716,7 +710,6 @@ bfd_perform_relocation (bfd *abfd, && strcmp (abfd->xvec->name, "coff-Intel-little") != 0 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0) { -#if 1 /* For m68k-coff, the addend was being subtracted twice during relocation with -r. Removing the line below this comment fixes that problem; see PR 2953. @@ -787,7 +780,6 @@ space consuming. For each target: right */ relocation -= reloc_entry->addend; -#endif reloc_entry->addend = 0; } else @@ -1013,8 +1005,7 @@ bfd_install_relocation (bfd *abfd, } /* Is the address of the relocation really within the section? */ - if (reloc_entry->address > (input_section->_cooked_size - / bfd_octets_per_byte (abfd))) + if (reloc_entry->address > bfd_get_section_limit (abfd, input_section)) return bfd_reloc_outofrange; /* Work out which section the relocation is targeted at and the @@ -1102,10 +1093,10 @@ bfd_install_relocation (bfd *abfd, && strcmp (abfd->xvec->name, "coff-Intel-little") != 0 && strcmp (abfd->xvec->name, "coff-Intel-big") != 0) { -#if 1 -/* For m68k-coff, the addend was being subtracted twice during - relocation with -r. Removing the line below this comment - fixes that problem; see PR 2953. + + /* For m68k-coff, the addend was being subtracted twice during + relocation with -r. Removing the line below this comment + fixes that problem; see PR 2953. However, Ian wrote the following, regarding removing the line below, which explains why it is still enabled: --djm @@ -1172,8 +1163,9 @@ space consuming. For each target: 7) if they are different you have to figure out which version is right. */ relocation -= reloc_entry->addend; -#endif - reloc_entry->addend = 0; + /* FIXME: There should be no target specific code here... */ + if (strcmp (abfd->xvec->name, "coff-z8k") != 0) + reloc_entry->addend = 0; } else { @@ -1350,7 +1342,7 @@ _bfd_final_link_relocate (reloc_howto_type *howto, bfd_vma relocation; /* Sanity check the address. */ - if (address > input_section->_raw_size) + if (address > bfd_get_section_limit (input_bfd, input_section)) return bfd_reloc_outofrange; /* This function assumes that we are dealing with a basic relocation @@ -1440,19 +1432,26 @@ _bfd_relocate_contents (reloc_howto_type *howto, the size of an address. For bitfields, all the bits matter. See also bfd_check_overflow. */ fieldmask = N_ONES (howto->bitsize); + signmask = ~fieldmask; addrmask = N_ONES (bfd_arch_bits_per_address (input_bfd)) | fieldmask; - a = relocation; - b = x & howto->src_mask; + a = (relocation & addrmask) >> rightshift; + b = (x & howto->src_mask & addrmask) >> bitpos; switch (howto->complain_on_overflow) { case complain_overflow_signed: - a = (a & addrmask) >> rightshift; - /* If any sign bits are set, all sign bits must be set. That is, A must be a valid negative address after shifting. */ - signmask = ~ (fieldmask >> 1); + signmask = ~(fieldmask >> 1); + /* Fall thru */ + + case complain_overflow_bitfield: + /* Much like the signed check, but for a field one bit + wider. We allow a bitfield to represent numbers in the + range -2**n to 2**n-1, where n is the number of bits in the + field. Note that when bfd_vma is 32 bits, a 32-bit reloc + can't overflow, which is exactly what we want. */ ss = a & signmask; if (ss != 0 && ss != ((addrmask >> rightshift) & signmask)) flag = bfd_reloc_overflow; @@ -1463,12 +1462,11 @@ _bfd_relocate_contents (reloc_howto_type *howto, SRC_MASK has more bits than BITSIZE, we can get into trouble; we would need to verify that B is in range, as we do for A above. */ - signmask = ((~ howto->src_mask) >> 1) & howto->src_mask; + ss = ((~howto->src_mask) >> 1) & howto->src_mask; + ss >>= bitpos; /* Set all the bits above the sign bit. */ - b = (b ^ signmask) - signmask; - - b = (b & addrmask) >> bitpos; + b = (b ^ ss) - ss; /* Now we can do the addition. */ sum = a + b; @@ -1480,11 +1478,14 @@ _bfd_relocate_contents (reloc_howto_type *howto, positive inputs. The test below looks only at the sign bits, and it really just SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM) - */ - signmask = (fieldmask >> 1) + 1; - if (((~ (a ^ b)) & (a ^ sum)) & signmask) - flag = bfd_reloc_overflow; + We mask with addrmask here to explicitly allow an address + wrap-around. The Linux kernel relies on it, and it is + the only way to write assembler code which can run when + loaded at a location 0x80000000 away from the location at + which it is linked. */ + if (((~(a ^ b)) & (a ^ sum)) & signmask & addrmask) + flag = bfd_reloc_overflow; break; case complain_overflow_unsigned: @@ -1499,44 +1500,9 @@ _bfd_relocate_contents (reloc_howto_type *howto, separate test, we can check for this by or-ing in the operands when testing for the sum overflowing its final field. */ - a = (a & addrmask) >> rightshift; - b = (b & addrmask) >> bitpos; sum = (a + b) & addrmask; - if ((a | b | sum) & ~ fieldmask) + if ((a | b | sum) & signmask) flag = bfd_reloc_overflow; - - break; - - case complain_overflow_bitfield: - /* Much like the signed check, but for a field one bit - wider, and no trimming inputs with addrmask. We allow a - bitfield to represent numbers in the range -2**n to - 2**n-1, where n is the number of bits in the field. - Note that when bfd_vma is 32 bits, a 32-bit reloc can't - overflow, which is exactly what we want. */ - a >>= rightshift; - - signmask = ~ fieldmask; - ss = a & signmask; - if (ss != 0 && ss != (((bfd_vma) -1 >> rightshift) & signmask)) - flag = bfd_reloc_overflow; - - signmask = ((~ howto->src_mask) >> 1) & howto->src_mask; - b = (b ^ signmask) - signmask; - - b >>= bitpos; - - sum = a + b; - - /* We mask with addrmask here to explicitly allow an address - wrap-around. The Linux kernel relies on it, and it is - the only way to write assembler code which can run when - loaded at a location 0x80000000 away from the location at - which it is linked. */ - signmask = fieldmask + 1; - if (((~ (a ^ b)) & (a ^ sum)) & signmask & addrmask) - flag = bfd_reloc_overflow; - break; default: @@ -1584,7 +1550,7 @@ DOCDD INODE howto manager, , typedef arelent, Relocations -SECTION +SUBSECTION The howto manager When an application wants to create a relocation, but doesn't @@ -1646,6 +1612,11 @@ the section containing the relocation. It depends on the specific target. The 24-bit relocation is used in some Intel 960 configurations. +ENUM + BFD_RELOC_32_SECREL +ENUMDOC + Section relative relocations. Some targets need this for DWARF2. + ENUM BFD_RELOC_32_GOT_PCREL ENUMX @@ -2061,14 +2032,35 @@ ENUM BFD_RELOC_LO16 ENUMDOC Low 16 bits. + ENUM - BFD_RELOC_PCREL_HI16_S + BFD_RELOC_HI16_PCREL ENUMDOC - Like BFD_RELOC_HI16_S, but PC relative. + High 16 bits of 32-bit pc-relative value ENUM - BFD_RELOC_PCREL_LO16 + BFD_RELOC_HI16_S_PCREL ENUMDOC - Like BFD_RELOC_LO16, but PC relative. + High 16 bits of 32-bit pc-relative value, adjusted +ENUM + BFD_RELOC_LO16_PCREL +ENUMDOC + Low 16 bits of pc-relative value + +ENUM + BFD_RELOC_MIPS16_HI16 +ENUMDOC + MIPS16 high 16 bits of 32-bit value. +ENUM + BFD_RELOC_MIPS16_HI16_S +ENUMDOC + MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign + extended and added to form the final result. If the low 16 + bits form a negative number, we need to add one to the high value + to compensate for the borrow when the low bits are added. +ENUM + BFD_RELOC_MIPS16_LO16 +ENUMDOC + MIPS16 low 16 bits. ENUM BFD_RELOC_MIPS_LITERAL @@ -2117,10 +2109,44 @@ ENUMX BFD_RELOC_MIPS_RELGOT ENUMX BFD_RELOC_MIPS_JALR +ENUMX + BFD_RELOC_MIPS_TLS_DTPMOD32 +ENUMX + BFD_RELOC_MIPS_TLS_DTPREL32 +ENUMX + BFD_RELOC_MIPS_TLS_DTPMOD64 +ENUMX + BFD_RELOC_MIPS_TLS_DTPREL64 +ENUMX + BFD_RELOC_MIPS_TLS_GD +ENUMX + BFD_RELOC_MIPS_TLS_LDM +ENUMX + BFD_RELOC_MIPS_TLS_DTPREL_HI16 +ENUMX + BFD_RELOC_MIPS_TLS_DTPREL_LO16 +ENUMX + BFD_RELOC_MIPS_TLS_GOTTPREL +ENUMX + BFD_RELOC_MIPS_TLS_TPREL32 +ENUMX + BFD_RELOC_MIPS_TLS_TPREL64 +ENUMX + BFD_RELOC_MIPS_TLS_TPREL_HI16 +ENUMX + BFD_RELOC_MIPS_TLS_TPREL_LO16 ENUMDOC MIPS ELF relocations. COMMENT +ENUM + BFD_RELOC_MIPS_COPY +ENUMX + BFD_RELOC_MIPS_JUMP_SLOT +ENUMDOC + MIPS ELF relocations (VxWorks extensions). +COMMENT + ENUM BFD_RELOC_FRV_LABEL16 ENUMX @@ -2167,6 +2193,38 @@ ENUMX BFD_RELOC_FRV_GOTOFFHI ENUMX BFD_RELOC_FRV_GOTOFFLO +ENUMX + BFD_RELOC_FRV_GETTLSOFF +ENUMX + BFD_RELOC_FRV_TLSDESC_VALUE +ENUMX + BFD_RELOC_FRV_GOTTLSDESC12 +ENUMX + BFD_RELOC_FRV_GOTTLSDESCHI +ENUMX + BFD_RELOC_FRV_GOTTLSDESCLO +ENUMX + BFD_RELOC_FRV_TLSMOFF12 +ENUMX + BFD_RELOC_FRV_TLSMOFFHI +ENUMX + BFD_RELOC_FRV_TLSMOFFLO +ENUMX + BFD_RELOC_FRV_GOTTLSOFF12 +ENUMX + BFD_RELOC_FRV_GOTTLSOFFHI +ENUMX + BFD_RELOC_FRV_GOTTLSOFFLO +ENUMX + BFD_RELOC_FRV_TLSOFF +ENUMX + BFD_RELOC_FRV_TLSDESC_RELAX +ENUMX + BFD_RELOC_FRV_GETTLSOFF_RELAX +ENUMX + BFD_RELOC_FRV_TLSOFF_RELAX +ENUMX + BFD_RELOC_FRV_TLSMOFF ENUMDOC Fujitsu Frv Relocations. COMMENT @@ -2248,6 +2306,12 @@ ENUMX BFD_RELOC_386_TLS_DTPOFF32 ENUMX BFD_RELOC_386_TLS_TPOFF32 +ENUMX + BFD_RELOC_386_TLS_GOTDESC +ENUMX + BFD_RELOC_386_TLS_DESC_CALL +ENUMX + BFD_RELOC_386_TLS_DESC ENUMDOC i386/elf relocations @@ -2283,6 +2347,26 @@ ENUMX BFD_RELOC_X86_64_GOTTPOFF ENUMX BFD_RELOC_X86_64_TPOFF32 +ENUMX + BFD_RELOC_X86_64_GOTOFF64 +ENUMX + BFD_RELOC_X86_64_GOTPC32 +ENUMX + BFD_RELOC_X86_64_GOT64 +ENUMX + BFD_RELOC_X86_64_GOTPCREL64 +ENUMX + BFD_RELOC_X86_64_GOTPC64 +ENUMX + BFD_RELOC_X86_64_GOTPLT64 +ENUMX + BFD_RELOC_X86_64_PLTOFF64 +ENUMX + BFD_RELOC_X86_64_GOTPC32_TLSDESC +ENUMX + BFD_RELOC_X86_64_TLSDESC_CALL +ENUMX + BFD_RELOC_X86_64_TLSDESC ENUMDOC x86-64/elf relocations @@ -2556,14 +2640,118 @@ ENUMDOC Thumb 22 bit pc-relative branch. The lowest bit must be zero and is not stored in the instruction. The 2nd lowest bit comes from a 1 bit field in the instruction. +ENUM + BFD_RELOC_ARM_PCREL_CALL +ENUMDOC + ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction. +ENUM + BFD_RELOC_ARM_PCREL_JUMP +ENUMDOC + ARM 26-bit pc-relative branch for B or conditional BL instruction. + +ENUM + BFD_RELOC_THUMB_PCREL_BRANCH7 +ENUMX + BFD_RELOC_THUMB_PCREL_BRANCH9 +ENUMX + BFD_RELOC_THUMB_PCREL_BRANCH12 +ENUMX + BFD_RELOC_THUMB_PCREL_BRANCH20 +ENUMX + BFD_RELOC_THUMB_PCREL_BRANCH23 +ENUMX + BFD_RELOC_THUMB_PCREL_BRANCH25 +ENUMDOC + Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches. + The lowest bit must be zero and is not stored in the instruction. + Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an + "nn" one smaller in all cases. Note further that BRANCH23 + corresponds to R_ARM_THM_CALL. + +ENUM + BFD_RELOC_ARM_OFFSET_IMM +ENUMDOC + 12-bit immediate offset, used in ARM-format ldr and str instructions. + +ENUM + BFD_RELOC_ARM_THUMB_OFFSET +ENUMDOC + 5-bit immediate offset, used in Thumb-format ldr and str instructions. + +ENUM + BFD_RELOC_ARM_TARGET1 +ENUMDOC + Pc-relative or absolute relocation depending on target. Used for + entries in .init_array sections. +ENUM + BFD_RELOC_ARM_ROSEGREL32 +ENUMDOC + Read-only segment base relative address. +ENUM + BFD_RELOC_ARM_SBREL32 +ENUMDOC + Data segment base relative address. +ENUM + BFD_RELOC_ARM_TARGET2 +ENUMDOC + This reloc is used for references to RTTI data from exception handling + tables. The actual definition depends on the target. It may be a + pc-relative or some form of GOT-indirect relocation. +ENUM + BFD_RELOC_ARM_PREL31 +ENUMDOC + 31-bit PC relative address. + +ENUM + BFD_RELOC_ARM_JUMP_SLOT +ENUMX + BFD_RELOC_ARM_GLOB_DAT +ENUMX + BFD_RELOC_ARM_GOT32 +ENUMX + BFD_RELOC_ARM_PLT32 +ENUMX + BFD_RELOC_ARM_RELATIVE +ENUMX + BFD_RELOC_ARM_GOTOFF +ENUMX + BFD_RELOC_ARM_GOTPC +ENUMDOC + Relocations for setting up GOTs and PLTs for shared libraries. + +ENUM + BFD_RELOC_ARM_TLS_GD32 +ENUMX + BFD_RELOC_ARM_TLS_LDO32 +ENUMX + BFD_RELOC_ARM_TLS_LDM32 +ENUMX + BFD_RELOC_ARM_TLS_DTPOFF32 +ENUMX + BFD_RELOC_ARM_TLS_DTPMOD32 +ENUMX + BFD_RELOC_ARM_TLS_TPOFF32 +ENUMX + BFD_RELOC_ARM_TLS_IE32 +ENUMX + BFD_RELOC_ARM_TLS_LE32 +ENUMDOC + ARM thread-local storage relocations. + ENUM BFD_RELOC_ARM_IMMEDIATE ENUMX BFD_RELOC_ARM_ADRL_IMMEDIATE ENUMX - BFD_RELOC_ARM_OFFSET_IMM + BFD_RELOC_ARM_T32_IMMEDIATE +ENUMX + BFD_RELOC_ARM_T32_IMM12 +ENUMX + BFD_RELOC_ARM_T32_ADD_PC12 ENUMX BFD_RELOC_ARM_SHIFT_IMM +ENUMX + BFD_RELOC_ARM_SMC ENUMX BFD_RELOC_ARM_SWI ENUMX @@ -2572,6 +2760,10 @@ ENUMX BFD_RELOC_ARM_CP_OFF_IMM ENUMX BFD_RELOC_ARM_CP_OFF_IMM_S2 +ENUMX + BFD_RELOC_ARM_T32_CP_OFF_IMM +ENUMX + BFD_RELOC_ARM_T32_CP_OFF_IMM_S2 ENUMX BFD_RELOC_ARM_ADR_IMM ENUMX @@ -2582,6 +2774,10 @@ ENUMX BFD_RELOC_ARM_IN_POOL ENUMX BFD_RELOC_ARM_OFFSET_IMM8 +ENUMX + BFD_RELOC_ARM_T32_OFFSET_U8 +ENUMX + BFD_RELOC_ARM_T32_OFFSET_IMM ENUMX BFD_RELOC_ARM_HWLITERAL ENUMX @@ -2590,34 +2786,30 @@ ENUMX BFD_RELOC_ARM_THUMB_IMM ENUMX BFD_RELOC_ARM_THUMB_SHIFT +ENUMDOC + These relocs are only used within the ARM assembler. They are not + (at present) written to any object files. + +ENUM + BFD_RELOC_SH_PCDISP8BY2 ENUMX - BFD_RELOC_ARM_THUMB_OFFSET + BFD_RELOC_SH_PCDISP12BY2 ENUMX - BFD_RELOC_ARM_GOT12 + BFD_RELOC_SH_IMM3 ENUMX - BFD_RELOC_ARM_GOT32 + BFD_RELOC_SH_IMM3U ENUMX - BFD_RELOC_ARM_JUMP_SLOT + BFD_RELOC_SH_DISP12 ENUMX - BFD_RELOC_ARM_COPY + BFD_RELOC_SH_DISP12BY2 ENUMX - BFD_RELOC_ARM_GLOB_DAT + BFD_RELOC_SH_DISP12BY4 ENUMX - BFD_RELOC_ARM_PLT32 + BFD_RELOC_SH_DISP12BY8 ENUMX - BFD_RELOC_ARM_RELATIVE + BFD_RELOC_SH_DISP20 ENUMX - BFD_RELOC_ARM_GOTOFF -ENUMX - BFD_RELOC_ARM_GOTPC -ENUMDOC - These relocs are only used within the ARM assembler. They are not - (at present) written to any object files. - -ENUM - BFD_RELOC_SH_PCDISP8BY2 -ENUMX - BFD_RELOC_SH_PCDISP12BY2 + BFD_RELOC_SH_DISP20BY8 ENUMX BFD_RELOC_SH_IMM4 ENUMX @@ -2781,16 +2973,6 @@ ENUMX ENUMDOC Renesas / SuperH SH relocs. Not all of these appear in object files. -ENUM - BFD_RELOC_THUMB_PCREL_BRANCH9 -ENUMX - BFD_RELOC_THUMB_PCREL_BRANCH12 -ENUMX - BFD_RELOC_THUMB_PCREL_BRANCH23 -ENUMDOC - Thumb 23-, 12- and 9-bit pc-relative branches. The lowest bit must - be zero and is not stored in the instruction. - ENUM BFD_RELOC_ARC_B22_PCREL ENUMDOC @@ -2805,6 +2987,169 @@ ENUMDOC stored in the instruction. The high 24 bits are installed in bits 23 through 0. +ENUM + BFD_RELOC_BFIN_16_IMM +ENUMDOC + ADI Blackfin 16 bit immediate absolute reloc. +ENUM + BFD_RELOC_BFIN_16_HIGH +ENUMDOC + ADI Blackfin 16 bit immediate absolute reloc higher 16 bits. +ENUM + BFD_RELOC_BFIN_4_PCREL +ENUMDOC + ADI Blackfin 'a' part of LSETUP. +ENUM + BFD_RELOC_BFIN_5_PCREL +ENUMDOC + ADI Blackfin. +ENUM + BFD_RELOC_BFIN_16_LOW +ENUMDOC + ADI Blackfin 16 bit immediate absolute reloc lower 16 bits. +ENUM + BFD_RELOC_BFIN_10_PCREL +ENUMDOC + ADI Blackfin. +ENUM + BFD_RELOC_BFIN_11_PCREL +ENUMDOC + ADI Blackfin 'b' part of LSETUP. +ENUM + BFD_RELOC_BFIN_12_PCREL_JUMP +ENUMDOC + ADI Blackfin. +ENUM + BFD_RELOC_BFIN_12_PCREL_JUMP_S +ENUMDOC + ADI Blackfin Short jump, pcrel. +ENUM + BFD_RELOC_BFIN_24_PCREL_CALL_X +ENUMDOC + ADI Blackfin Call.x not implemented. +ENUM + BFD_RELOC_BFIN_24_PCREL_JUMP_L +ENUMDOC + ADI Blackfin Long Jump pcrel. +ENUM + BFD_RELOC_BFIN_GOT17M4 +ENUMX + BFD_RELOC_BFIN_GOTHI +ENUMX + BFD_RELOC_BFIN_GOTLO +ENUMX + BFD_RELOC_BFIN_FUNCDESC +ENUMX + BFD_RELOC_BFIN_FUNCDESC_GOT17M4 +ENUMX + BFD_RELOC_BFIN_FUNCDESC_GOTHI +ENUMX + BFD_RELOC_BFIN_FUNCDESC_GOTLO +ENUMX + BFD_RELOC_BFIN_FUNCDESC_VALUE +ENUMX + BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4 +ENUMX + BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI +ENUMX + BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO +ENUMX + BFD_RELOC_BFIN_GOTOFF17M4 +ENUMX + BFD_RELOC_BFIN_GOTOFFHI +ENUMX + BFD_RELOC_BFIN_GOTOFFLO +ENUMDOC + ADI Blackfin FD-PIC relocations. +ENUM + BFD_RELOC_BFIN_GOT +ENUMDOC + ADI Blackfin GOT relocation. +ENUM + BFD_RELOC_BFIN_PLTPC +ENUMDOC + ADI Blackfin PLTPC relocation. +ENUM + BFD_ARELOC_BFIN_PUSH +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_CONST +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_ADD +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_SUB +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_MULT +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_DIV +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_MOD +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_LSHIFT +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_RSHIFT +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_AND +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_OR +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_XOR +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_LAND +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_LOR +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_LEN +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_NEG +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_COMP +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_PAGE +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_HWPAGE +ENUMDOC + ADI Blackfin arithmetic relocation. +ENUM + BFD_ARELOC_BFIN_ADDR +ENUMDOC + ADI Blackfin arithmetic relocation. + ENUM BFD_RELOC_D10V_10_PCREL_R ENUMDOC @@ -2903,6 +3248,17 @@ ENUM ENUMDOC DLX relocs +ENUM + BFD_RELOC_M32C_HI8 +ENUMX + BFD_RELOC_M32C_RL_JUMP +ENUMX + BFD_RELOC_M32C_RL_1ADDR +ENUMX + BFD_RELOC_M32C_RL_2ADDR +ENUMDOC + Renesas M16C/M32C Relocations. + ENUM BFD_RELOC_M32R_24 ENUMDOC @@ -2953,6 +3309,12 @@ ENUMX BFD_RELOC_M32R_RELATIVE ENUMX BFD_RELOC_M32R_GOTOFF +ENUMX + BFD_RELOC_M32R_GOTOFF_HI_ULO +ENUMX + BFD_RELOC_M32R_GOTOFF_HI_SLO +ENUMX + BFD_RELOC_M32R_GOTOFF_LO ENUMX BFD_RELOC_M32R_GOTPC24 ENUMX @@ -3056,6 +3418,11 @@ ENUM BFD_RELOC_V850_ALIGN ENUMDOC Used to maintain alignment whilst relaxing. +ENUM + BFD_RELOC_V850_LO16_SPLIT_OFFSET +ENUMDOC + This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu + instructions. ENUM BFD_RELOC_MN10300_32_PCREL ENUMDOC @@ -3266,6 +3633,11 @@ ENUM ENUMDOC This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit of program memory address) into 8 bit immediate value of LDI insn. +ENUM + BFD_RELOC_AVR_MS8_LDI +ENUMDOC + This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit + of 32 bit value) into 8 bit immediate value of LDI insn. ENUM BFD_RELOC_AVR_LO8_LDI_NEG ENUMDOC @@ -3283,6 +3655,11 @@ ENUMDOC This is a 16 bit reloc for the AVR that stores negated 8 bit value (most high 8 bit of program memory address) into 8 bit immediate value of LDI or SUBI insn. +ENUM + BFD_RELOC_AVR_MS8_LDI_NEG +ENUMDOC + This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb + of 32 bit value) into 8 bit immediate value of LDI insn. ENUM BFD_RELOC_AVR_LO8_LDI_PM ENUMDOC @@ -3320,6 +3697,21 @@ ENUM ENUMDOC This is a 32 bit reloc for the AVR that stores 23 bit value into 22 bits. +ENUM + BFD_RELOC_AVR_LDI +ENUMDOC + This is a 16 bit reloc for the AVR that stores all needed bits + for absolute addressing with ldi with overflow check to linktime +ENUM + BFD_RELOC_AVR_6 +ENUMDOC + This is a 6 bit reloc for the AVR that stores offset for ldd/std + instructions +ENUM + BFD_RELOC_AVR_6_ADIW +ENUMDOC + This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw + instructions ENUM BFD_RELOC_390_12 @@ -3770,6 +4162,132 @@ ENUMDOC Motorola 68HC12 reloc. This is the 5 bits of a value. +ENUM + BFD_RELOC_16C_NUM08 +ENUMX + BFD_RELOC_16C_NUM08_C +ENUMX + BFD_RELOC_16C_NUM16 +ENUMX + BFD_RELOC_16C_NUM16_C +ENUMX + BFD_RELOC_16C_NUM32 +ENUMX + BFD_RELOC_16C_NUM32_C +ENUMX + BFD_RELOC_16C_DISP04 +ENUMX + BFD_RELOC_16C_DISP04_C +ENUMX + BFD_RELOC_16C_DISP08 +ENUMX + BFD_RELOC_16C_DISP08_C +ENUMX + BFD_RELOC_16C_DISP16 +ENUMX + BFD_RELOC_16C_DISP16_C +ENUMX + BFD_RELOC_16C_DISP24 +ENUMX + BFD_RELOC_16C_DISP24_C +ENUMX + BFD_RELOC_16C_DISP24a +ENUMX + BFD_RELOC_16C_DISP24a_C +ENUMX + BFD_RELOC_16C_REG04 +ENUMX + BFD_RELOC_16C_REG04_C +ENUMX + BFD_RELOC_16C_REG04a +ENUMX + BFD_RELOC_16C_REG04a_C +ENUMX + BFD_RELOC_16C_REG14 +ENUMX + BFD_RELOC_16C_REG14_C +ENUMX + BFD_RELOC_16C_REG16 +ENUMX + BFD_RELOC_16C_REG16_C +ENUMX + BFD_RELOC_16C_REG20 +ENUMX + BFD_RELOC_16C_REG20_C +ENUMX + BFD_RELOC_16C_ABS20 +ENUMX + BFD_RELOC_16C_ABS20_C +ENUMX + BFD_RELOC_16C_ABS24 +ENUMX + BFD_RELOC_16C_ABS24_C +ENUMX + BFD_RELOC_16C_IMM04 +ENUMX + BFD_RELOC_16C_IMM04_C +ENUMX + BFD_RELOC_16C_IMM16 +ENUMX + BFD_RELOC_16C_IMM16_C +ENUMX + BFD_RELOC_16C_IMM20 +ENUMX + BFD_RELOC_16C_IMM20_C +ENUMX + BFD_RELOC_16C_IMM24 +ENUMX + BFD_RELOC_16C_IMM24_C +ENUMX + BFD_RELOC_16C_IMM32 +ENUMX + BFD_RELOC_16C_IMM32_C +ENUMDOC + NS CR16C Relocations. + +ENUM + BFD_RELOC_CRX_REL4 +ENUMX + BFD_RELOC_CRX_REL8 +ENUMX + BFD_RELOC_CRX_REL8_CMP +ENUMX + BFD_RELOC_CRX_REL16 +ENUMX + BFD_RELOC_CRX_REL24 +ENUMX + BFD_RELOC_CRX_REL32 +ENUMX + BFD_RELOC_CRX_REGREL12 +ENUMX + BFD_RELOC_CRX_REGREL22 +ENUMX + BFD_RELOC_CRX_REGREL28 +ENUMX + BFD_RELOC_CRX_REGREL32 +ENUMX + BFD_RELOC_CRX_ABS16 +ENUMX + BFD_RELOC_CRX_ABS32 +ENUMX + BFD_RELOC_CRX_NUM8 +ENUMX + BFD_RELOC_CRX_NUM16 +ENUMX + BFD_RELOC_CRX_NUM32 +ENUMX + BFD_RELOC_CRX_IMM16 +ENUMX + BFD_RELOC_CRX_IMM32 +ENUMX + BFD_RELOC_CRX_SWITCH8 +ENUMX + BFD_RELOC_CRX_SWITCH16 +ENUMX + BFD_RELOC_CRX_SWITCH32 +ENUMDOC + NS CRX Relocations. + ENUM BFD_RELOC_CRIS_BDISP8 ENUMX @@ -3778,6 +4296,16 @@ ENUMX BFD_RELOC_CRIS_SIGNED_6 ENUMX BFD_RELOC_CRIS_UNSIGNED_6 +ENUMX + BFD_RELOC_CRIS_SIGNED_8 +ENUMX + BFD_RELOC_CRIS_UNSIGNED_8 +ENUMX + BFD_RELOC_CRIS_SIGNED_16 +ENUMX + BFD_RELOC_CRIS_UNSIGNED_16 +ENUMX + BFD_RELOC_CRIS_LAPCQ_OFFSET ENUMX BFD_RELOC_CRIS_UNSIGNED_4 ENUMDOC @@ -3920,6 +4448,17 @@ ENUMX ENUMDOC Sony Xstormy16 Relocations. +ENUM + BFD_RELOC_XC16X_PAG +ENUMX + BFD_RELOC_XC16X_POF +ENUMX + BFD_RELOC_XC16X_SEG +ENUMX + BFD_RELOC_XC16X_SOF +ENUMDOC + Infineon Relocations. + ENUM BFD_RELOC_VAX_GLOB_DAT ENUMX @@ -3928,7 +4467,32 @@ ENUMX BFD_RELOC_VAX_RELATIVE ENUMDOC Relocations used by VAX ELF. - + +ENUM + BFD_RELOC_MT_PC16 +ENUMDOC + Morpho MT - 16 bit immediate relocation. +ENUM + BFD_RELOC_MT_HI16 +ENUMDOC + Morpho MT - Hi 16 bits of an address. +ENUM + BFD_RELOC_MT_LO16 +ENUMDOC + Morpho MT - Low 16 bits of an address. +ENUM + BFD_RELOC_MT_GNU_VTINHERIT +ENUMDOC + Morpho MT - Used to tell the linker which vtable entries are used. +ENUM + BFD_RELOC_MT_GNU_VTENTRY +ENUMDOC + Morpho MT - Used to tell the linker which vtable entries are used. +ENUM + BFD_RELOC_MT_PCINSN8 +ENUMDOC + Morpho MT - 8 bit immediate relocation. + ENUM BFD_RELOC_MSP430_10_PCREL ENUMX @@ -3939,6 +4503,10 @@ ENUMX BFD_RELOC_MSP430_16_PCREL_BYTE ENUMX BFD_RELOC_MSP430_16_BYTE +ENUMX + BFD_RELOC_MSP430_2X_PCREL +ENUMX + BFD_RELOC_MSP430_RL_PCREL ENUMDOC msp430 specific relocation codes @@ -3970,6 +4538,87 @@ ENUM ENUMDOC Xtensa relocation used in ELF object files for symbols that may require PLT entries. Otherwise, this is just a generic 32-bit relocation. +ENUM + BFD_RELOC_XTENSA_DIFF8 +ENUMX + BFD_RELOC_XTENSA_DIFF16 +ENUMX + BFD_RELOC_XTENSA_DIFF32 +ENUMDOC + Xtensa relocations to mark the difference of two local symbols. + These are only needed to support linker relaxation and can be ignored + when not relaxing. The field is set to the value of the difference + assuming no relaxation. The relocation encodes the position of the + first symbol so the linker can determine whether to adjust the field + value. +ENUM + BFD_RELOC_XTENSA_SLOT0_OP +ENUMX + BFD_RELOC_XTENSA_SLOT1_OP +ENUMX + BFD_RELOC_XTENSA_SLOT2_OP +ENUMX + BFD_RELOC_XTENSA_SLOT3_OP +ENUMX + BFD_RELOC_XTENSA_SLOT4_OP +ENUMX + BFD_RELOC_XTENSA_SLOT5_OP +ENUMX + BFD_RELOC_XTENSA_SLOT6_OP +ENUMX + BFD_RELOC_XTENSA_SLOT7_OP +ENUMX + BFD_RELOC_XTENSA_SLOT8_OP +ENUMX + BFD_RELOC_XTENSA_SLOT9_OP +ENUMX + BFD_RELOC_XTENSA_SLOT10_OP +ENUMX + BFD_RELOC_XTENSA_SLOT11_OP +ENUMX + BFD_RELOC_XTENSA_SLOT12_OP +ENUMX + BFD_RELOC_XTENSA_SLOT13_OP +ENUMX + BFD_RELOC_XTENSA_SLOT14_OP +ENUMDOC + Generic Xtensa relocations for instruction operands. Only the slot + number is encoded in the relocation. The relocation applies to the + last PC-relative immediate operand, or if there are no PC-relative + immediates, to the last immediate operand. +ENUM + BFD_RELOC_XTENSA_SLOT0_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT1_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT2_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT3_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT4_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT5_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT6_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT7_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT8_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT9_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT10_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT11_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT12_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT13_ALT +ENUMX + BFD_RELOC_XTENSA_SLOT14_ALT +ENUMDOC + Alternate Xtensa relocations. Only the slot is encoded in the + relocation. The meaning of these relocations is opcode-specific. ENUM BFD_RELOC_XTENSA_OP0 ENUMX @@ -3977,23 +4626,40 @@ ENUMX ENUMX BFD_RELOC_XTENSA_OP2 ENUMDOC - Generic Xtensa relocations. Only the operand number is encoded - in the relocation. The details are determined by extracting the - instruction opcode. + Xtensa relocations for backward compatibility. These have all been + replaced by BFD_RELOC_XTENSA_SLOT0_OP. ENUM BFD_RELOC_XTENSA_ASM_EXPAND ENUMDOC - Xtensa relocation to mark that the assembler expanded the + Xtensa relocation to mark that the assembler expanded the instructions from an original target. The expansion size is encoded in the reloc size. ENUM BFD_RELOC_XTENSA_ASM_SIMPLIFY ENUMDOC - Xtensa relocation to mark that the linker should simplify - assembler-expanded instructions. This is commonly used - internally by the linker after analysis of a + Xtensa relocation to mark that the linker should simplify + assembler-expanded instructions. This is commonly used + internally by the linker after analysis of a BFD_RELOC_XTENSA_ASM_EXPAND. +ENUM + BFD_RELOC_Z80_DISP8 +ENUMDOC + 8 bit signed offset in (ix+d) or (iy+d). + +ENUM + BFD_RELOC_Z8K_DISP7 +ENUMDOC + DJNZ offset. +ENUM + BFD_RELOC_Z8K_CALLR +ENUMDOC + CALR offset. +ENUM + BFD_RELOC_Z8K_IMM4L +ENUMDOC + 4 bit value. + ENDSENUM BFD_RELOC_UNUSED CODE_FRAGMENT @@ -4023,7 +4689,7 @@ bfd_reloc_type_lookup (bfd *abfd, bfd_reloc_code_real_type code) } static reloc_howto_type bfd_howto_32 = -HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_bitfield, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE); +HOWTO (0, 00, 2, 32, FALSE, 0, complain_overflow_dont, 0, "VRT32", FALSE, 0xffffffff, 0xffffffff, TRUE); /* INTERNAL_FUNCTION @@ -4096,8 +4762,7 @@ SYNOPSIS DESCRIPTION Provides default handling for relaxing for back ends which - don't do relaxing -- i.e., does nothing except make sure that the - final size of the section is set. + don't do relaxing. */ bfd_boolean @@ -4106,11 +4771,6 @@ bfd_generic_relax_section (bfd *abfd ATTRIBUTE_UNUSED, struct bfd_link_info *link_info ATTRIBUTE_UNUSED, bfd_boolean *again) { - /* We're not relaxing the section, so just copy the size info if it's - zero. Someone else, like bfd_merge_sections, might have set it, so - don't overwrite a non-zero value. */ - if (section->_cooked_size == 0) - section->_cooked_size = section->_raw_size; *again = FALSE; return TRUE; } @@ -4130,7 +4790,7 @@ DESCRIPTION bfd_boolean bfd_generic_gc_sections (bfd *abfd ATTRIBUTE_UNUSED, - struct bfd_link_info *link_info ATTRIBUTE_UNUSED) + struct bfd_link_info *info ATTRIBUTE_UNUSED) { return TRUE; } @@ -4189,6 +4849,7 @@ bfd_generic_get_relocated_section_contents (bfd *abfd, long reloc_size = bfd_get_reloc_upper_bound (input_bfd, input_section); arelent **reloc_vector = NULL; long reloc_count; + bfd_size_type sz; if (reloc_size < 0) goto error_return; @@ -4198,22 +4859,10 @@ bfd_generic_get_relocated_section_contents (bfd *abfd, goto error_return; /* Read in the section. */ - if (!bfd_get_section_contents (input_bfd, - input_section, - data, - 0, - input_section->_raw_size)) + sz = input_section->rawsize ? input_section->rawsize : input_section->size; + if (!bfd_get_section_contents (input_bfd, input_section, data, 0, sz)) goto error_return; - /* Don't set input_section->_cooked_size here. The caller has set - _cooked_size or called bfd_relax_section, which sets _cooked_size. - Despite using this generic relocation function, some targets perform - target-specific relaxation or string merging, which happens before - this function is called. We do not want to clobber the _cooked_size - they computed. */ - - input_section->reloc_done = TRUE; - reloc_count = bfd_canonicalize_reloc (input_bfd, input_section, reloc_vector, @@ -4264,7 +4913,8 @@ bfd_generic_get_relocated_section_contents (bfd *abfd, break; case bfd_reloc_overflow: if (!((*link_info->callbacks->reloc_overflow) - (link_info, bfd_asymbol_name (*(*parent)->sym_ptr_ptr), + (link_info, NULL, + bfd_asymbol_name (*(*parent)->sym_ptr_ptr), (*parent)->howto->name, (*parent)->addend, input_bfd, input_section, (*parent)->address))) goto error_return;