X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=cpu%2Fm32c.cpu;h=ab65fc13626731ce6d2a03fc0fbaf4ede1f1115e;hb=22aa1d51198689f5f3f01a874b405bf4449cbfb0;hp=dfbd1afe5db8f32cfa2f57216ededb2b94fe3dde;hpb=49f58d10f8827774889f6dbc79a934943be8bc44;p=deliverable%2Fbinutils-gdb.git diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu index dfbd1afe5d..ab65fc1362 100644 --- a/cpu/m32c.cpu +++ b/cpu/m32c.cpu @@ -1,7 +1,25 @@ ; Renesas M32C CPU description. -*- Scheme -*- -; Copyright (C) 2005 Red Hat, Inc. -; This file is part of CGEN. -; See file COPYING.CGEN for details. +; +; Copyright 2005, 2006, 2007, 2009 Free Software Foundation, Inc. +; +; Contributed by Red Hat Inc; developed under contract from Renesas. +; +; This file is part of the GNU Binutils. +; +; This program is free software; you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation; either version 3 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, write to the Free Software +; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, +; MA 02110-1301, USA. (include "simplify.inc") @@ -122,6 +140,13 @@ ) ) +(define-attr + (type enum) + (name RL_TYPE) + (values NONE JUMP 1ADDR 2ADDR) + (default NONE) + ) + ; Macros to simplify MACH attribute specification. (define-pmacro all-isas () (ISA m16c,m32c)) @@ -133,6 +158,11 @@ (define-pmacro (machine size) (MACH (.sym m size c)) (ISA (.sym m size c))) + +(define-pmacro RL_JUMP (RL_TYPE JUMP)) +(define-pmacro RL_1ADDR (RL_TYPE 1ADDR)) +(define-pmacro RL_2ADDR (RL_TYPE 2ADDR)) + ;============================================================= ; Fields @@ -178,6 +208,7 @@ (dnf f-16-1 "opcode" (all-isas) 16 1) (dnf f-16-2 "opcode" (all-isas) 16 2) (dnf f-16-4 "opcode" (all-isas) 16 4) +(dnf f-16-8 "opcode" (all-isas) 16 8) (dnf f-18-1 "opcode" (all-isas) 18 1) (dnf f-18-2 "opcode" (all-isas) 18 2) (dnf f-18-3 "opcode" (all-isas) 18 3) @@ -187,6 +218,8 @@ (dnf f-20-4 "opcode" (all-isas) 20 4) (dnf f-21-3 "opcode" (all-isas) 21 3) (dnf f-24-2 "opcode" (all-isas) 24 2) +(dnf f-24-8 "opcode" (all-isas) 24 8) +(dnf f-32-16 "opcode" (all-isas) 32 16) ;------------------------------------------------------------- ; Registers @@ -207,7 +240,7 @@ ; r1l 10'b 11'b ; r1h 11'b 01'b (df f-src32-rn-unprefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 10 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract ) ; QI mode gr encoding for m32c is different than for m16c. The hardware @@ -219,7 +252,7 @@ ; r1l 10'b 11'b ; r1h 11'b 01'b (df f-src32-rn-prefixed-QI "source Rn QI for m32c" (MACH32 m32c-isa) 18 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract ) ; HI mode gr encoding for m32c is different than for m16c. The hardware @@ -283,11 +316,11 @@ ; r1l 10'b 11'b ; r1h 11'b 01'b (df f-dst32-rn-unprefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 8 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract ) (df f-dst32-rn-prefixed-QI "destination Rn QI for m32c" (MACH32 m32c-isa) 16 2 UINT - ((value pc) (or USI (and (sll (inv value) 1) 2) (and (srl value 1) 1))) ; insert + ((value pc) (or USI (and (inv (sll value 1)) 2) (and (srl value 1) 1))) ; insert ((value pc) (or USI (and (inv (srl value 1)) 1) (and (sll value 1) 2))) ; extract ) ; HI mode gr encoding for m32c is different than for m16c. The hardware @@ -403,42 +436,42 @@ (df f-dsp-8-u16 "16 bit unsigned" (all-isas) 8 16 UINT ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert + (and (srl value 8) #xff) + (sll (and value #xff) 8))) ; insert ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract + (and UHI (srl UHI value 8) #xff) + (sll UHI (and UHI value #xff) 8))) ; extract ) (df f-dsp-8-s16 "8 bit signed" (all-isas) 8 16 INT ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; insert ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; extract ) (df f-dsp-16-u16 "16 bit unsigned" (all-isas) 16 16 UINT ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert + (and (srl value 8) #xff) + (sll (and value #xff) 8))) ; insert ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract + (and UHI (srl UHI value 8) #xff) + (sll UHI (and UHI value #xff) 8))) ; extract ) (df f-dsp-16-s16 "16 bit signed" (all-isas) 16 16 INT ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; insert ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; extract ) (dnmf f-dsp-24-u16 "16 bit unsigned" (all-isas) UINT @@ -471,72 +504,92 @@ (df f-dsp-32-u16 "16 bit unsigned" (all-isas) 32 16 UINT ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert + (and (srl value 8) #xff) + (sll (and value #xff) 8))) ; insert ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract + (and UHI (srl UHI value 8) #xff) + (sll UHI (and UHI value #xff) 8))) ; extract ) (df f-dsp-32-s16 "16 bit signed" (all-isas) 32 16 INT ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; insert ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; extract ) (df f-dsp-40-u16 "16 bit unsigned" (all-isas) 40 16 UINT ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert + (and (srl value 8) #xff) + (sll (and value #xff) 8))) ; insert ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract + (and UHI (srl UHI value 8) #xff) + (sll UHI (and UHI value #xff) 8))) ; extract ) (df f-dsp-40-s16 "16 bit signed" (all-isas) 40 16 INT ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; insert ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; extract ) (df f-dsp-48-u16 "16 bit unsigned" (all-isas) 48 16 UINT ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert + (and (srl value 8) #xff) + (sll (and value #xff) 8))) ; insert ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract + (and UHI (srl UHI value 8) #xff) + (sll UHI (and UHI value #xff) 8))) ; extract ) (df f-dsp-48-s16 "16 bit signed" (all-isas) 48 16 INT ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; insert ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; extract ) (df f-dsp-64-u16 "16 bit unsigned" (all-isas) 64 16 UINT ((value pc) (or UHI - (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))) ; insert + (and (srl value 8) #xff) + (sll (and value #xff) 8))) ; insert ((value pc) (or UHI - (and UHI (srl UHI value 8) #x00ff) - (and UHI (sll UHI value 8) #xff00))) ; extract -) + (and UHI (srl UHI value 8) #xff) + (sll UHI (and UHI value #xff) 8))) ; extract +) +(df f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT + ((value pc) (sub SI (xor (or SI (or (and (srl value 16) #xff) + (and value #xff00)) + (sll (and value #xff) 16)) + #x800000) #x800000)) + ((value pc) (sub SI (xor (or SI + (or (and (srl value 16) #xff) + (and value #xff00)) + (sll (and value #xff) 16)) + #x800000) #x800000)) + ) + +(df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT + ((value pc) (or SI + (or (srl value 16) (and value #xff00)) + (sll (and value #xff) 16))) + ((value pc) (or SI + (or (srl value 16) (and value #xff00)) + (sll (and value #xff) 16))) + ) (dnmf f-dsp-16-u24 "24 bit unsigned" (all-isas) UINT (f-dsp-16-u16 f-dsp-32-u8) @@ -567,12 +620,25 @@ (or USI (and (srl value 16) #x0000ff) (and value #x00ff00)) - (and (sll value 16) #xff0000))) ; insert + (and (sll value 16) #xff0000))) ; insert ((value pc) (or USI (or USI - (and USI (srl UHI value 16) #x0000ff) - (and USI value #x00ff00)) - (and USI (sll UHI value 16) #xff0000))) ; extract + (and USI (srl value 16) #x0000ff) + (and USI value #x00ff00)) + (and USI (sll value 16) #xff0000))) ; extract +) + +(df f-dsp-40-u20 "20 bit unsigned" (all-isas) 40 20 UINT + ((value pc) (or USI + (or USI + (and (srl value 16) #x0000ff) + (and value #x00ff00)) + (and (sll value 16) #x0f0000))) ; insert + ((value pc) (or USI + (or USI + (and USI (srl value 16) #x0000ff) + (and USI value #x00ff00)) + (and USI (sll value 16) #x0f0000))) ; extract ) (df f-dsp-40-u24 "24 bit unsigned" (all-isas) 40 24 UINT @@ -580,12 +646,12 @@ (or USI (and (srl value 16) #x0000ff) (and value #x00ff00)) - (and (sll value 16) #xff0000))) ; insert + (and (sll value 16) #xff0000))) ; insert ((value pc) (or USI (or USI - (and USI (srl UHI value 16) #x0000ff) - (and USI value #x00ff00)) - (and USI (sll UHI value 16) #xff0000))) ; extract + (and USI (srl value 16) #x0000ff) + (and USI value #x00ff00)) + (and USI (sll value 16) #xff0000))) ; extract ) (dnmf f-dsp-40-s32 "32 bit signed" (all-isas) INT @@ -600,6 +666,17 @@ ) ) +(dnmf f-dsp-48-u20 "20 bit unsigned" (all-isas) UINT + (f-dsp-48-u16 f-dsp-64-u8) + (sequence () ; insert + (set (ifield f-dsp-64-u8) (and (srl (ifield f-dsp-48-u20) 16) #x0f)) + (set (ifield f-dsp-48-u16) (and (ifield f-dsp-48-u20) #xffff)) + ) + (sequence () ; extract + (set (ifield f-dsp-48-u20) (or (and (ifield f-dsp-48-u16) #xffff) + (and (sll (ifield f-dsp-64-u8) 16) #x0f0000))) + ) +) (dnmf f-dsp-48-u24 "24 bit unsigned" (all-isas) UINT (f-dsp-48-u16 f-dsp-64-u8) (sequence () ; insert @@ -643,22 +720,22 @@ (ext INT (or SI (or SI - (and (srl value 24) #x000000ff) - (and (srl value 8) #x0000ff00)) + (and (srl value 24) #x00ff) + (and (srl value 8) #xff00)) (or SI - (and (sll value 8) #x00ff0000) - (and (sll value 24) #xff000000))))) + (sll (and value #xff00) 8) + (sll (and value #x00ff) 24))))) ;; extract ((value pc) (ext INT (or SI (or SI - (and (srl value 24) #x000000ff) - (and (srl value 8) #x0000ff00)) + (and (srl value 24) #x00ff) + (and (srl value 8) #xff00)) (or SI - (and (sll value 8) #x00ff0000) - (and (sll value 24) #xff000000))))) + (sll (and value #xff00) 8) + (sll (and value #x00ff) 24))))) ) (dnmf f-dsp-48-u32 "32 bit unsigned" (all-isas) UINT @@ -669,7 +746,7 @@ ) (sequence () ; extract (set (ifield f-dsp-48-u32) (or (and (ifield f-dsp-48-u16) #xffff) - (and (sll (ifield f-dsp-64-u16) 16) #xffff0000))) + (sll (and (ifield f-dsp-64-u16) #xffff) 16))) ) ) @@ -681,7 +758,7 @@ ) (sequence () ; extract (set (ifield f-dsp-48-s32) (or (and (ifield f-dsp-48-u16) #xffff) - (and (sll (ifield f-dsp-64-u16) 16) #xffff0000))) + (sll (and (ifield f-dsp-64-u16) #xffff) 16))) ) ) @@ -704,12 +781,12 @@ (df f-dsp-64-s16 " 16 bit signed" (all-isas) 64 16 INT ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; insert + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; insert ((value pc) (ext INT (trunc HI - (or (and (srl value 8) #x00ff) - (and (sll value 8) #xff00))))) ; extract + (or (and (srl value 8) #xff) + (sll (and value #xff) 8))))) ; extract ) ;------------------------------------------------------------- @@ -750,7 +827,7 @@ (set (ifield f-dsp-16-s8) (sra INT (ifield f-bitbase32-16-s11-unprefixed) 3)) ) (sequence () ; extract - (set (ifield f-bitbase32-16-s11-unprefixed) (or (sll (ifield f-dsp-16-s8) 3) + (set (ifield f-bitbase32-16-s11-unprefixed) (or (mul (ifield f-dsp-16-s8) 8) (ifield f-bitno32-unprefixed))) ) ) @@ -772,7 +849,7 @@ (set (ifield f-dsp-16-s16) (sra INT (ifield f-bitbase32-16-s19-unprefixed) 3)) ) (sequence () ; extract - (set (ifield f-bitbase32-16-s19-unprefixed) (or (sll (ifield f-dsp-16-s16) 3) + (set (ifield f-bitbase32-16-s19-unprefixed) (or (mul (ifield f-dsp-16-s16) 8) (ifield f-bitno32-unprefixed))) ) ) @@ -808,7 +885,7 @@ (set (ifield f-dsp-24-s8) (sra INT (ifield f-bitbase32-24-s11-prefixed) 3)) ) (sequence () ; extract - (set (ifield f-bitbase32-24-s11-prefixed) (or (sll (ifield f-dsp-24-s8) 3) + (set (ifield f-bitbase32-24-s11-prefixed) (or (mul (ifield f-dsp-24-s8) 8) (ifield f-bitno32-prefixed))) ) ) @@ -836,7 +913,7 @@ ) (sequence () ; extract (set (ifield f-bitbase32-24-s19-prefixed) (or (sll (ifield f-dsp-24-u8) 3) - (or (sll (ifield f-dsp-32-s8) 11) + (or (mul (ifield f-dsp-32-s8) 2048) (ifield f-bitno32-prefixed)))) ) ) @@ -859,15 +936,16 @@ ; Labels ;------------------------------------------------------------- -(df f-lab-5-3 "3 bit pc relative signed offset" (PCREL-ADDR all-isas) 5 3 INT +(df f-lab-5-3 "3 bit pc relative unsigned offset" (PCREL-ADDR all-isas) 5 3 UINT ((value pc) (sub SI value (add SI pc 2))) ; insert ((value pc) (add SI value (add SI pc 2))) ; extract ) (dnmf f-lab32-jmp-s "unsigned 3 bit pc relative offset" (PCREL-ADDR all-isas) UINT (f-2-2 f-7-1) - (sequence () ; insert - (set (ifield f-7-1) (and (sub (ifield f-lab32-jmp-s) pc) #x1)) - (set (ifield f-2-2) (srl (sub (ifield f-lab32-jmp-s) pc) 1)) + (sequence ((SI val)) ; insert + (set val (sub (sub (ifield f-lab32-jmp-s) pc) 2)) + (set (ifield f-7-1) (and val #x1)) + (set (ifield f-2-2) (srl val 1)) ) (sequence () ; extract (set (ifield f-lab32-jmp-s) (add pc (add (or (sll (ifield f-2-2) 1) @@ -881,9 +959,12 @@ ) (df f-lab-8-16 "16 bit pc relative signed offset" (PCREL-ADDR SIGN-OPT all-isas) 8 16 UINT ((value pc) (or SI (sll (and (sub value (add pc 1)) #xff) 8) - (srl (and (sub value (add pc 1)) #xffff) 8))) - ((value pc) (add SI (or (srl (and value #xffff) 8) - (sra (sll (and value #xff) 24) 16)) (add pc 1))) + (srl (and (sub value (add pc 1)) #xff00) 8))) + ((value pc) (add SI (sub (xor (or (srl (and value #xff00) 8) + (sll (and value #xff) 8)) + #x8000) + #x8000) + (add pc 1))) ) (df f-lab-8-24 "24 bit absolute" (all-isas ABS-ADDR) 8 24 UINT ((value pc) (or SI @@ -994,7 +1075,7 @@ (indices keyword "" (("r2r0" 0) ("r3r1" 1))) (get (index) (or SI (and (reg h-gr index) #xffff) - (and (sll (reg h-gr (add index 2)) 16) #xffff0000))) + (sll (and (reg h-gr (add index 2)) #xffff) 16))) (set (index newval) (sequence () (set (reg h-gr index) (and newval #xffff)) (set (reg h-gr (add index 2)) (srl newval 16))))) @@ -1727,6 +1808,14 @@ h-sint DFLT f-dsp-8-s8 ((parse "signed8")) () () ) +(define-full-operand Dsp-8-s24 "signed 24 bit displacement at offset 8 bits" (all-isas) + h-sint DFLT f-dsp-8-s24 + ((parse "signed24")) () () +) +(define-full-operand Dsp-8-u24 "unsigned 24 bit displacement at offset 8 bits" (all-isas) + h-uint DFLT f-dsp-8-u24 + ((parse "unsigned24")) () () +) (define-full-operand Dsp-10-u6 "unsigned 6 bit displacement at offset 10 bits" (all-isas) h-uint DFLT f-dsp-10-u6 ((parse "unsigned6")) () () @@ -1808,7 +1897,7 @@ ((parse "unsigned8")) () () ) (define-full-operand Dsp-40-s8 "signed 8 bit displacement at offset 40 bits" (all-isas) - h-uint DFLT f-dsp-40-s8 + h-sint DFLT f-dsp-40-s8 ((parse "signed8")) () () ) (define-full-operand Dsp-40-u16 "unsigned 16 bit displacement at offset 40 bits" (all-isas) @@ -1816,9 +1905,13 @@ ((parse "unsigned16")) () () ) (define-full-operand Dsp-40-s16 "signed 16 bit displacement at offset 40 bits" (all-isas) - h-uint DFLT f-dsp-40-s16 + h-sint DFLT f-dsp-40-s16 ((parse "signed16")) () () ) +(define-full-operand Dsp-40-u20 "unsigned 20 bit displacement at offset 40 bits" (all-isas) + h-uint DFLT f-dsp-40-u20 + ((parse "unsigned20")) () () +) (define-full-operand Dsp-40-u24 "unsigned 24 bit displacement at offset 40 bits" (all-isas) h-uint DFLT f-dsp-40-u24 ((parse "unsigned24")) () () @@ -1828,7 +1921,7 @@ ((parse "unsigned8")) () () ) (define-full-operand Dsp-48-s8 "signed 8 bit displacement at offset 48 bits" (all-isas) - h-uint DFLT f-dsp-48-s8 + h-sint DFLT f-dsp-48-s8 ((parse "signed8")) () () ) (define-full-operand Dsp-48-u16 "unsigned 16 bit displacement at offset 48 bits" (all-isas) @@ -1836,9 +1929,13 @@ ((parse "unsigned16")) () () ) (define-full-operand Dsp-48-s16 "signed 16 bit displacement at offset 48 bits" (all-isas) - h-uint DFLT f-dsp-48-s16 + h-sint DFLT f-dsp-48-s16 ((parse "signed16")) () () ) +(define-full-operand Dsp-48-u20 "unsigned 24 bit displacement at offset 40 bits" (all-isas) + h-uint DFLT f-dsp-48-u20 + ((parse "unsigned24")) () () +) (define-full-operand Dsp-48-u24 "unsigned 24 bit displacement at offset 48 bits" (all-isas) h-uint DFLT f-dsp-48-u24 ((parse "unsigned24")) () () @@ -1848,6 +1945,10 @@ h-sint DFLT f-imm-8-s4 ((parse "signed4")) () () ) +(define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas) + h-sint DFLT f-imm-8-s4 + ((parse "signed4n") (print "signed4n")) () () +) (define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas) h-shimm DFLT f-imm-8-s4 () () () @@ -1864,12 +1965,16 @@ h-sint DFLT f-imm-12-s4 ((parse "signed4")) () () ) +(define-full-operand Imm-12-s4n "negated 4 bit immediate at offset 12 bits" (all-isas) + h-sint DFLT f-imm-12-s4 + ((parse "signed4n") (print "signed4n")) () () +) (define-full-operand Imm-sh-12-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas) h-shimm DFLT f-imm-12-s4 () () () ) (define-full-operand Imm-13-u3 "signed 3 bit immediate at offset 13 bits" (all-isas) - h-uint DFLT f-imm-13-u3 + h-sint DFLT f-imm-13-u3 ((parse "signed4")) () () ) (define-full-operand Imm-20-s4 "signed 4 bit immediate at offset 20 bits" (all-isas) @@ -1960,6 +2065,10 @@ h-sint DFLT f-imm3-S ((parse "imm3_S")) () () ) +(define-full-operand Bit3-S "3 bit bit number" (m32c-isa) + h-sint DFLT f-imm3-S + ((parse "bit3_S")) () () +) ;------------------------------------------------------------- ; Bit numbers @@ -1977,7 +2086,7 @@ ((parse "unsigned_bitbase8") (print "unsigned_bitbase")) () () ) (define-full-operand BitBase16-16-s8 "signed bit,base:8 at offset 16for m16c" (m16c-isa) - h-uint DFLT f-dsp-16-s8 + h-sint DFLT f-dsp-16-s8 ((parse "signed_bitbase8") (print "signed_bitbase")) () () ) (define-full-operand BitBase16-16-u16 "unsigned bit,base:16 at offset 16 for m16c" (m16c-isa) @@ -1985,7 +2094,7 @@ ((parse "unsigned_bitbase16") (print "unsigned_bitbase")) () () ) (define-full-operand BitBase16-8-u11-S "signed bit,base:11 at offset 16 for m16c" (m16c-isa) - h-sint DFLT f-bitbase16-u11-S + h-uint DFLT f-bitbase16-u11-S ((parse "unsigned_bitbase11") (print "unsigned_bitbase")) () () ) @@ -2033,15 +2142,21 @@ ; Labels ;------------------------------------------------------------- -(dnop Lab-5-3 "3 bit label" (all-isas) h-iaddr f-lab-5-3) -(dnop Lab32-jmp-s "3 bit label" (all-isas) h-iaddr f-lab32-jmp-s) -(dnop Lab-8-8 "8 bit label" (all-isas) h-iaddr f-lab-8-8) -(dnop Lab-8-16 "16 bit label" (all-isas) h-iaddr f-lab-8-16) -(dnop Lab-8-24 "24 bit label" (all-isas) h-iaddr f-lab-8-24) -(dnop Lab-16-8 "8 bit label" (all-isas) h-iaddr f-lab-16-8) -(dnop Lab-24-8 "8 bit label" (all-isas) h-iaddr f-lab-24-8) -(dnop Lab-32-8 "8 bit label" (all-isas) h-iaddr f-lab-32-8) -(dnop Lab-40-8 "8 bit label" (all-isas) h-iaddr f-lab-40-8) +(define-full-operand Lab-5-3 "3 bit label" (all-isas RELAX) + h-iaddr DFLT f-lab-5-3 + ((parse "lab_5_3")) () () ) + +(define-full-operand Lab32-jmp-s "3 bit label" (all-isas RELAX) + h-iaddr DFLT f-lab32-jmp-s + ((parse "lab_5_3")) () () ) + +(dnop Lab-8-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-8-8) +(dnop Lab-8-16 "16 bit label" (all-isas RELAX) h-iaddr f-lab-8-16) +(dnop Lab-8-24 "24 bit label" (all-isas RELAX) h-iaddr f-lab-8-24) +(dnop Lab-16-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-16-8) +(dnop Lab-24-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-24-8) +(dnop Lab-32-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-32-8) +(dnop Lab-40-8 "8 bit label" (all-isas RELAX) h-iaddr f-lab-40-8) ;------------------------------------------------------------- ; Condition code bits @@ -2133,6 +2248,9 @@ (define-pmacro (mem16 mode address) (mem mode (and #xffff address))) +(define-pmacro (mem20 mode address) + (mem mode (and #xfffff address))) + (define-pmacro (mem32 mode address) (mem mode (and #xffffff address))) @@ -2365,6 +2483,19 @@ (getter (mem16 xmode (add Dsp-16-u16 Src16An))) (setter (set (mem16 xmode (add Dsp-16-u16 Src16An)) newval)) ) + (define-derived-operand + (name (.sym src16-16-20-An-relative- xmode)) + (comment (.str "m16c dsp:20[An] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Src16An Dsp-16-u20)) + (syntax "${Dsp-16-u20}[$Src16An]") + (base-ifield f-8-4) + (encoding (+ (f-8-2 3) (f-10-1 0) Dsp-16-u20 Src16An)) + (ifield-assertion (andif (eq f-8-2 3) (eq f-10-1 0))) + (getter (mem20 xmode (add Dsp-16-u20 Src16An))) + (setter (set (mem20 xmode (add Dsp-16-u20 Src16An)) newval)) + ) ) ) @@ -3081,6 +3212,19 @@ (getter (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An))) (setter (set (mem16 xmode (add (.sym Dsp- offset -u16) Dst16An)) newval)) ) + (define-derived-operand + (name (.sym dst16- offset -20-An-relative- xmode)) + (comment (.str "m16c dsp:20[An] relative destination " xmode)) + (attrs (machine 16)) + (mode xmode) + (args (Dst16An (.sym Dsp- offset -u20))) + (syntax (.str "${Dsp-" offset "-u20}[$Dst16An]")) + (base-ifield f-12-4) + (encoding (+ (f-12-2 3) (f-14-1 0) (.sym Dsp- offset -u20) Dst16An)) + (ifield-assertion (andif (eq f-12-2 3) (eq f-14-1 0))) + (getter (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An))) + (setter (set (mem16 xmode (add (.sym Dsp- offset -u20) Dst16An)) newval)) + ) ) ) @@ -4651,6 +4795,25 @@ (.sym dst16-16-16-absolute- xmode) ) ) + (define-anyof-operand + (name (.sym dst16-16-16sa- xmode)) + (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-16-16-SB-relative- xmode) + (.sym dst16-16-16-absolute- xmode) + ) + ) + (define-anyof-operand + (name (.sym dst16-16-20ar- xmode)) + (comment (.str "m16c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 16)) + (mode xmode) + (choices + (.sym dst16-16-20-An-relative- xmode) + ) + ) ) ) @@ -5019,6 +5182,17 @@ (.sym dst32-16-16-absolute-Unprefixed- xmode) ) ) + (define-anyof-operand + (name (.sym dst32-16-16sa-Unprefixed- xmode)) + (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) + (attrs (machine 32)) + (mode xmode) + (choices + (.sym dst32-16-16-SB-relative-Unprefixed- xmode) + (.sym dst32-16-16-FB-relative-Unprefixed- xmode) + (.sym dst32-16-16-absolute-Unprefixed- xmode) + ) + ) (define-anyof-operand (name (.sym dst32-16-24-Unprefixed- xmode)) (comment (.str "m32c destination operand of size " xmode " with additional fields at offset 16")) @@ -5796,24 +5970,31 @@ ; Unary insn macros ;------------------------------------------------------------- -(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem) +(define-pmacro (unary-insn-defn-g mach group mode wstr op encoding sem opg) (dni (.sym op mach wstr - group) - (.str op wstr " dst" mach "-" group "-" mode) - ((machine mach)) - (.str op wstr " ${dst" mach "-" group "-" mode "}") + (.str op wstr opg " dst" mach "-" group "-" mode) + ((machine mach) RL_1ADDR) + (.str op wstr opg " ${dst" mach "-" group "-" mode "}") encoding (sem mode (.sym dst mach - group - mode)) ()) ) +(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem) + (unary-insn-defn-g mach group mode wstr op encoding sem "") +) + +(define-pmacro (unary16-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg) + (unary-insn-defn-g 16 16 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode)) + sem opg) +) (define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem) - (unary-insn-defn 16 16 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode)) - sem) + (unary-16-defn-g mode wstr wbit op opc1 opc2 opc3 sem "") ) -(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem) +(define-pmacro (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg) (begin ; Multi insns are tried for assembly in the reverse order in which they appear here, so ; define the absolute-indirect insns first in order to prevent them from being selected @@ -5821,26 +6002,39 @@ ; (unary-insn-defn 32 24-absolute-indirect mode wstr op ; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) (f-20-4 opc3)) ; sem) - (unary-insn-defn 32 16-Unprefixed mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3)) - sem) + (unary-insn-defn-g 32 16-Unprefixed mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3)) + sem opg) ; (unary-insn-defn 32 24-indirect mode wstr op ; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-indirect- mode) (f-18-2 opc2) (f-20-4 opc3)) ; sem) ) ) +(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem) + (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem "") +) -(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem) +(define-pmacro (unary-insn-mach-g mach op opc1 opc2 opc3 sem opg) (begin - (.apply (.sym unary mach -defn) (QI .b 0 op opc1 opc2 opc3 sem)) - (.apply (.sym unary mach -defn) (HI .w 1 op opc1 opc2 opc3 sem)) + (.apply (.sym unary mach -defn-g) (QI .b 0 op opc1 opc2 opc3 sem opg)) + (.apply (.sym unary mach -defn-g) (HI .w 1 op opc1 opc2 opc3 sem opg)) ) ) +(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem) + (unary-insn-mach-g mach op opc1 opc2 opc3 sem "") +) (define-pmacro (unary-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) (begin - (unary-insn-mach 16 op opc16-1 opc16-2 opc16-3 sem) - (unary-insn-mach 32 op opc32-1 opc32-2 opc32-3 sem) + (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "") + (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "") + ) +) + +(define-pmacro (unary-insn-g op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) + (begin + (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "$G") + (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "$G") ) ) @@ -5958,10 +6152,10 @@ ;------------------------------------------------------------- (define-pmacro (binary-arith16-Q-sp op opc1 opc2 opc3 sem) - (dni (.sym op 16 -Q-sp) - (.str op ":Q #imm4,sp") + (dni (.sym op 16 -wQ-sp) + (.str op ".w:q #imm4,sp") ((machine 16)) - (.str op "${size}$Q #${Imm-12-s4},sp") + (.str op ".w$Q #${Imm-12-s4},sp") (+ opc1 opc2 opc3 Imm-12-s4) (sem QI Imm-12-s4 sp) ()) @@ -5995,7 +6189,7 @@ (define-pmacro (binary-arith-imm-dst-defn mach src dstgroup dmode wstr op suffix encoding sem) (dni (.sym op mach wstr - imm-G - dstgroup) (.str op wstr " " mach "-imm-G-" dstgroup "-" dmode) - ((machine mach)) + ((machine mach) RL_1ADDR) (.str op wstr "$"suffix " #${" src "},${dst" mach "-" dstgroup "-" dmode "}") encoding (sem dmode src (.sym dst mach - dstgroup - dmode)) @@ -6105,7 +6299,7 @@ (define-pmacro (binary-arith-imm4-dst-defn mach src dstgroup mode wstr op encoding sem) (dni (.sym op mach wstr - imm4-Q - dstgroup) (.str op wstr " " mach "-imm4-Q-" dstgroup "-" mode) - ((machine mach)) + ((machine mach) RL_1ADDR) (.str op wstr "$Q #${" src "},${dst" mach "-" dstgroup "-" mode "}") encoding (sem mode src (.sym dst mach - dstgroup - mode)) @@ -6181,7 +6375,7 @@ (define-pmacro (binary-arith-src-dst-defn mach srcgroup dstgroup smode dmode wstr op suffix encoding sem) (dni (.sym op mach wstr - srcgroup - dstgroup) (.str op wstr " dst" mach "-" srcgroup "-" dstgroup "-" dmode) - ((machine mach)) + ((machine mach) RL_2ADDR) (.str op wstr "$" suffix " ${src" mach "-" srcgroup "-" smode "},${dst" mach "-" dstgroup "-" dmode "}") encoding (sem dmode (.sym src mach - srcgroup - smode) (.sym dst mach - dstgroup - dmode)) @@ -6495,7 +6689,7 @@ (define-pmacro (arith-jnz-imm4-dst-defn mach src dstgroup label mode wstr op encoding sem) (dni (.sym op mach wstr - imm4 - dstgroup) (.str op wstr " " mach "-imm4-" dstgroup "-" label "-" mode) - ((machine mach)) + (RL_JUMP RELAXABLE (machine mach)) (.str op wstr " #${" src "},${dst" mach "-" dstgroup "-" mode "},${" label "}") encoding (sem mode src (.sym dst mach - dstgroup - mode) label) @@ -6503,49 +6697,49 @@ ) ; m16c variants -(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op opc1 opc2 sem) +(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem) (begin - (arith-jnz-imm4-dst-defn 16 Imm-8-s4 basic Lab-16-8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-basic- mode) Lab-16-8) + (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) basic Lab-16-8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8) sem) - (arith-jnz-imm4-dst-defn 16 Imm-8-s4 16-16 Lab-32-8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-16-16- mode) Lab-16-8) + (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-32-8) sem) - (arith-jnz-imm4-dst-defn 16 Imm-8-s4 16-8 Lab-24-8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-16-8- mode) Lab-16-8) + (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-24-8) sem) ) ) ; m32c variants -(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op opc1 opc2 sem) +(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem) (begin - (arith-jnz-imm4-dst-defn 32 Imm-12-s4 basic-Unprefixed Lab-16-8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-16-8) + (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) basic-Unprefixed Lab-16-8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-16-8) sem) - (arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-24-Unprefixed Lab-40-8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-40-8) + (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-24-Unprefixed Lab-40-8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-40-8) sem) - (arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-16-Unprefixed Lab-32-8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-32-8) + (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-16-Unprefixed Lab-32-8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-32-8) sem) - (arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-8-Unprefixed Lab-24-8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-24-8) + (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-8-Unprefixed Lab-24-8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-24-8) sem) ) ) -(define-pmacro (arith-jnz-imm4-dst-mach mach op opc1 opc2 sem) +(define-pmacro (arith-jnz-imm4-dst-mach mach op i4n opc1 opc2 sem) (begin - (.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op opc1 opc2 sem)) - (.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op opc1 opc2 sem)) + (.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op i4n opc1 opc2 sem)) + (.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op i4n opc1 opc2 sem)) ) ) -(define-pmacro (arith-jnz-imm4-dst op opc16-1 opc16-2 opc32-1 opc32-2 sem) +(define-pmacro (arith-jnz-imm4-dst op i4n opc16-1 opc16-2 opc32-1 opc32-2 sem) (begin - (arith-jnz-imm4-dst-mach 16 op opc16-1 opc16-2 sem) - (arith-jnz-imm4-dst-mach 32 op opc32-1 opc32-2 sem) + (arith-jnz-imm4-dst-mach 16 op i4n opc16-1 opc16-2 sem) + (arith-jnz-imm4-dst-mach 32 op i4n opc32-1 opc32-2 sem) ) ) @@ -6556,7 +6750,7 @@ (dni (.sym op mach wstr -dspsp-dst- dstgroup) (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) ((machine mach)) - (.str op wstr " ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}") + (.str op wstr "$G ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}") encoding (sem mach mode dsp (.sym dst mach - dstgroup - mode)) ()) @@ -6565,7 +6759,7 @@ (dni (.sym op mach wstr -dst-dspsp- dstgroup) (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) ((machine mach)) - (.str op wstr " ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]") + (.str op wstr "$G ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]") encoding (sem mach mode (.sym dst mach - dstgroup - mode) dsp) ()) @@ -6574,28 +6768,28 @@ ; m16c variants (define-pmacro (mov16-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem) (begin - (mov-dspsp-dst-defn 16 basic Dsp-16-u8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u8) + (mov-dspsp-dst-defn 16 basic Dsp-16-s8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8) sem) - (mov-dspsp-dst-defn 16 16-16 Dsp-32-u8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u8) + (mov-dspsp-dst-defn 16 16-16 Dsp-32-s8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8) sem) - (mov-dspsp-dst-defn 16 16-8 Dsp-24-u8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u8) + (mov-dspsp-dst-defn 16 16-8 Dsp-24-s8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8) sem) ) ) (define-pmacro (mov16-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem) (begin - (mov-src-dspsp-defn 16 basic Dsp-16-u8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u8) + (mov-src-dspsp-defn 16 basic Dsp-16-s8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8) sem) - (mov-src-dspsp-defn 16 16-16 Dsp-32-u8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u8) + (mov-src-dspsp-defn 16 16-16 Dsp-32-s8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8) sem) - (mov-src-dspsp-defn 16 16-8 Dsp-24-u8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u8) + (mov-src-dspsp-defn 16 16-8 Dsp-24-s8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8) sem) ) ) @@ -6603,33 +6797,33 @@ ; m32c variants (define-pmacro (mov32-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem) (begin - (mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-u8) + (mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8) sem) - (mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-u8) + (mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8) sem) - (mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-u8) + (mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8) sem) - (mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-u8) + (mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8) sem) ) ) (define-pmacro (mov32-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem) (begin - (mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-u8) + (mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8) sem) - (mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-u8) + (mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8) sem) - (mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-u8) + (mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8) sem) - (mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-u8) + (mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8) sem) ) ) @@ -6663,59 +6857,91 @@ ;------------------------------------------------------------- ; lde dsp24,dst -- for m16c -; TODO abs20[a0], [a0a1] for dsp24 ;------------------------------------------------------------- -(define-pmacro (lde-defn mach dstgroup dsp mode wstr op encoding sem) - (dni (.sym op mach wstr -dst-dspsp- dstgroup) - (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) - ((machine mach)) - (.str op wstr " ${" dsp "},${dst" mach "-" dstgroup "-" mode "}") - encoding - (sem mode (.sym dst mach - dstgroup - mode) dsp) - ()) -) +(define-pmacro (lde-dst-dsp mode wstr wbit dstgroup srcdisp) + (begin + + (dni (.sym lde wstr - dstgroup -u20) + (.str "lde" wstr "-" dstgroup "-u20") + ((machine 16)) + (.str "lde" wstr " ${" srcdisp "},${dst16-" dstgroup "-" mode "}") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x8) + (.sym dst16- dstgroup - mode) srcdisp) + (nop) + ()) + + (dni (.sym lde wstr - dstgroup -u20a0) + (.str "lde" wstr "-" dstgroup "-u20a0") + ((machine 16)) + (.str "lde" wstr " ${" srcdisp "}[a0],${dst16-" dstgroup "-" mode "}") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x9) + (.sym dst16- dstgroup - mode) srcdisp) + (nop) + ()) + + (dni (.sym lde wstr - dstgroup -a1a0) + (.str "lde" wstr "-" dstgroup "-a1a0") + ((machine 16)) + (.str "lde" wstr " [a1a0],${dst16-" dstgroup "-" mode "}") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #xa) + (.sym dst16- dstgroup - mode)) + (nop) + ()) + ) + ) -(define-pmacro (lde-dst mode wstr wbit op opc1 opc2 opc3 sem) +(define-pmacro (lde-dst mode wstr wbit) (begin - (lde-defn 16 basic Dsp-16-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u20) - sem) - (lde-defn 16 16-16 Dsp-32-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u20) - sem) - (lde-defn 16 16-8 Dsp-24-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u20) - sem) + ; like: QI .b 0 + (lde-dst-dsp mode wstr wbit basic Dsp-16-u20) + (lde-dst-dsp mode wstr wbit 16-8 Dsp-24-u20) + (lde-dst-dsp mode wstr wbit 16-16 Dsp-32-u20) ) ) ;------------------------------------------------------------- -; ste src,dsp24 -- for m16c -; TODO abs20[a0], [a0a1] for dsp24 +; ste dst,dsp24 -- for m16c ;------------------------------------------------------------- -(define-pmacro (ste-defn mach dstgroup dsp mode wstr op encoding sem) - (dni (.sym op mach wstr -dst-dspsp- dstgroup) - (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) - ((machine mach)) - (.str op wstr " ${dst" mach "-" dstgroup "-" mode "},${" dsp "}") - encoding - (sem mode (.sym dst mach - dstgroup - mode) dsp) - ()) -) +(define-pmacro (ste-dst-dsp mode wstr wbit dstgroup srcdisp) + (begin + + (dni (.sym ste wstr - dstgroup -u20) + (.str "ste" wstr "-" dstgroup "-u20") + ((machine 16)) + (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x0) + (.sym dst16- dstgroup - mode) srcdisp) + (nop) + ()) + + (dni (.sym ste wstr - dstgroup -u20a0) + (.str "ste" wstr "-" dstgroup "-u20a0") + ((machine 16)) + (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}[a0]") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x1) + (.sym dst16- dstgroup - mode) srcdisp) + (nop) + ()) -(define-pmacro (ste-dst mode wstr wbit op opc1 opc2 opc3 sem) + (dni (.sym ste wstr - dstgroup -a1a0) + (.str "ste" wstr "-" dstgroup "-a1a0") + ((machine 16)) + (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},[a1a0]") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x2) + (.sym dst16- dstgroup - mode)) + (nop) + ()) + ) + ) + +(define-pmacro (ste-dst mode wstr wbit) (begin - (ste-defn 16 basic Dsp-16-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u20) - sem) - (ste-defn 16 16-16 Dsp-32-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u20) - sem) - (ste-defn 16 16-8 Dsp-24-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u20) - sem) + ; like: QI .b 0 + (ste-dst-dsp mode wstr wbit basic Dsp-16-u20) + (ste-dst-dsp mode wstr wbit 16-8 Dsp-24-u20) + (ste-dst-dsp mode wstr wbit 16-16 Dsp-32-u20) ) ) @@ -7052,6 +7278,9 @@ (binary-arith16-b-S-imm8-dst3 add ".b" (f-0-4 8) (f-4-1 0) add-sem) ; add.BW:Q #imm4,sp (m16 #7) (binary-arith16-Q-sp add (f-0-4 7) (f-4-4 #xD) (f-8-4 #xB) add-sem) +(dnmi add16-bQ-sp "add16-bQ-sp" () + "add.b:q #${Imm-12-s4},sp" + (emit add16-wQ-sp Imm-12-s4)) ; add.BW:G #imm,sp (m16 #6) (binary-arith16-G-sp add (f-0-4 7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #xB) add-sem) ; add.BW:G src,dst (m16 #4 m32 #6) @@ -7116,7 +7345,7 @@ (dni (.sym op 16.b-imm8) (.str op ".b #imm8") ((machine 16)) - (.str op ".b #${Imm-16-QI}") + (.str op ".b #${Imm-16-QI},r0l") (+ (f-0-4 #x7) (f-4-4 #xC) (f-8-4 #xE) (f-12-4 opc1) Imm-16-QI) ((.sym op -sem) QI Imm-16-QI R0l) ()) @@ -7124,7 +7353,7 @@ (dni (.sym op 16.w-imm16) (.str op ".b #imm16") ((machine 16)) - (.str op ".w #${Imm-16-HI}") + (.str op ".w #${Imm-16-HI},r0") (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xE) (f-12-4 opc1) Imm-16-HI) ((.sym op -sem) HI Imm-16-HI R0) ()) @@ -7207,7 +7436,7 @@ ) ; adjnz.size #imm4,dst,label -(arith-jnz-imm4-dst adjnz (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem) +(arith-jnz-imm4-dst adjnz s4 (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem) ;------------------------------------------------------------- ; and - binary and @@ -7435,7 +7664,16 @@ (set zbit (inv dst)) (set cbit dst) ) -(bitdst-insn btst (f-0-4 7) (f-4-4 #xE) (f-8-4 #xB) (f-0-2 1) (f-2-2 1) (f-4-1 1) #xD #x0 #x0 btst-sem) +(bitdst16-defn btst (f-0-4 7) (f-4-4 #xE) (f-8-4 #xB) (f-0-2 1) (f-2-2 1) (f-4-1 1) btst-sem) + +(bit-insn-defn 32 btst G bit32-16-Unprefixed + (+ (f-0-4 #xD) bit32-16-Unprefixed (f-7-1 #x0) (f-10-3 #x0)) + btst-sem) + +(dni btst.s "btst:s" ((machine 32)) + "btst:s ${Bit3-S},${Dsp-8-u16}" + (+ (f-0-2 #x0) (f-4-3 #x5) Bit3-S Dsp-8-u16) + () ()) ;------------------------------------------------------------- ; btstc @@ -7864,6 +8102,9 @@ (define-pmacro (indexls-sem mode d) (set SrcIndex (sll d (const 2))) (set DstIndex (const 0))) +; Note that "wbit" not where the size bit goes here, hence, it's +; always 0 in these calls but op2 differs instead. + ; indexb src (index byte) (unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem) (unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem) @@ -7940,7 +8181,7 @@ (dni jcnd16-5 "jCnd label" - ((machine 16)) + (RL_JUMP RELAXABLE (machine 16)) "j$cond16j5 ${Lab-8-8}" (+ (f-0-4 #x6) (f-4-1 1) cond16j5 Lab-8-8) (jcnd16-sem cond16j5 Lab-8-8) @@ -7949,7 +8190,7 @@ (dni jcnd16 "jCnd label" - ((machine 16)) + (RL_JUMP RELAXABLE (machine 16)) "j$cond16j ${Lab-16-8}" (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xC) cond16j Lab-16-8) (jcnd16-sem cond16j Lab-16-8) @@ -7958,7 +8199,7 @@ (dni jcnd32 "jCnd label" - ((machine 32)) + (RL_JUMP RELAXABLE (machine 32)) "j$cond32j ${Lab-8-8}" (+ (f-0-1 1) (f-4-3 5) cond32j Lab-8-8) (jcnd32-sem cond32j Lab-8-8) @@ -7970,25 +8211,25 @@ ;------------------------------------------------------------- ; jmp.s label3 (m16 #1) -(dni jmp16.s "jmp.s Lab-5-3" ((machine 16)) +(dni jmp16.s "jmp.s Lab-5-3" (RL_JUMP RELAXABLE (machine 16)) ("jmp.s ${Lab-5-3}") (+ (f-0-4 6) (f-4-1 0) Lab-5-3) (sequence () (set pc Lab-5-3)) ()) ; jmp.b label8 (m16 #2) -(dni jmp16.b "jmp.b Lab-8-8" ((machine 16)) +(dni jmp16.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 16)) ("jmp.b ${Lab-8-8}") (+ (f-0-4 #xF) (f-4-4 #xE) Lab-8-8) (sequence () (set pc Lab-8-8)) ()) ; jmp.w label16 (m16 #3) -(dni jmp16.w "jmp.w Lab-8-16" ((machine 16)) +(dni jmp16.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16)) ("jmp.w ${Lab-8-16}") (+ (f-0-4 #xF) (f-4-4 4) Lab-8-16) (sequence () (set pc Lab-8-16)) ()) ; jmp.a label24 (m16 #4) -(dni jmp16.a "jmp.a Lab-8-24" ((machine 16)) +(dni jmp16.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16)) ("jmp.a ${Lab-8-24}") (+ (f-0-4 #xF) (f-4-4 #xC) Lab-8-24) (sequence () (set pc Lab-8-24)) @@ -8015,32 +8256,32 @@ ; jmp.s label3 (m32 #1) (dni jmp32.s "jmp.s label" - ((machine 32)) + (RL_JUMP RELAXABLE (machine 32)) "jmp.s ${Lab32-jmp-s}" (+ (f-0-2 1) (f-4-3 5) Lab32-jmp-s) (set pc Lab32-jmp-s) () ) ; jmp.b label8 (m32 #2) -(dni jmp32.b "jmp.b Lab-8-8" ((machine 32)) +(dni jmp32.b "jmp.b Lab-8-8" (RL_JUMP RELAXABLE (machine 32)) ("jmp.b ${Lab-8-8}") (+ (f-0-4 #xB) (f-4-4 #xB) Lab-8-8) (set pc Lab-8-8) ()) ; jmp.w label16 (m32 #3) -(dni jmp32.w "jmp.w Lab-8-16" ((machine 32)) +(dni jmp32.w "jmp.w Lab-8-16" (RL_JUMP RELAXABLE (machine 32)) ("jmp.w ${Lab-8-16}") (+ (f-0-4 #xC) (f-4-4 #xE) Lab-8-16) (set pc Lab-8-16) ()) ; jmp.a label24 (m32 #4) -(dni jmp32.a "jmp.a Lab-8-24" ((machine 32)) +(dni jmp32.a "jmp.a Lab-8-24" (RL_JUMP RELAXABLE (machine 32)) ("jmp.a ${Lab-8-24}") (+ (f-0-4 #xC) (f-4-4 #xC) Lab-8-24) (set pc Lab-8-24) ()) ; jmp.s imm8 (m32 #1) -(dni jmps32 "jmps Imm-8-QI" ((machine 32)) +(dni jmps32 "jmps Imm-8-QI" (RL_JUMP (machine 32)) ("jmps #${Imm-8-QI}") (+ (f-0-4 #xD) (f-4-4 #xC) Imm-8-QI) (set pc Imm-8-QI) @@ -8072,13 +8313,13 @@ ) ; jsr.w label16 (m16 #1) -(dni jsr16.w "jsr.w Lab-8-16" ((machine 16)) +(dni jsr16.w "jsr.w Lab-8-16" (RL_JUMP RELAXABLE (machine 16)) ("jsr.w ${Lab-8-16}") (+ (f-0-4 #xF) (f-4-4 5) Lab-8-16) (jsr16-sem 3 Lab-8-16) ()) ; jsr.a label24 (m16 #2) -(dni jsr16.a "jsr.a Lab-8-24" ((machine 16)) +(dni jsr16.a "jsr.a Lab-8-24" (RL_JUMP RELAXABLE (machine 16)) ("jsr.a ${Lab-8-24}") (+ (f-0-4 #xF) (f-4-4 #xD) Lab-8-24) (jsr16-sem 4 Lab-8-24) @@ -8088,14 +8329,14 @@ (begin (dni (.sym jsri16 mode - op16) (.str "jsri." mode " " op16) - ((machine 16)) + (RL_1ADDR (machine 16)) (.str "jsri." mode " ${" op16 "}") (+ op16-1 op16-2 op16-3 op16) (op16-sem len op16) ()) (dni (.sym jsri32 mode - op32) (.str "jsri." mode " " op32) - ((machine 32)) + (RL_1ADDR (machine 32)) (.str "jsri." mode " ${" op32 "}") (+ op32-1 op32-2 op32-3 op32-4 op32) (op32-sem len op32) @@ -8103,38 +8344,38 @@ ) ) ; jsri.w dst (m16 #1 m32 #1)) -(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem - dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2) +(jsri-defn w dst16-16-20ar-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem + dst32-16-24-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) +(jsri-defn w dst16-16-16sa-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem + dst32-16-16sa-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) (jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3) -(jsri-defn w dst16-16-16-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem - dst32-16-16-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) -(dni jsri32.w "jsr.w dst32-16-24-Unprefixed-HI" ((machine 32)) - ("jsri.w ${dst32-16-24-Unprefixed-HI}") - (+ (f-0-4 #xC) (f-7-1 1) dst32-16-24-Unprefixed-HI (f-10-2 #x1) (f-12-4 #xF)) - (jsr32-sem 6 dst32-16-24-Unprefixed-HI) - ()) +(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem + dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2) ; jsri.a (m16 #2 m32 #2) -(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem - dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2) +(jsri-defn a dst16-16-20ar-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem + dst32-16-24-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) (jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3) -(jsri-defn a dst16-16-16-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem - dst32-16-16-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) -(dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" ((machine 32)) - ("jsri.w ${dst32-16-24-Unprefixed-SI}") +(jsri-defn a dst16-16-16sa-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem + dst32-16-16sa-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) +(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem + dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2) + +(dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" (RL_1ADDR (machine 32)) + ("jsri.a ${dst32-16-24-Unprefixed-SI}") (+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1)) (jsr32-sem 6 dst32-16-24-Unprefixed-SI) ()) ; jsr.w label16 (m32 #1) -(dni jsr32.w "jsr.w label" ((machine 32)) +(dni jsr32.w "jsr.w label" (RL_JUMP RELAXABLE (machine 32)) ("jsr.w ${Lab-8-16}") (+ (f-0-4 #xC) (f-4-4 #xF) Lab-8-16) (jsr32-sem 3 Lab-8-16) ()) ; jsr.a label16 (m32 #2) -(dni jsr32.a "jsr.a label" ((machine 32)) +(dni jsr32.a "jsr.a label" (RL_JUMP (machine 32)) ("jsr.a ${Lab-8-24}") (+ (f-0-4 #xC) (f-4-4 #xD) Lab-8-24) (jsr32-sem 4 Lab-8-24) @@ -8411,21 +8652,11 @@ ; ste - store to extra far data area (m16) ;------------------------------------------------------------- -; A special variant of mem16 for lde and ste -(define-pmacro (extra-mem16 mode address) - (mem mode (and #xfffff address))) - -(define-pmacro (lde-sem mode src1 dst) - (set mode src1 (extra-mem16 mode dst)) -) -(lde-dst QI .b 0 lde (f-0-4 #x7) (f-4-3 2) (f-8-4 #x8) lde-sem) -(lde-dst HI .w 1 lde (f-0-4 #x7) (f-4-3 2) (f-8-4 #x8) lde-sem) +(lde-dst QI .b 0) +(lde-dst HI .w 1) -(define-pmacro (ste-sem mode src1 dst) - (set (extra-mem16 mode dst) src1) -) -(ste-dst QI .b 0 ste (f-0-4 #x7) (f-4-3 2) (f-8-4 #x0) ste-sem) -(ste-dst HI .w 1 ste (f-0-4 #x7) (f-4-3 2) (f-8-4 #x0) ste-sem) +(ste-dst QI .b 0) +(ste-dst HI .w 1) ;------------------------------------------------------------- ; ldipl - load interrupt permission level @@ -8433,6 +8664,7 @@ ; ??? semantics ; ldintb <==> ldc #imm,intbh ; ldc #imm,intbl + (dni ldipl16.imm "ldipl #imm" ((machine 16)) ("ldipl #${Imm-13-u3}") (+ (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #xA) (f-12-1 0) Imm-13-u3) @@ -8514,11 +8746,6 @@ (binary-arith-imm-dst mov G (f-0-4 7) (f-4-3 2) (f-8-4 #xC) #x9 #x2 #xF mov-sem) ; mov.L:G #imm32,dst (m32 #2) (binary-arith32-imm-dst-defn SI SI .l 0 mov G #xB #x3 #x1 mov-sem) -; mov.size:Q #imm4,dst (m16 #2 m32 #3) -(binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem) -(binary-arith16-imm4-dst-defn QI .w 0 1 mov (f-0-4 #xD) (f-4-3 4) mov-sem) -(binary-arith32-imm4-dst-defn QI .b 1 0 mov #x7 #x2 mov-sem) -(binary-arith32-imm4-dst-defn HI .w 1 1 mov #x7 #x2 mov-sem) ; mov.BW:S #imm,dst2 (m32 #4) (binary-arith32-s-imm-dst QI .b 0 mov #x0 #x2 mov-sem) (binary-arith32-s-imm-dst HI .w 1 mov #x0 #x2 mov-sem) @@ -8541,8 +8768,14 @@ ) (mov32-wl-s-defn HI w #x9 Imm-8-HI a0 #xC) (mov32-wl-s-defn HI w #x9 Imm-8-HI a1 #xD) -(mov32-wl-s-defn SI l #xB Dsp-16-u24 a0 #xC) -(mov32-wl-s-defn SI l #xB Dsp-16-u24 a1 #xD) +(mov32-wl-s-defn SI l #xB Dsp-8-s24 a0 #xC) +(mov32-wl-s-defn SI l #xB Dsp-8-s24 a1 #xD) + +; mov.size:Q #imm4,dst (m16 #2 m32 #3) +(binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem) +(binary-arith16-imm4-dst-defn HI .w 0 1 mov (f-0-4 #xD) (f-4-3 4) mov-sem) +(binary-arith32-imm4-dst-defn QI .b 1 0 mov #x7 #x2 mov-sem) +(binary-arith32-imm4-dst-defn HI .w 1 1 mov #x7 #x2 mov-sem) ; mov.BW:Z #0,dst (m16 #5 m32 #6) (dni mov16.b-Z-imm8-dst3 @@ -8609,7 +8842,7 @@ (mov32-src-r b 0 QI dst32-2-S-8 r0l 0 4) (mov32-src-r w 1 HI dst32-2-S-8 r0 0 4) (mov32-src-r b 0 QI dst32-2-S-basic r1l 1 7) -(mov32-src-r w 1 HI dst32-2-S-basic r1l 1 7) +(mov32-src-r w 1 HI dst32-2-S-basic r1 1 7) (mov32-src-r b 0 QI dst32-2-S-16 r1l 1 7) (mov32-src-r w 1 HI dst32-2-S-16 r1 1 7) (mov32-src-r b 0 QI dst32-2-S-8 r1l 1 7) @@ -8787,6 +9020,17 @@ ; mul.BW src,dst (binary-arith-src-dst mul G (f-0-4 #x7) (f-4-3 4) #x1 #xC mul-sem) +(dni mul_l "mul.l src,r2r0" ((machine 32)) + ("mul.l ${dst32-24-Prefixed-SI},r2r0") + (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x1) (f-20-4 #xf) + dst32-24-Prefixed-SI) + () ()) + +(dni mulu_l "mulu.l src,r2r0" ((machine 32)) + ("mulu.l ${dst32-24-Prefixed-SI},r2r0") + (+ (f-0-4 #x0) (f-4-4 #x1) (f-8-4 #x8) (f-15-1 #x1) (f-18-2 #x0) (f-20-4 #xf) + dst32-24-Prefixed-SI) + () ()) ;------------------------------------------------------------- ; mulex - multiple extend sign (m32) ;------------------------------------------------------------- @@ -8850,7 +9094,15 @@ ) ; not.BW:G -(unary-insn not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem) +(unary-insn-g not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem) + +(dni not16.b.s + "not.b:s Dst16-3-S-8" + ((machine 16)) + "not.b:s ${Dst16-3-S-8}" + (+ (f-0-4 #xb) (f-4-1 #x1) Dst16-3-S-8) + (not-sem QI Dst16-3-S-8) + ()) ;------------------------------------------------------------- ; nop @@ -8891,6 +9143,8 @@ (binary-arith32-s-imm-dst HI .w 1 or #x1 #x2 or-sem) ; or.BW src,dst (m16 #3 m32 #3) (binary-arith-src-dst or G (f-0-4 #x9) (f-4-3 4) #x1 #x5 or-sem) +; or.b:S src,r0[lh] (m16) +(binary-arith16-b-S-src2 or (f-0-4 1) (f-4-1 1) or-sem) ;------------------------------------------------------------- ; pop - restore register/memory @@ -8916,7 +9170,7 @@ (define-pmacro (pop-sem32 mode dest) (pop-sem-mach 32 mode dest)) ; pop.BW:G (m16 #1) -(unary-insn-mach 16 pop (f-0-4 7) (f-4-3 2) (f-8-4 #xD) pop-sem16) +(unary-insn-mach-g 16 pop (f-0-4 7) (f-4-3 2) (f-8-4 #xD) pop-sem16 $G) ; pop.BW:G (m32 #1) (unary-insn-mach 32 pop #xB #x2 #xF pop-sem32) @@ -9226,8 +9480,8 @@ (push-sem16 HI Imm-16-HI) ()) -(dni push32.b.imm "push.w #Imm-8-QI" ((machine 32)) - ("push.b #Imm-8-QI") +(dni push32.b.imm "push.b #Imm-8-QI" ((machine 32)) + ("push.b #${Imm-8-QI}") (+ (f-0-4 #xA) (f-4-4 #xE) Imm-8-QI) (push-sem32 QI Imm-8-QI) ()) @@ -9239,7 +9493,7 @@ ()) ; push.BW:G src (m16 #2) -(unary-insn-mach 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16) +(unary-insn-mach-g 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16 $G) ; push.BW:G src (m32 #2) (unary-insn-mach 32 push #xC #x0 #xE push-sem32) @@ -9441,9 +9695,9 @@ ; rot.BW src,dst (dni rot16.b-dst "rot r1h,dest" ((machine 16)) - ("rot.b r1h,${dst16-16-HI}") - (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-HI) - (rot-2-sem QI dst16-16-HI) + ("rot.b r1h,${dst16-16-QI}") + (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-QI) + (rot-2-sem QI dst16-16-QI) ()) (dni rot16.w-dst "rot r1h,dest" ((machine 16)) ("rot.w r1h,${dst16-16-HI}") @@ -9452,14 +9706,14 @@ ()) (dni rot32.b-dst "rot r1h,dest" ((machine 32)) - ("rot.b r1h,${dst32-16-Unprefixed-SI}") - (+ (f-0-4 #xA) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 3) (f-12-4 #xF)) - (rot-2-sem QI dst32-16-Unprefixed-SI) + ("rot.b r1h,${dst32-16-Unprefixed-QI}") + (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xF)) + (rot-2-sem QI dst32-16-Unprefixed-QI) ()) (dni rot32.w-dst "rot r1h,dest" ((machine 32)) - ("rot.w r1h,${dst32-16-Unprefixed-SI}") - (+ (f-0-4 #xA) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 3) (f-12-4 #xF)) - (rot-2-sem HI dst32-16-Unprefixed-SI) + ("rot.w r1h,${dst32-16-Unprefixed-HI}") + (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xF)) + (rot-2-sem HI dst32-16-Unprefixed-HI) ()) ;------------------------------------------------------------- @@ -9535,7 +9789,7 @@ ) ; sbjnz.size #imm4,dst,label -(arith-jnz-imm4-dst sbjnz (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem) +(arith-jnz-imm4-dst sbjnz s4n (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem) ;------------------------------------------------------------- ; sccnd - store condition on condition (m32) @@ -10065,18 +10319,18 @@ (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0l)) ()) (dni stzx16-imm8-imm8-dsp8sb "stzx #Imm8,#Imm8,dsp8[sb]" ((machine 16)) - ("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[sb]") + ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb]") (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI Dsp-16-u8 Imm-24-QI) (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-sb) Dsp-24-u8))) ()) (dni stzx16-imm8-imm8-dsp8fb "stzx #Imm8,#Imm8,dsp8[fb]" ((machine 16)) - ("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[fb]") - (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u8 Imm-24-QI) - (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-fb) Dsp-24-u8))) + ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb]") + (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-s8 Imm-24-QI) + (stzx-sem QI Imm-8-QI Imm-24-QI (mem16 QI (add (reg h-fb) Dsp-16-s8))) ()) (dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16)) - ("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u16") - (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u16 Imm-32-QI) + ("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}") + (+ (f-0-4 #xD) (f-4-4 #xF) Imm-8-QI Dsp-16-u16 Imm-32-QI) (stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16)) ()) ; stzx.BW #imm,dst (m32) @@ -10109,12 +10363,12 @@ ) ; tst.BW #imm,dst (m16 #1 m32 #1) -(binary-arith-imm-dst tst X (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem) +(binary-arith-imm-dst tst G (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem) ; tst.BW src,dst (m16 #2 m32 #3) (binary-arith16-src-dst-defn QI QI .b 0 tst X (f-0-4 #x8) (f-4-3 0) tst-sem) (binary-arith16-src-dst-defn HI HI .w 1 tst X (f-0-4 #x8) (f-4-3 0) tst-sem) -(binary-arith32-src-dst-Prefixed QI QI .b 0 tst X #x1 #x9 tst-sem) -(binary-arith32-src-dst-Prefixed HI HI .w 1 tst X #x1 #x9 tst-sem) +(binary-arith32-src-dst-Prefixed QI QI .b 0 tst G #x1 #x9 tst-sem) +(binary-arith32-src-dst-Prefixed HI HI .w 1 tst G #x1 #x9 tst-sem) ; tst.BW:S #imm,dst2 (m32 #2) (binary-arith32-s-imm-dst QI .b 0 tst #x0 #x6 tst-sem) (binary-arith32-s-imm-dst HI .w 1 tst #x0 #x6 tst-sem) @@ -10175,7 +10429,7 @@ (xchg16-defn QI b 0 1 r0h) (xchg16-defn QI b 0 2 r1l) (xchg16-defn QI b 0 3 r1h) -(xchg16-defn QI w 1 0 r0) +(xchg16-defn HI w 1 0 r0) (xchg16-defn HI w 1 1 r1) (xchg16-defn HI w 1 2 r2) (xchg16-defn HI w 1 3 r3)