X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2FChangeLog;h=139c5cfd53859c62174f5a02679b4885a01b8108;hb=6648b7cff9e4fa76e9bff0f57aa5fd81cb19f0f3;hp=4680e77e9bea046f64f6878728d1230307f60a02;hpb=5002adadc5daf053675d9a08988a1725a9cd7a2b;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/ChangeLog b/gas/ChangeLog index 4680e77e9b..139c5cfd53 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,6 +1,318 @@ -2006-05-22 Nick Clifton +2006-06-07 Joseph S. Myers + + * po/Make-in (pdf, ps): New dummy targets. + +2006-06-07 Julian Brown + + * config/tc-arm.c (stdarg.h): include. + (arm_it): Add uncond_value field. Add isvec and issingle to operand + array. + (arm_reg_type): Add REG_TYPE_VFSD (single or double VFP reg) and + REG_TYPE_NSDQ (single, double or quad vector reg). + (reg_expected_msgs): Update. + (BAD_FPU): Add macro for unsupported FPU instruction error. + (parse_neon_type): Support 'd' as an alias for .f64. + (parse_typed_reg_or_scalar): Support REG_TYPE_VFSD, REG_TYPE_NSDQ + sets of registers. + (parse_vfp_reg_list): Don't update first arg on error. + (parse_neon_mov): Support extra syntax for VFP moves. + (operand_parse_code): Add OP_RVSD, OP_RNSDQ, OP_VRSDLST, OP_RVSD_IO, + OP_RNSDQ_RNSC, OP_RVC_PSR, OP_APSR_RR, OP_oRNSDQ. + (parse_operands): Support isvec, issingle operands fields, new parse + codes above. + (do_vfp_nsyn_mrs, do_vfp_nsyn_msr): New functions. Support VFP mrs, + msr variants. + (do_mrs, do_msr, do_t_mrs, do_t_msr): Add support for above. + (NEON_ENC_TAB): Add vnmul, vnmla, vnmls, vcmp, vcmpz, vcmpe, vcmpez. + (NEON_ENC_SINGLE, NEON_ENC_DOUBLE): Define macros. + (NEON_SHAPE_DEF): New macro. Define table of possible instruction + shapes. + (neon_shape): Redefine in terms of above. + (neon_shape_class): New enumeration, table of shape classes. + (neon_shape_el): New enumeration. One element of a shape. + (neon_shape_el_size): Register widths of above, where appropriate. + (neon_shape_info): New struct. Info for shape table. + (neon_shape_tab): New array. + (neon_type_mask): Add N_F64, N_VFP. Update N_MAX_NONSPECIAL. + (neon_check_shape): Rewrite as... + (neon_select_shape): New function to classify instruction shapes, + driven by new table neon_shape_tab array. + (neon_quad): New function. Return 1 if shape should set Q flag in + instructions (or equivalent), 0 otherwise. + (type_chk_of_el_type): Support F64. + (el_type_of_type_chk): Likewise. + (neon_check_type): Add support for VFP type checking (VFP data + elements fill their containing registers). + (do_vfp_cond_or_thumb): Fill in condition field in ARM mode, or 0xE + in thumb mode for VFP instructions. + (do_vfp_nsyn_opcode): New function. Look up the opcode in argument, + and encode the current instruction as if it were that opcode. + (try_vfp_nsyn): New. If this looks like a VFP instruction with ARGS + arguments, call function in PFN. + (do_vfp_nsyn_add_sub, do_vfp_nsyn_mla_mls, do_vfp_nsyn_mul) + (do_vfp_nsyn_abs_neg, do_vfp_nsyn_ldm_stm, do_vfp_nsyn_ldr_str) + (do_vfp_nsyn_sqrt, do_vfp_nsyn_div, do_vfp_nsyn_nmul) + (do_vfp_nsyn_cmp, nsyn_insert_sp, do_vfp_nsyn_push) + (do_vfp_nsyn_pop, do_vfp_nsyn_cvt, do_vfp_nsyn_cvtz): New functions. + Redirect Neon-syntax VFP instructions to VFP instruction handlers. + (do_neon_dyadic_i_su, do_neon_dyadic_i64_su, do_neon_shl_imm) + (do_neon_qshl_imm, do_neon_logic, do_neon_bitfield) + (neon_dyadic_misc, neon_compare, do_neon_tst, do_neon_qdmulh) + (do_neon_fcmp_absolute, do_neon_step, do_neon_sli, do_neon_sri) + (do_neon_qshlu_imm, neon_move_immediate, do_neon_mvn, do_neon_ext) + (do_neon_rev, do_neon_dup, do_neon_rshift_round_imm, do_neon_trn) + (do_neon_zip_uzp, do_neon_sat_abs_neg, do_neon_pair_long) + (do_neon_recip_est, do_neon_cls, do_neon_clz, do_neon_cnt) + (do_neon_swp): Use neon_select_shape not neon_check_shape. Use + neon_quad. + (vfp_or_neon_is_neon): New function. Call if a mnemonic shared + between VFP and Neon turns out to belong to Neon. Perform + architecture check and fill in condition field if appropriate. + (do_neon_addsub_if_i, do_neon_mac_maybe_scalar, do_neon_abs_neg) + (do_neon_cvt): Add support for VFP variants of instructions. + (neon_cvt_flavour): Extend to cover VFP conversions. + (do_neon_mov): Rewrite to use neon_select_shape. Add support for VFP + vmov variants. + (do_neon_ldr_str): Handle single-precision VFP load/store. + (do_neon_ld_st_interleave, do_neon_ld_st_lane, do_neon_ld_dup): Use + NS_NULL not NS_IGNORE. + (opcode_tag): Add OT_csuffixF for operands which either take a + conditional suffix, or have 0xF in the condition field. + (md_assemble): Add support for OT_csuffixF. + (NCE): Replace macro with... + (NCE_tag, NCE, NCEF): New macros. + (nCE): Replace macro with... + (nCE_tag, nCE, nCEF): New macros. + (insns): Add support for VFP insns or VFP versions of insns msr, + mrs, vsqrt, vdiv, vnmul, vnmla, vnmls, vcmp, vcmpe, vpush, vpop, + vcvtz, vmul, vmla, vmls, vadd, vsub, vabs, vneg, vldm, vldmia, + vldbdb, vstm, vstmia, vstmdb, vldr, vstr, vcvt, vmov. Group shared + VFP/Neon insns together. + +2006-06-07 Alan Modra + Ladislav Michl + + * app.c: Don't include headers already included by as.h. + * as.c: Likewise. + * atof-generic.c: Likewise. + * cgen.c: Likewise. + * dwarf2dbg.c: Likewise. + * expr.c: Likewise. + * input-file.c: Likewise. + * input-scrub.c: Likewise. + * macro.c: Likewise. + * output-file.c: Likewise. + * read.c: Likewise. + * sb.c: Likewise. + * config/bfin-lex.l: Likewise. + * config/obj-coff.h: Likewise. + * config/obj-elf.h: Likewise. + * config/obj-som.h: Likewise. + * config/tc-arc.c: Likewise. + * config/tc-arm.c: Likewise. + * config/tc-avr.c: Likewise. + * config/tc-bfin.c: Likewise. + * config/tc-cris.c: Likewise. + * config/tc-d10v.c: Likewise. + * config/tc-d30v.c: Likewise. + * config/tc-dlx.h: Likewise. + * config/tc-fr30.c: Likewise. + * config/tc-frv.c: Likewise. + * config/tc-h8300.c: Likewise. + * config/tc-hppa.c: Likewise. + * config/tc-i370.c: Likewise. + * config/tc-i860.c: Likewise. + * config/tc-i960.c: Likewise. + * config/tc-ip2k.c: Likewise. + * config/tc-iq2000.c: Likewise. + * config/tc-m32c.c: Likewise. + * config/tc-m32r.c: Likewise. + * config/tc-maxq.c: Likewise. + * config/tc-mcore.c: Likewise. + * config/tc-mips.c: Likewise. + * config/tc-mmix.c: Likewise. + * config/tc-mn10200.c: Likewise. + * config/tc-mn10300.c: Likewise. + * config/tc-msp430.c: Likewise. + * config/tc-mt.c: Likewise. + * config/tc-ns32k.c: Likewise. + * config/tc-openrisc.c: Likewise. + * config/tc-ppc.c: Likewise. + * config/tc-s390.c: Likewise. + * config/tc-sh.c: Likewise. + * config/tc-sh64.c: Likewise. + * config/tc-sparc.c: Likewise. + * config/tc-tic30.c: Likewise. + * config/tc-tic4x.c: Likewise. + * config/tc-tic54x.c: Likewise. + * config/tc-v850.c: Likewise. + * config/tc-vax.c: Likewise. + * config/tc-xc16x.c: Likewise. + * config/tc-xstormy16.c: Likewise. + * config/tc-xtensa.c: Likewise. + * config/tc-z80.c: Likewise. + * config/tc-z8k.c: Likewise. + * macro.h: Don't include sb.h or ansidecl.h. + * sb.h: Don't include stdio.h or ansidecl.h. + * cond.c: Include sb.h. + * itbl-lex.l: Include as.h instead of other system headers. + * itbl-parse.y: Likewise. + * itbl-ops.c: Similarly. + * itbl-ops.h: Don't include as.h or ansidecl.h. + * config/bfin-defs.h: Don't include bfd.h or as.h. + * config/bfin-parse.y: Include as.h instead of other system headers. + +2006-06-06 Ben Elliston + Anton Blanchard + + * config/tc-ppc.c (parse_cpu): Handle "-mpower6". + (md_show_usage): Document it. + (ppc_setup_opcodes): Test power6 opcode flag bits. + * doc/c-ppc.texi (PowerPC-Opts): Document "-mpower6". + +2006-06-06 Thiemo Seufer + Chao-ying Fu + + * config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro. + (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete. + (macro_build): Update comment. + (mips_ip): Allow DSP64 instructions for MIPS64R2. + (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and + CPU_HAS_MDMX. + (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and + MIPS_CPU_ASE_MDMX flags for sb1. + +2006-06-05 Thiemo Seufer + + * config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew + appropriate. + (mips16_macro_build): Use MIPS16_INSERT_OPERAND where appropriate. + (mips_ip): Make overflowed/underflowed constant arguments in DSP + and MT instructions a fatal error. Use INSERT_OPERAND where + appropriate. Improve warnings for break and wait code overflows. + Use symbolic constant of OP_MASK_COPZ. + (mips16_ip): Use MIPS16_INSERT_OPERAND where appropriate. + +2006-06-05 Daniel Jacobowitz + + * po/Make-in (top_builddir): Define. + +2006-06-02 Joseph S. Myers + + * doc/Makefile.am (TEXI2DVI): Define. + * doc/Makefile.in: Regenerate. + * doc/c-arc.texi: Fix typo. + +2006-06-01 Alan Modra + + * config/obj-ieee.c: Delete. + * config/obj-ieee.h: Delete. + * Makefile.am (OBJ_FORMATS): Remove ieee. + (OBJ_FORMAT_CFILES, OBJ_FORMAT_HFILES): Similarly. + (obj-ieee.o): Remove rule. + * Makefile.in: Regenerate. + * configure.in (atof): Remove tahoe. + (OBJ_MAYBE_IEEE): Don't define. + * configure: Regenerate. + * config.in: Regenerate. + * doc/Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2006-05-31 Daniel Jacobowitz + + * Makefile.am: Replace INTLLIBS and INTLDEPS with LIBINTL + and LIBINTL_DEP everywhere. + (INTLLIBS): Remove. + (INCLUDES, DEP_INCLUDES): Use @INCINTL@. + * acinclude.m4: Include new gettext macros. + * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS. + Remove local code for po/Makefile. + * Makefile.in, configure, doc/Makefile.in: Regenerated. + +2006-05-30 Nick Clifton + + * po/es.po: Updated Spanish translation. + +2006-05-06 Denis Chertykov + + * doc/c-avr.texi: New file. + * doc/Makefile.am (CPU_DOCS): Add c-avr.texi + * doc/all.texi: Set AVR + * doc/as.texinfo: Include c-avr.texi + +2006-05-28 Jie Zhang + + * config/bfin-parse.y (check_macfunc): Loose the condition of + calling check_multiply_halfregs (). + +2006-05-25 Jie Zhang + + * config/bfin-parse.y (asm_1): Better check and deal with + vector and scalar Multiply 16-Bit Operands instructions. + +2006-05-24 Nick Clifton + + * config/tc-hppa.c: Convert to ISO C90 format. + * config/tc-hppa.h: Likewise. + +2006-05-24 Carlos O'Donell + Randolph Chung + + * config/tc-hppa.c (is_tls_gdidx, is_tls_ldidx, is_tls_dtpoff, + is_tls_ieoff, is_tls_leoff): Define. + (fix_new_hppa): Handle TLS. + (cons_fix_new_hppa): Likewise. + (pa_ip): Likewise. + (md_apply_fix): Handle TLS relocs. + * config/tc-hppa.h (hppa_fix_adjustable): Handle TLS. + +2006-05-24 Bjoern Haase + + * config/tc-avr.c: Add new cpu targets avr6, avr2560 and avr2561. + +2006-05-23 Thiemo Seufer + David Ung + Nigel Stephens - * po/gas.pot: Revised template. + [ gas/ChangeLog ] + * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS): Rename. + (ISA_SUPPORTS_DSP_ASE, ISA_SUPPORTS_MT_ASE, ISA_HAS_64BIT_FPRS, + ISA_HAS_MXHC1): New macros. + (HAVE_32BIT_FPRS): Use ISA_HAS_64BIT_FPRS instead of + ISA_HAS_64BIT_REGS. Formatting fixes. Improved comments. + (mips_cpu_info): Change to use combined ASE/IS_ISA flag. + (MIPS_CPU_IS_ISA, MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, + MIPS_CPU_ASE_MT, MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX): New defines. + (mips_after_parse_args): Change default handling of float register + size to account for 32bit code with 64bit FP. Better sanity checking + of ISA/ASE/ABI option combinations. + (s_mipsset): Support switching of GPR and FPR sizes via + .set {g,f}p={32,64,default}. Better sanity checking for .set ASE + options. + (mips_elf_final_processing): We should record the use of 64bit FP + registers in 32bit code but we don't, because ELF header flags are + a scarce ressource. + (mips_cpu_info_table): Add ASE flags for CPUs with mandatory ASE + extensions. Add 4ksc, 4kec, 4kem, 4kep, 4ksd, m4kp, 24kec, 24kef, + 24kex, 34kc, 34kf, 34kx, 25kf CPU definitions. + (mips_cpu_info_from_isa): Use MIPS_CPU_IS_ISA. + * doc/c-mips.texi: Document .set {g,f}p={32,64,default}. Document + missing -march options. Document .set arch=CPU. Move .set smartmips + to ASE page. Use @code for .set FOO examples. + +2006-05-23 Jie Zhang + + * config/tc-bfin.c (bfin_start_line_hook): Bump line counters + if needed. + +2006-05-23 Jie Zhang + + * config/bfin-defs.h (bfin_equals): Remove declaration. + * config/bfin-parse.y (asm_1): Remove "expr ASSIGN expr". + * config/tc-bfin.c (bfin_name_is_register): Remove. + (bfin_equals): Remove. + * config/tc-bfin.h (TC_EQUAL_IN_INSN): Redefine as 1. + (bfin_name_is_register): Remove declaration. 2006-05-19 Thiemo Seufer Nigel Stephens