X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2FChangeLog;h=5953cd0c96006dff56e6be3279538b06b273b1e1;hb=dc821c5f9ae5208ad1ec438718f75e224f856deb;hp=1b6401fe17fbd2eea9739dcb7301b6e6bd2adbed;hpb=e21440ba622e17a2f12a858a87a6a75ef90654ca;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/ChangeLog b/gas/ChangeLog index 1b6401fe17..5953cd0c96 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,152 @@ +2017-12-18 Jan Beulich + + * config/tc-i386.c (operand_type_check, pi): Switch .reg to + just .reg. + (operand_size_match): Qualify .anysize check with .reg one. + Extend .acc check to also cover .reg. + (operand_type_register_match): Drop m0 and m1 parameters. Switch + .reg to .byte/.word/.dword/.qword. Drop .acc special + handling. + (md_assemble): Expand .reg8 checks to .reg plus .bytes ones. + (optimize_imm, process_suffix, check_byte_reg, check_long_reg, + check_qword_reg, check_word_reg): Expand .reg checks to .reg + plus size ones. + (match_template): Drop arguments from calls to + operand_type_register_match(). + (build_modrm_byte, i386_addressing_mode, i386_index_check, + parse_real_register): Replace .reg checks. + * config/tc-i386-intel.c (i386_intel_simplify, + i386_intel_operand): Switch .reg16 to .word. + +2017-12-17 H.J. Lu + + PR gas/22623 + * gas/config/tc-i386.c (output_insn): Check pseudo prefix + without instruction. + * testsuite/gas/i386/i386.exp: Run inval-pseudo. + * testsuite/gas/i386/inval-pseudo.l: New file. + * testsuite/gas/i386/inval-pseudo.s: Likewise. + +2017-12-15 Jan Beulich + + * config/tc-i386.c (match_template): Add missing ! to + reg{x,y,z}mm checks in q- and l-suffix handling. + +2017-12-15 Jan Beulich + + * config/tc-i386.c (build_modrm_byte): Add missing ! to reg64 + check leading to abort(). + +2017-12-14 Nick Clifton + + * config/tc-m32c.c: Update address of FSF in copyright notice. + * config/tc-m32c.h: Likewise. + * config/tc-mt.c: Likewise. + * config/tc-mt.h: Likewise. + * config/tc-visium.c: Likewise. + * config/tc-visium.h: Likewise. + * testsuite/gas/rx/explode: Likewise. + +2017-12-13 Jim Wilson + + PR 22599 + * testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New. + +2017-12-13 Dimitar Dimitrov + + * testsuite/gas/pru/extern.s: New test for print of U16_PMEMM + relocation. + * testsuite/gas/pru/extern.d: New test driver. + +2017-12-12 Alan Modra + + PR 21118 + * config/tc-ppc.c (md_assemble): Don't mask register number. + +2017-12-07 Max Filippov + + * config/tc-xtensa.c (xg_order_trampoline_chain): Replace + xg_order_trampoline_chain_entry call with check for + canonicalized symbol equality and offset equality. + +2017-12-04 Alan Modra + + PR 22544 + * doc/as.texinfo (8byte): Correct. + +2017-12-04 Alan Modra + + * testsuite/gas/ppc/ppc.exp: Don't exclude VLE tests when little-endian. + * testsuite/gas/ppc/efs.d: Add -mbig to assembler options. + * testsuite/gas/ppc/efs2.d: Likewise. + * testsuite/gas/ppc/lsp-checks.d: Likewise. + * testsuite/gas/ppc/lsp.d: Likewise. + * testsuite/gas/ppc/spe.d: Likewise. + * testsuite/gas/ppc/spe2-checks.d: Likewise. + * testsuite/gas/ppc/spe2.d: Likewise. + * testsuite/gas/ppc/spe_ambiguous.d: Likewise. + * testsuite/gas/ppc/vle-mult-ld-st-insns.d: Likewise. + * testsuite/gas/ppc/vle-reloc.d: Likewise. + * testsuite/gas/ppc/vle-simple-1.d: Likewise. + * testsuite/gas/ppc/vle-simple-2.d: Likewise. + * testsuite/gas/ppc/vle-simple-3.d: Likewise. + * testsuite/gas/ppc/vle-simple-4.d: Likewise. + * testsuite/gas/ppc/vle-simple-5.d: Likewise. + * testsuite/gas/ppc/vle-simple-6.d: Likewise. + * testsuite/gas/ppc/vle.d: Likewise. + +2017-12-03 Jim Wilson + + * doc/c-riscv.texi (RISC-V-Directives): Move @section immediately after + @node. + +2017-12-01 Palmer Dabbelt + Jim Wilson + + * doc/as.texinfo (RISC-V): Alphabetize RISC-V entries. Change + RISC-V-Opts to RISC-V-Options. Delete redundant space. Add -fpic + and related options to option list. + * doc/c-riscv.texi: (RISC-V-Options): Renamed from RISC-V-Opts. + (RISC-V Options): Renamed from Options. Add missing period. + (-fpic): Also mention -fPIC. + (RISC-V Directives): New node. + +2017-12-01 Peter Bergner + + * config/tc-ppc.c (last_insn): Update type. + (insn_validate) : Likewise. + (ppc_setup_opcodes) : Likewise. + : Update types and printf format specifiers. + (ppc_insert_operand): Update return and argument types and remove + unneeded type casts. + : Update type. + (md_assemble): Remove unneeded type casts. + : Update type. + +2017-11-29 Jan Beulich + + * config/tc-i386.c (enum i386_error): Remove try_vector_disp8. + (mode_from_disp_size, build_modrm_byte, build_modrm_byte, + disp_size): Remove reference to .vec_disp8. + (output_disp): Likewise. Unconditionally use i.memshift. + (fits_in_vec_disp8): Rename to fits_in_disp8. + (type_names): Remove OPERAND_TYPE_VEC_DISP8 entry. + (optimize_disp): Use fits_in_disp8. + (check_VecOperands): Re-work (simplify) .disp8memshift + conditional handling. + +2017-11-29 Jan Beulich + + PR gas/21874 + * config/tc-i386-intel.c (i386_intel_simplify): Chain together + multiple segment override expressions. + (i386_intel_operand): Issue diagnostic for redundant segment + overrides. + * testsuite/gas/i386/intelok.e: New. + * testsuite/gas/i386/intelok.d: Reference intelok.e. + * testsuite/gas/i386/inval-seg.s: Add redundant override checks. + * testsuite/gas/i386/inval-seg.l: Adjust expectations. + 2017-11-29 Jim Wilson Palmer Dabbelt