X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2FChangeLog;h=5953cd0c96006dff56e6be3279538b06b273b1e1;hb=dc821c5f9ae5208ad1ec438718f75e224f856deb;hp=6fe0983c33ed39121c4e84ea84de4a05b7e5fd4c;hpb=be7d1531e1ce34efbdb9367f1483f9cdad477059;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/ChangeLog b/gas/ChangeLog index 6fe0983c33..5953cd0c96 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,363 @@ +2017-12-18 Jan Beulich + + * config/tc-i386.c (operand_type_check, pi): Switch .reg to + just .reg. + (operand_size_match): Qualify .anysize check with .reg one. + Extend .acc check to also cover .reg. + (operand_type_register_match): Drop m0 and m1 parameters. Switch + .reg to .byte/.word/.dword/.qword. Drop .acc special + handling. + (md_assemble): Expand .reg8 checks to .reg plus .bytes ones. + (optimize_imm, process_suffix, check_byte_reg, check_long_reg, + check_qword_reg, check_word_reg): Expand .reg checks to .reg + plus size ones. + (match_template): Drop arguments from calls to + operand_type_register_match(). + (build_modrm_byte, i386_addressing_mode, i386_index_check, + parse_real_register): Replace .reg checks. + * config/tc-i386-intel.c (i386_intel_simplify, + i386_intel_operand): Switch .reg16 to .word. + +2017-12-17 H.J. Lu + + PR gas/22623 + * gas/config/tc-i386.c (output_insn): Check pseudo prefix + without instruction. + * testsuite/gas/i386/i386.exp: Run inval-pseudo. + * testsuite/gas/i386/inval-pseudo.l: New file. + * testsuite/gas/i386/inval-pseudo.s: Likewise. + +2017-12-15 Jan Beulich + + * config/tc-i386.c (match_template): Add missing ! to + reg{x,y,z}mm checks in q- and l-suffix handling. + +2017-12-15 Jan Beulich + + * config/tc-i386.c (build_modrm_byte): Add missing ! to reg64 + check leading to abort(). + +2017-12-14 Nick Clifton + + * config/tc-m32c.c: Update address of FSF in copyright notice. + * config/tc-m32c.h: Likewise. + * config/tc-mt.c: Likewise. + * config/tc-mt.h: Likewise. + * config/tc-visium.c: Likewise. + * config/tc-visium.h: Likewise. + * testsuite/gas/rx/explode: Likewise. + +2017-12-13 Jim Wilson + + PR 22599 + * testsuite/gas/riscv/fsxxi.d, testsuite/gas/riscv/fsxxi.s: New. + +2017-12-13 Dimitar Dimitrov + + * testsuite/gas/pru/extern.s: New test for print of U16_PMEMM + relocation. + * testsuite/gas/pru/extern.d: New test driver. + +2017-12-12 Alan Modra + + PR 21118 + * config/tc-ppc.c (md_assemble): Don't mask register number. + +2017-12-07 Max Filippov + + * config/tc-xtensa.c (xg_order_trampoline_chain): Replace + xg_order_trampoline_chain_entry call with check for + canonicalized symbol equality and offset equality. + +2017-12-04 Alan Modra + + PR 22544 + * doc/as.texinfo (8byte): Correct. + +2017-12-04 Alan Modra + + * testsuite/gas/ppc/ppc.exp: Don't exclude VLE tests when little-endian. + * testsuite/gas/ppc/efs.d: Add -mbig to assembler options. + * testsuite/gas/ppc/efs2.d: Likewise. + * testsuite/gas/ppc/lsp-checks.d: Likewise. + * testsuite/gas/ppc/lsp.d: Likewise. + * testsuite/gas/ppc/spe.d: Likewise. + * testsuite/gas/ppc/spe2-checks.d: Likewise. + * testsuite/gas/ppc/spe2.d: Likewise. + * testsuite/gas/ppc/spe_ambiguous.d: Likewise. + * testsuite/gas/ppc/vle-mult-ld-st-insns.d: Likewise. + * testsuite/gas/ppc/vle-reloc.d: Likewise. + * testsuite/gas/ppc/vle-simple-1.d: Likewise. + * testsuite/gas/ppc/vle-simple-2.d: Likewise. + * testsuite/gas/ppc/vle-simple-3.d: Likewise. + * testsuite/gas/ppc/vle-simple-4.d: Likewise. + * testsuite/gas/ppc/vle-simple-5.d: Likewise. + * testsuite/gas/ppc/vle-simple-6.d: Likewise. + * testsuite/gas/ppc/vle.d: Likewise. + +2017-12-03 Jim Wilson + + * doc/c-riscv.texi (RISC-V-Directives): Move @section immediately after + @node. + +2017-12-01 Palmer Dabbelt + Jim Wilson + + * doc/as.texinfo (RISC-V): Alphabetize RISC-V entries. Change + RISC-V-Opts to RISC-V-Options. Delete redundant space. Add -fpic + and related options to option list. + * doc/c-riscv.texi: (RISC-V-Options): Renamed from RISC-V-Opts. + (RISC-V Options): Renamed from Options. Add missing period. + (-fpic): Also mention -fPIC. + (RISC-V Directives): New node. + +2017-12-01 Peter Bergner + + * config/tc-ppc.c (last_insn): Update type. + (insn_validate) : Likewise. + (ppc_setup_opcodes) : Likewise. + : Update types and printf format specifiers. + (ppc_insert_operand): Update return and argument types and remove + unneeded type casts. + : Update type. + (md_assemble): Remove unneeded type casts. + : Update type. + +2017-11-29 Jan Beulich + + * config/tc-i386.c (enum i386_error): Remove try_vector_disp8. + (mode_from_disp_size, build_modrm_byte, build_modrm_byte, + disp_size): Remove reference to .vec_disp8. + (output_disp): Likewise. Unconditionally use i.memshift. + (fits_in_vec_disp8): Rename to fits_in_disp8. + (type_names): Remove OPERAND_TYPE_VEC_DISP8 entry. + (optimize_disp): Use fits_in_disp8. + (check_VecOperands): Re-work (simplify) .disp8memshift + conditional handling. + +2017-11-29 Jan Beulich + + PR gas/21874 + * config/tc-i386-intel.c (i386_intel_simplify): Chain together + multiple segment override expressions. + (i386_intel_operand): Issue diagnostic for redundant segment + overrides. + * testsuite/gas/i386/intelok.e: New. + * testsuite/gas/i386/intelok.d: Reference intelok.e. + * testsuite/gas/i386/inval-seg.s: Add redundant override checks. + * testsuite/gas/i386/inval-seg.l: Adjust expectations. + +2017-11-29 Jim Wilson + Palmer Dabbelt + + * config/tc-riscv.c (riscv_frag_align_code): New local insn_alignment. + Early return if bytes less than or equal to insn_alignment. + * testsuite/gas/riscv/align-1.l: New. + * testsuite/gas/riscv/align-1.s: New. + * testsuite/gas/riscv/riscv.exp: Use run_dump_tests. Use run_list_test + for align-1. + + PR gas/22464 + * doc/c-i386.texi (-n): Clarify docs. + +2017-11-29 Renlin Li + + * config/tc-aarch64.c (reg_names): Fix IP1 register alias typo. + * testsuite/gas/aarch64/register_aliases.s: Add IP0 and IP1 tests. + * testsuite/gas/aarch64/register_aliases.d: Update. + +2017-11-29 Stefan Stroe + + * po/Make-in (datadir): Define as @datadir@. + (localedir): Define as @localedir@. + (gnulocaledir, gettextsrcdir): Use @datarootdir@. + +2017-11-29 Nick Clifton + + PR 22492 + * config/obj-elf.c (obj_elf_version): Use record_alignment rather + than bfd_set_section_alignment. + +2017-11-27 Andrew Waterman + Palmer Dabbelt + Jim Wilson + + * config/tc-riscv.c (riscv_handle_implicit_zero_offset): New. + (riscv_ip): Cases 'k', 'l', 'm', 'n', 'M', 'N', add call to + riscv_handle_implicit_zero_offset. At label load_store, replace + existing code with call to riscv_handle_implicit_zero_offset. + * testsuite/gas/riscv/c-ld.d, testsuite/gas/riscv/c-ld.s: New. + * testsuite/gas/riscv/c-lw.d, testsuite/gas/riscv/c-lw.s: New. + * testsuite/gas/riscv/riscv.exp: Run new tests. + +2017-11-27 Max Filippov + + * config/tc-xtensa.c (find_trampoline_seg): Add static variable + that caches the result of the most recent search. + +2017-11-27 Max Filippov + + * config/tc-xtensa.c (trampoline_chain_entry, trampoline_chain) + (trampoline_chain_index): New structures. + (trampoline_index): Add chain_index field. + (xg_order_trampoline_chain_entry, xg_sort_trampoline_chain) + (xg_find_chain_entry, xg_get_best_chain_entry) + (xg_order_trampoline_chain, xg_get_trampoline_chain) + (xg_find_best_eq_target, xg_add_location_to_chain) + (xg_create_trampoline_chain, xg_get_single_symbol_slot): New + functions. + (xg_relax_fixups): Call xg_find_best_eq_target to adjust jump + target to point to an existing jump. Call + xg_create_trampoline_chain to create new jump target. Call + xg_add_location_to_chain to add newly created trampoline jump + to the corresponding chain. + (add_jump_to_trampoline): Extract loop searching for a single + slot with a symbol into a separate function, replace that code + with a call to that function. + (relax_frag_immed): Call xg_find_best_eq_target to adjust jump + target to point to an existing jump. + * testsuite/gas/xtensa/all.exp: Add trampoline-2 test. + * testsuite/gas/xtensa/trampoline.d: Adjust absolute addresses + as many duplicate trampoline chains are now coalesced. + * testsuite/gas/xtensa/trampoline.s: Add _nop so that objdump + stays in sync with instruction stream. + * testsuite/gas/xtensa/trampoline-2.l: New test result file. + * testsuite/gas/xtensa/trampoline-2.s: New test source file. + +2017-11-27 Max Filippov + + * config/tc-xtensa.c (search_trampolines, get_best_trampoline): + Remove definitions. + (xg_find_best_trampoline_for_tinsn): New function. + (relax_frag_immed): Replace call to get_best_trampoline with a + call to xg_find_best_trampoline_for_tinsn. + * testsuite/gas/xtensa/trampoline.d: Adjust absolute addresses + as the placement of trampolines for relaxed branches has been + changed. + +2017-11-27 Max Filippov + + * config/tc-xtensa.c (trampoline_index): New structure. + (trampoline_seg): Replace trampoline list with trampoline index. + (xg_find_trampoline, xg_add_trampoline_to_index) + (xg_remove_trampoline_from_index, xg_add_trampoline_to_seg) + (xg_is_trampoline_frag_full, xg_get_fulcrum) + (xg_find_best_trampoline, xg_relax_fixup, xg_relax_fixups) + (xg_is_relaxable_fixup): New functions. + (J_MARGIN): New macro. + (xtensa_create_trampoline_frag): Use xg_add_trampoline_to_seg + instead of open-coded addition to the linked list. + (dump_trampolines): Iterate through the trampoline_seg::index. + (cached_fixupS, cached_fixup, fixup_cacheS, fixup_cache) + (fixup_order, xtensa_make_cached_fixup) + (xtensa_realloc_fixup_cache, xtensa_cache_relaxable_fixups) + (xtensa_find_first_cached_fixup, xtensa_delete_cached_fixup) + (xtensa_add_cached_fixup, check_and_update_trampolines): Remove + definitions. + (xg_relax_trampoline): Extract logic into separate functions, + replace body with a call to xg_relax_fixups. + (search_trampolines): Replace search in linked list with search + in index. Change data type of address-tracking variables from + int to offsetT. Replace abs with labs. + (xg_append_jump): Finish the trampoline frag if it's full. + (add_jump_to_trampoline): Remove trampoline frag from the index + if the frag is full. + * config/tc-xtensa.h (xtensa_frag_type): Remove next_trampoline. + * testsuite/gas/xtensa/trampoline.d: Adjust absolute addresses + as the placement of trampolines has slightly changed. + * testsuite/gas/xtensa/trampoline.s: Add _nop so that objdump + stays in sync with instruction stream. + +2017-11-27 Max Filippov + + * config/tc-xtensa.c (init_trampoline_frag): Replace pointer to + struct trampoline_frag parameter with pointer to fragS. + (xg_append_jump): Remove jump_around parameter. + (struct trampoline_frag): Remove. + (struct trampoline_seg): Change type of trampoline_list from + struct trampoline_frag to fragS. + (xtensa_create_trampoline_frag): Don't allocate struct + trampoline_frag. Initialize new fragS::tc_frag_data fields. + (dump_trampolines, xg_relax_trampoline, search_trampolines) + (get_best_trampoline, init_trampoline_frag) + (add_jump_to_trampoline, relax_frag_immed): Replace pointer to + struct trampoline_frag with a pointer to fragS. + (xg_append_jump): Remove jump_around parameter, use + fragS::tc_frag_data.jump_around_fix instead. + (xg_relax_trampoline, init_trampoline_frag) + (add_jump_to_trampoline): Don't pass jump_around parameter to + xg_append_jump. + * config/tc-xtensa.h (struct xtensa_frag_type): Add new fields: + needs_jump_around, next_trampoline and jump_around_fix. + +2017-11-27 Max Filippov + + * config/tc-xtensa.c (find_trampoline_seg): Move above the first + use. + (xtensa_create_trampoline_frag): Replace trampoline seg search + code with a call to find_trampoline_seg. + +2017-11-27 Max Filippov + + * config/tc-xtensa.c (xg_append_jump): New function. + (xg_relax_trampoline, init_trampoline_frag) + (add_jump_to_trampoline): Replace trampoline jump assembling + code with a call to xg_append_jump. + +2017-11-27 Max Filippov + + * config/tc-xtensa.c (xg_relax_trampoline): New function. + (xtensa_relax_frag): Replace trampoline relaxation code with a + call to xg_relax_trampoline. + +2017-11-27 Nick Clifton + + PR 22492 + * config/obj-elf.c (obj_elf_version): Set the alignment of the + .note section. + +2017-11-26 H.J. Lu + + * testsuite/gas/i386/sse-noavx.s: Add tests for fisttps and + fisttpl. + * testsuite/gas/i386/x86-64-sse-noavx.s: Likewise. + * testsuite/gas/i386/ilp32/x86-64-sse-noavx.d: Updated. + * testsuite/gas/i386/sse-noavx.d: Likewise. + * testsuite/gas/i386/x86-64-sse-noavx.d: Likewise. + +2017-11-24 Jim Wilson + + * write.h (FAKE_LABEL_CHAR): Expand comment. + +2017-11-24 Jan Beulich + + * config/tc-i386.c (check_VecOperations): Check register type + for masking. Quote the actual register name in the respective + diagnostic. Check {z} wasn't specified on its own. + * testsuite/gas/i386/inval-avx512f.s, + testsuite/gas/i386/x86-64-inval-avx512f.s: Add further bad + masking tests. + * testsuite/gas/i386/inval-avx512f.l, + testsuite/gas/i386/x86-64-inval-avx512f.l: Adjust expectations. + +2017-11-24 Jan Beulich + + * testsuite/gas/i386/intel.d, testsuite/gas/i386/opcode.d, + testsuite/gas/i386/opcode-suffix.d, testsuite/gas/i386/sse3.d, + testsuite/gas/i386/sse-noavx.d, testsuite/gas/i386/x86-64-sse3.d, + testsuite/gas/i386/x86-64-sse-noavx.d, + testsuite/gas/i386/ilp32/x86-64-sse3.d, + testsuite/gas/i386/ilp32/x86-64-sse-noavx.d: Adjust expectations. + +2017-11-23 Jim Wilson + + * testsuite/gas/all/err-fakelabel.s (dg-error): Also accept fatal error + string. + + * as.c (INITIALIZING_EMULS): Define. + * config/obj-multi.h (FAKE_LABEL_NAME): When INITIALIZING_EMULS set, + don't define it. + 2017-11-23 Igor Tsimbalist * testsuite/gas/i386/avx512f_vaes-intel.d: Regenerate. @@ -1183,19 +1543,6 @@ * testsuite/gas/elf/dwarf2-6.d: Likewise. * testsuite/gas/elf/dwarf2-7.d: Likewise. -2017-08-01 H.J. Lu - - PR gas/21874 - * config/tc-i386-intel.c (i386_intel_operand): Update segment - register check. - * testsuite/gas/i386/intelok.s: Replace "fs:gs:[eax]" with - "fs:[eax]". - * testsuite/gas/i386/inval-seg.s: Add tests for invalid segment - register. - * testsuite/gas/i386/x86-64-inval-seg.s: Likewise. - * testsuite/gas/i386/inval-seg.l: Updated. - * testsuite/gas/i386/x86-64-inval-seg.l: Likewise. - 2017-07-31 John David Anglin * config/tc-hppa.c (pa_ip): Clear `d' bit in branch on bit instructions