X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2FChangeLog;h=92a8b348cf3c135de485ea7c73389d2b267a38c5;hb=b2a5fbdc946c0b4a0032f4d9f8cf23d87f5a2dd6;hp=bae8e5fc70493e6bd84070c9c4fa3c80e3213a7c;hpb=3251495bd703dad0798b68acb17205f02b293f4b;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/ChangeLog b/gas/ChangeLog index bae8e5fc70..92a8b348cf 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,219 @@ +2010-09-23 Matthew Gretton-Dann + + * config/tc-arm.c (arm_ext_v6m): New variable. + (arm_ext_m): Add support for OS extension. + (arm_ext_os): New variable. + (do_t_swi): In v6-M ensure we have the OS extension. + (arm_cpus): The cortex-m1 and cortex-m0 options have the OS + extension by default. + (arm_archs): Add armv6s-m. + (arm_extensions): Add 'os' extension. + (cpu_arch_ver): Add support for v6S-M. + * doc/c-arm.texi: Document the OS Extension, and v6-m and v6s-m + architecture options. + +2010-09-23 Matthew Gretton-Dann + + * config/tc-arm.c (arm_ext_v6z): Remove. + (arm_ext_sec): New variable. + (do_t_smc): In Thumb state SMC requires v7-A. + (insns): Make SMC depend on Security Extensions. + (arm_cpus): All -mcpu=cortex-a* options have the Security Extensions. + (arm_extensions): Add 'sec' extension. + (cpu_arch_ver): Reorder. + (aeabi_set_public_attributes): Emit Tag_Virtualization_use as + appropriate. + * doc/c-arm.texi: Document Security Extensions. + +2010-09-23 Matthew Gretton-Dann + + * config/tc-arm.c (arm_ext_mp): Add. + (do_pld): Update comment. + (insns): Add support for pldw. + (arm_cpus): Update cortex-a5, cortex-a9, and cortex-a15 to support + MP extension. + (arm_extensions): Add 'mp' extension. + (aeabi_set_public_attributes): Emit correct build attribute when + MP extension is enabled. + * doc/c-arm.texi: Update for MP extensions. + +2010-09-23 Matthew Gretton-Dann + + * config/tc-arm.c (md_pseduo_table): Add .arch_extension directive. + (arm_option_extension_value_table): Add. + (arm_extensions): Change type. + (arm_option_cpu_table): Rename... + (arm_option_fpu_table): ...to this. + (arm_fpus): Change type. + (arm_parse_extension): Enforce alphabetical order. Allow + extensions to be removed. + (arm_parse_arch): Allow extensions to be specified with -march. + (s_arm_arch_extension): Add. + (s_arm_fpu): Update for type changes. + * doc/c-arm.texi: Document changes to infrastructure. + +2010-09-23 Alan Modra + + * config/tc-mn10300.c (tc_gen_reloc): Replace absolute symbols + with the absolute section symbol. + +2010-09-22 Mike Frysinger + + * config/bfin-parse.y: Fix typo in BYTEOP16P comment. + +2010-09-22 Robin Getz + + * config/bfin-parse.y (is_store): New function. + (gen_multi_instr_1): Check parallel slots for store insns. + +2010-09-22 Robin Getz + + * config/bfin-defs.h (IS_EMUDAT): New define. + * config/bfin-parse.y: Accept EMUDAT for any register move. + +2010-09-22 Robin Getz + + * config/bfin-parse.y: Improve error messages. + +2010-09-22 Robin Getz + + * config/bfin-parse.y (DBG): Fix regno encoding. + (DBGCMPLX): Likewise. + +2010-09-22 Robin Getz + + * config/bfin-lex.l: Accept multibyte chars in symbol names. + +2010-09-22 Robin Getz + + * config/bfin-defs.h (statusflags): Add AC0_COPY, V_COPY, and RND_MOD. + * config/bfin-lex.l: Tokenize AC0_COPY, V_COPY, and RND_MOD. + +2010-09-22 Mike Frysinger + + * config/bfin-aux.h (bfin_gen_pseudochr): New prototype. + * config/tc-bfin.c (bfin_gen_pseudochr): New function. + * config/bfin-parse.y: Call bfin_gen_pseudochr for OUTC tokens. + +2010-09-22 Mike Frysinger + + * config/bfin-lex.l (abort): Accept case-insensitive abort insn. + * config/bfin-parse.y (ABORT): Handle the ABORT token. + +2010-09-22 Mike Frysinger + + * config/tc-bfin.c (bfin_cpus[]): Add 0.2 for bf512/bf514/bf516/bf518. + +2010-09-22 Mike Frysinger + + * doc/c-bfin.texi (-mcpu): Add bf592. + * config/tc-bfin.c (bfin_cpu_type): Add BFIN_CPU_BF592. + (bfin_cpus[]): Add 0.0/0.1 for bf592. + +2010-09-22 Mike Frysinger + + * config/tc-bfin.c (comment_chars): Add #. + +2010-09-20 Matthew Gretton-Dann + + * config/tc-arm.c (arm_cpus): Correct canonical names for Cortex CPUs. + +2010-09-20 Richard Henderson + + * config/tc-alpha.c (tc_gen_reloc): Remove hack around + bfd_perform_reloc for OBJ_ELF. + +2010-09-17 Tejas Belagod + + * config/tc-arm.c (do_t_ldmstm): Add logic to handle single-register + list for ldm/stm. + +2010-09-17 Tejas Belagod + + * config/tc-arm.c (parse_psr): Add condition for matching "APSR" on + non-M-arch cpus. + (psrs): Add entry for PSR flags, g, nzcvq, nzcvqg. + +2010-09-17 Tejas Belagod + + * config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead + of just RR. + +2010-09-17 Andrew Burgess + + PR gas/12011 + * config/obj-elf.c (obj_elf_parse_section_letters): Correct test + for error return from md_elf_section_letter. + * config/tc-alpha.c (alpha_elf_section_letter): Correct error message. + * config/tc-i386.c (x86_64_section_letter): Likewise. + * config/tc-ia64.c (ia64_elf_section_letter): Likewise. + * config/tc-mep.c (mep_elf_section_letter): Likewise. + +2010-09-15 Kai Tietz + + * config/obj-coff-seh.c (seh_validate_seg): New funtion. + (obj_coff_seh_endproc): Add check for segment. + (obj_coff_seh_endprologue): Likewise. + (obj_coff_seh_pushreg): Likewise. + (obj_coff_seh_pushframe): Likewise. + (obj_coff_seh_save): Likewise. + (obj_coff_seh_setframe): Likewise. + + * config/obj-coff-seh.h (seh_context): New member code_seg. + * config/obj-coff-seh.c: Implementing xdata/pdata section cloning + for link-once code-segment. + +2010-09-14 Jie Zhang + + * doc/c-arm.texi: Document -mcpu=cortex-m4. + +2010-09-09 H.J. Lu + + * config/tc-i386.c (build_vex_prefix): Check VEXW1 for 2-byte + VEX prefix. + +2010-09-09 Joseph Myers + + * doc/c-tic6x.texi (.c6xabi_attribute): Document directive. + +2010-09-09 Matthew Gretton-Dann + + * config/tc-arm.c (arm_cpus): Add cortex-a15 entry. + * doc/c-arm.texi: Document -mcpu=cortex-a15. + +2010-09-09 Gunther Nikl + + * gas/config/tc-m68k.c (tc_gen_reloc): Handle references to defined + weak symbols first if generating an a.out object. + +2010-09-09 Tejas Belagod + + * config/tc-arm.c (md_apply_fix): Check if widened add, sub are + flag-setting and handle accordingly. + +2010-09-09 Nick Clifton + + PR gas/11972 + * config/tc-arm.c (parse_big_immediate): Allow for bignums being + extended to the size of a .octa. + +2010-09-08 Julian Brown + + * config/tc-arm.c (create_neon_reg_alias): Deal with case + sensitivity. + +2010-09-08 Nick Clifton + + PR gas/11973 + * config/tc-mn10300.c (md_convert_frag): Zero out top two bytes of + long call instruction's displacement. + +2010-09-03 H.J. Lu + + PR gas/11974 + * config/tc-i386.c (i386_finalize_immediate): Check flag_code + instead of use_rela_relocations for 64bit. + 2010-09-02 Richard Henderson * dw2gencfi.c (TC_DWARF2_EMIT_OFFSET): Provide default.