X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fconfig%2Ftc-aarch64.c;h=d29aa111ea1c2306f7ef19fbc477f4912c82519c;hb=116adc27470ed3682b6236e44e3b18838673036c;hp=4ae27f76ed9a9bdc6f058ca43f5f58b9cc30345f;hpb=104fefeebb544b7745bb353b63110afa46119647;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 4ae27f76ed..d29aa111ea 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -1,6 +1,6 @@ /* tc-aarch64.c -- Assemble for the AArch64 ISA - Copyright (C) 2009-2018 Free Software Foundation, Inc. + Copyright (C) 2009-2019 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of GAS. @@ -1993,6 +1993,14 @@ s_aarch64_inst (int ignored ATTRIBUTE_UNUSED) demand_empty_rest_of_line (); } +static void +s_aarch64_cfi_b_key_frame (int ignored ATTRIBUTE_UNUSED) +{ + demand_empty_rest_of_line (); + struct fde_entry *fde = frchain_now->frch_cfi_data->cur_fde_data; + fde->pauth_key = AARCH64_PAUTH_KEY_B; +} + #ifdef OBJ_ELF /* Emit BFD_RELOC_AARCH64_TLSDESC_ADD on the next ADD instruction. */ @@ -2067,6 +2075,7 @@ const pseudo_typeS md_pseudo_table[] = { {"arch", s_aarch64_arch, 0}, {"arch_extension", s_aarch64_arch_extension, 0}, {"inst", s_aarch64_inst, 0}, + {"cfi_b_key_frame", s_aarch64_cfi_b_key_frame, 0}, #ifdef OBJ_ELF {"tlsdescadd", s_tlsdescadd, 0}, {"tlsdesccall", s_tlsdesccall, 0}, @@ -3680,7 +3689,7 @@ parse_address_main (char **str, aarch64_opnd_info *operand, } /* If at this point neither .preind nor .postind is set, we have a - bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */ + bare [Rn]{!}; reject [Rn]! accept [Rn] as a shorthand for [Rn,#0]. */ if (operand->addr.preind == 0 && operand->addr.postind == 0) { if (operand->addr.writeback) @@ -5126,6 +5135,7 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode, case AARCH64_OPND_Rm: case AARCH64_OPND_Rt: case AARCH64_OPND_Rt2: + case AARCH64_OPND_Rt_SP: case AARCH64_OPND_Rs: case AARCH64_OPND_Ra: case AARCH64_OPND_Rt_SYS: @@ -5502,6 +5512,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_Rd_SP: case AARCH64_OPND_Rn_SP: + case AARCH64_OPND_Rt_SP: case AARCH64_OPND_SVE_Rn_SP: case AARCH64_OPND_Rm_SP: po_int_reg_or_fail (REG_TYPE_R_SP); @@ -5626,6 +5637,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_SVE_Zm3_INDEX: case AARCH64_OPND_SVE_Zm3_22_INDEX: + case AARCH64_OPND_SVE_Zm3_11_INDEX: case AARCH64_OPND_SVE_Zm4_INDEX: case AARCH64_OPND_SVE_Zn_INDEX: reg_type = REG_TYPE_ZN; @@ -5741,7 +5753,10 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_CCMP_IMM: case AARCH64_OPND_SIMM5: case AARCH64_OPND_FBITS: + case AARCH64_OPND_TME_UIMM16: case AARCH64_OPND_UIMM4: + case AARCH64_OPND_UIMM4_ADDG: + case AARCH64_OPND_UIMM10: case AARCH64_OPND_UIMM3_OP1: case AARCH64_OPND_UIMM3_OP2: case AARCH64_OPND_IMM_VLSL: @@ -5768,6 +5783,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_IMM_ROT3: case AARCH64_OPND_SVE_IMM_ROT1: case AARCH64_OPND_SVE_IMM_ROT2: + case AARCH64_OPND_SVE_IMM_ROT3: po_imm_nc_or_fail (); info->imm.value = val; break; @@ -6212,6 +6228,8 @@ parse_operands (char *str, const aarch64_opcode *opcode) case AARCH64_OPND_ADDR_SIMM9: case AARCH64_OPND_ADDR_SIMM9_2: + case AARCH64_OPND_ADDR_SIMM11: + case AARCH64_OPND_ADDR_SIMM13: po_misc_or_fail (parse_address (&str, info)); if (info->addr.pcrel || info->addr.offset.is_reg || (!info->addr.preind && !info->addr.postind) @@ -6759,9 +6777,12 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str) == AARCH64_OPND_CLASS_INT_REG) && opnds[0].reg.regno == opnds[1].addr.base_regno && opnds[1].addr.base_regno != REG_SP + /* Exempt STG/STZG/ST2G/STZ2G. */ + && !(opnds[1].type == AARCH64_OPND_ADDR_SIMM13) && opnds[1].addr.writeback) as_warn (_("unpredictable transfer with writeback -- `%s'"), str); break; + case ldstpair_off: case ldstnapair_offs: case ldstpair_indexed: @@ -6771,6 +6792,8 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str) && (opnds[0].reg.regno == opnds[2].addr.base_regno || opnds[1].reg.regno == opnds[2].addr.base_regno) && opnds[2].addr.base_regno != REG_SP + /* Exempt STGP. */ + && !(opnds[2].type == AARCH64_OPND_ADDR_SIMM11) && opnds[2].addr.writeback) as_warn (_("unpredictable transfer with writeback -- `%s'"), str); /* Load operations must load different registers. */ @@ -7672,6 +7695,8 @@ fix_insn (fixS *fixP, uint32_t flags, offsetT value) case AARCH64_OPND_ADDR_SIMM9_2: case AARCH64_OPND_ADDR_SIMM10: case AARCH64_OPND_ADDR_UIMM12: + case AARCH64_OPND_ADDR_SIMM11: + case AARCH64_OPND_ADDR_SIMM13: /* Immediate offset in an address. */ insn = get_aarch64_insn (buf); @@ -8311,15 +8336,18 @@ aarch64_after_parse_args (void) const char * elf64_aarch64_target_format (void) { - if (strcmp (TARGET_OS, "cloudabi") == 0) - { - /* FIXME: What to do for ilp32_p ? */ - return target_big_endian ? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi"; - } +#ifdef TE_CLOUDABI + /* FIXME: What to do for ilp32_p ? */ + if (target_big_endian) + return "elf64-bigaarch64-cloudabi"; + else + return "elf64-littleaarch64-cloudabi"; +#else if (target_big_endian) return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64"; else return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64"; +#endif } void @@ -8714,6 +8742,11 @@ static const struct aarch64_cpu_option_table aarch64_cpus[] = { {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2, AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD), "Cortex-A76"}, + {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2, + AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 + | AARCH64_FEATURE_DOTPROD + | AARCH64_FEATURE_PROFILE), + "Ares"}, {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8, AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO), "Samsung Exynos M1"}, @@ -8721,6 +8754,16 @@ static const struct aarch64_cpu_option_table aarch64_cpus[] = { AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO | AARCH64_FEATURE_RDMA), "Qualcomm Falkor"}, + {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2, + AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 + | AARCH64_FEATURE_DOTPROD + | AARCH64_FEATURE_SSBS), + "Neoverse E1"}, + {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2, + AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 + | AARCH64_FEATURE_DOTPROD + | AARCH64_FEATURE_PROFILE), + "Neoverse N1"}, {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8, AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO | AARCH64_FEATURE_RDMA), @@ -8805,6 +8848,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_COMPNUM, 0)}, + {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME, 0), + AARCH64_ARCH_NONE}, {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0), AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0)}, @@ -8829,6 +8874,21 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { AARCH64_ARCH_NONE}, {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS, 0), AARCH64_ARCH_NONE}, + {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG, 0), + AARCH64_ARCH_NONE}, + {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0), + AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)}, + {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4, 0), + AARCH64_FEATURE (AARCH64_FEATURE_SVE2 + | AARCH64_FEATURE_SM4, 0)}, + {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES, 0), + AARCH64_FEATURE (AARCH64_FEATURE_SVE2 + | AARCH64_FEATURE_AES, 0)}, + {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3, 0), + AARCH64_FEATURE (AARCH64_FEATURE_SVE2 + | AARCH64_FEATURE_SHA3, 0)}, + {"bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM, 0), + AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0)}, {NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE}, };