X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fconfig%2Ftc-i386.c;h=653245f59d163cd74a7061e4038fc2fd96c80a9c;hb=13ae64f3c752ec57e71471d8820c72823a8d827e;hp=ed5c956888d81e27b0e629936b59f439ef2241e4;hpb=76a0ddacc00c5345b7eb4bcb88fa8fdb63ea7248;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index ed5c956888..653245f59d 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -1,5 +1,6 @@ /* i386.c -- Assemble code for the Intel 80386 - Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000 + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2001, 2002 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. @@ -21,12 +22,12 @@ /* Intel 80386 machine specific gas. Written by Eliot Dresselhaus (eliot@mgm.mit.edu). + x86_64 support by Jan Hubicka (jh@suse.cz) Bugs & suggestions are completely welcome. This is free software. Please help us make it better. */ -#include - #include "as.h" +#include "safe-ctype.h" #include "subsegs.h" #include "dwarf2dbg.h" #include "opcode/i386.h" @@ -47,27 +48,70 @@ #define SCALE1_WHEN_NO_INDEX 1 #endif -#define true 1 -#define false 0 +#ifdef BFD_ASSEMBLER +#define RELOC_ENUM enum bfd_reloc_code_real +#else +#define RELOC_ENUM int +#endif + +#ifndef DEFAULT_ARCH +#define DEFAULT_ARCH "i386" +#endif + +#ifndef INLINE +#if __GNUC__ >= 2 +#define INLINE __inline__ +#else +#define INLINE +#endif +#endif -static unsigned int mode_from_disp_size PARAMS ((unsigned int)); -static int fits_in_signed_byte PARAMS ((offsetT)); -static int fits_in_unsigned_byte PARAMS ((offsetT)); -static int fits_in_unsigned_word PARAMS ((offsetT)); -static int fits_in_signed_word PARAMS ((offsetT)); +static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int)); +static INLINE int fits_in_signed_byte PARAMS ((offsetT)); +static INLINE int fits_in_unsigned_byte PARAMS ((offsetT)); +static INLINE int fits_in_unsigned_word PARAMS ((offsetT)); +static INLINE int fits_in_signed_word PARAMS ((offsetT)); +static INLINE int fits_in_unsigned_long PARAMS ((offsetT)); +static INLINE int fits_in_signed_long PARAMS ((offsetT)); static int smallest_imm_type PARAMS ((offsetT)); static offsetT offset_in_range PARAMS ((offsetT, int)); static int add_prefix PARAMS ((unsigned int)); -static void set_16bit_code_flag PARAMS ((int)); +static void set_code_flag PARAMS ((int)); static void set_16bit_gcc_code_flag PARAMS ((int)); static void set_intel_syntax PARAMS ((int)); static void set_cpu_arch PARAMS ((int)); - -#ifdef BFD_ASSEMBLER -static bfd_reloc_code_real_type reloc - PARAMS ((int, int, bfd_reloc_code_real_type)); +static char *output_invalid PARAMS ((int c)); +static int i386_operand PARAMS ((char *operand_string)); +static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); +static const reg_entry *parse_register PARAMS ((char *reg_string, + char **end_op)); +static char *parse_insn PARAMS ((char *, char *)); +static char *parse_operands PARAMS ((char *, const char *)); +static void swap_operands PARAMS ((void)); +static void optimize_imm PARAMS ((void)); +static void optimize_disp PARAMS ((void)); +static int match_template PARAMS ((void)); +static int check_string PARAMS ((void)); +static int process_suffix PARAMS ((void)); +static int check_byte_reg PARAMS ((void)); +static int check_long_reg PARAMS ((void)); +static int check_qword_reg PARAMS ((void)); +static int check_word_reg PARAMS ((void)); +static int finalize_imm PARAMS ((void)); +static int process_operands PARAMS ((void)); +static const seg_entry *build_modrm_byte PARAMS ((void)); +static void output_insn PARAMS ((void)); +static void output_branch PARAMS ((void)); +static void output_jump PARAMS ((void)); +static void output_interseg_jump PARAMS ((void)); +static void output_imm PARAMS ((void)); +static void output_disp PARAMS ((void)); +#ifndef I386COFF +static void s_bss PARAMS ((int)); #endif +static const char *default_arch = DEFAULT_ARCH; + /* 'md_assemble ()' gathers together information and puts it into a i386_insn. */ @@ -103,12 +147,12 @@ struct _i386_insn operand. */ union i386_op op[MAX_OPERANDS]; + /* Flags for operands. */ + unsigned int flags[MAX_OPERANDS]; +#define Operand_PCrel 1 + /* Relocation type for operand */ -#ifdef BFD_ASSEMBLER - enum bfd_reloc_code_real disp_reloc[MAX_OPERANDS]; -#else - int disp_reloc[MAX_OPERANDS]; -#endif + RELOC_ENUM reloc[MAX_OPERANDS]; /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode the base index byte below. */ @@ -129,6 +173,7 @@ struct _i386_insn addressing modes of this insn are encoded. */ modrm_byte rm; + rex_byte rex; sib_byte sib; }; @@ -137,22 +182,20 @@ typedef struct _i386_insn i386_insn; /* List of chars besides those in app.c:symbol_chars that can start an operand. Used to prevent the scrubber eating vital white-space. */ #ifdef LEX_AT -const char extra_symbol_chars[] = "*%-(@"; +const char extra_symbol_chars[] = "*%-(@["; #else -const char extra_symbol_chars[] = "*%-("; +const char extra_symbol_chars[] = "*%-(["; #endif +#if (defined (TE_I386AIX) \ + || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \ + && !defined (TE_LINUX) \ + && !defined (TE_FreeBSD) \ + && !defined (TE_NetBSD))) /* This array holds the chars that always start a comment. If the pre-processor is disabled, these aren't very useful. */ -#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) -/* Putting '/' here makes it impossible to use the divide operator. - However, we need it for compatibility with SVR4 systems. */ const char comment_chars[] = "#/"; #define PREFIX_SEPARATOR '\\' -#else -const char comment_chars[] = "#"; -#define PREFIX_SEPARATOR '/' -#endif /* This array holds the chars that only start a comment at the beginning of a line. If the line seems to have the form '# 123 filename' @@ -162,9 +205,14 @@ const char comment_chars[] = "#"; #NO_APP at the beginning of its output. Also note that comments started like this one will always work if '/' isn't otherwise defined. */ -#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD)) const char line_comment_chars[] = ""; + #else +/* Putting '/' here makes it impossible to use the divide operator. + However, we need it for compatibility with SVR4 systems. */ +const char comment_chars[] = "#"; +#define PREFIX_SEPARATOR '/' + const char line_comment_chars[] = "/"; #endif @@ -220,9 +268,25 @@ static expressionS disp_expressions[2], im_expressions[2]; /* Current operand we are working on. */ static int this_operand; -/* 1 if we're writing 16-bit code, - 0 if 32-bit. */ -static int flag_16bit_code; +/* We support four different modes. FLAG_CODE variable is used to distinguish + these. */ + +enum flag_code { + CODE_32BIT, + CODE_16BIT, + CODE_64BIT }; +#define NUM_FLAG_CODE ((int) CODE_64BIT + 1) + +static enum flag_code flag_code; +static int use_rela_relocations = 0; + +/* The names used to print error messages. */ +static const char *flag_code_names[] = + { + "32", + "16", + "64" + }; /* 1 for intel syntax, 0 if att syntax. */ @@ -243,23 +307,31 @@ static int quiet_warnings = 0; static const char *cpu_arch_name = NULL; /* CPU feature flags. */ -static unsigned int cpu_arch_flags = 0; +static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64; + +/* If set, conditional jumps are not automatically promoted to handle + larger than a byte offset. */ +static unsigned int no_cond_jump_promotion = 0; + +/* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ +symbolS *GOT_symbol; /* Interface to relax_segment. - There are 2 relax states for 386 jump insns: one for conditional & - one for unconditional jumps. This is because these two types of - jumps add different sizes to frags when we're figuring out what - sort of jump to choose to reach a given label. */ + There are 3 major relax states for 386 jump insns because the + different types of jumps add different sizes to frags when we're + figuring out what sort of jump to choose to reach a given label. */ /* Types. */ +#define UNCOND_JUMP 0 #define COND_JUMP 1 -#define UNCOND_JUMP 2 +#define COND_JUMP86 2 + /* Sizes. */ #define CODE16 1 #define SMALL 0 -#define SMALL16 (SMALL|CODE16) +#define SMALL16 (SMALL | CODE16) #define BIG 2 -#define BIG16 (BIG|CODE16) +#define BIG16 (BIG | CODE16) #ifndef INLINE #ifdef __GNUC__ @@ -269,10 +341,12 @@ static unsigned int cpu_arch_flags = 0; #endif #endif -#define ENCODE_RELAX_STATE(type,size) \ - ((relax_substateT)((type<<2) | (size))) -#define SIZE_FROM_RELAX_STATE(s) \ - ( (((s) & 0x3) == BIG ? 4 : (((s) & 0x3) == BIG16 ? 2 : 1)) ) +#define ENCODE_RELAX_STATE(type, size) \ + ((relax_substateT) (((type) << 2) | (size))) +#define TYPE_FROM_RELAX_STATE(s) \ + ((s) >> 2) +#define DISP_SIZE_FROM_RELAX_STATE(s) \ + ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1))) /* This table is used by relax_frag to promote short jumps to long ones where necessary. SMALL (short) jumps may be promoted to BIG @@ -287,31 +361,38 @@ const relax_typeS md_relax_table[] = /* The fields are: 1) most positive reach of this state, 2) most negative reach of this state, - 3) how many bytes this mode will add to the size of the current frag + 3) how many bytes this mode will have in the variable part of the frag 4) which index into the table to try if we can't fit into this one. */ - {1, 1, 0, 0}, - {1, 1, 0, 0}, - {1, 1, 0, 0}, - {1, 1, 0, 0}, - - {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, - {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, - /* dword conditionals adds 4 bytes to frag: - 1 extra opcode byte, 3 extra displacement bytes. */ + + /* UNCOND_JUMP states. */ + {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, + {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, + /* dword jmp adds 4 bytes to frag: + 0 extra opcode bytes, 4 displacement bytes. */ {0, 0, 4, 0}, - /* word conditionals add 2 bytes to frag: - 1 extra opcode byte, 1 extra displacement byte. */ + /* word jmp adds 2 byte2 to frag: + 0 extra opcode bytes, 2 displacement bytes. */ {0, 0, 2, 0}, - {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)}, - {127 + 1, -128 + 1, 0, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)}, - /* dword jmp adds 3 bytes to frag: - 0 extra opcode bytes, 3 extra displacement bytes. */ + /* COND_JUMP states. */ + {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)}, + {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)}, + /* dword conditionals adds 5 bytes to frag: + 1 extra opcode byte, 4 displacement bytes. */ + {0, 0, 5, 0}, + /* word conditionals add 3 bytes to frag: + 1 extra opcode byte, 2 displacement bytes. */ {0, 0, 3, 0}, - /* word jmp adds 1 byte to frag: - 0 extra opcode bytes, 1 extra displacement byte. */ - {0, 0, 1, 0} + /* COND_JUMP86 states. */ + {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)}, + {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)}, + /* dword conditionals adds 5 bytes to frag: + 1 extra opcode byte, 4 displacement bytes. */ + {0, 0, 5, 0}, + /* word conditionals add 4 bytes to frag: + 1 displacement byte and a 3 byte long branch insn. */ + {0, 0, 4, 0} }; static const arch_entry cpu_arch[] = { @@ -324,11 +405,50 @@ static const arch_entry cpu_arch[] = { {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX }, {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE }, - {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX|Cpu3dnow }, - {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|Cpu3dnow }, + {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 }, + {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow }, + {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow }, + {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 }, {NULL, 0 } }; +const pseudo_typeS md_pseudo_table[] = +{ +#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) + {"align", s_align_bytes, 0}, +#else + {"align", s_align_ptwo, 0}, +#endif + {"arch", set_cpu_arch, 0}, +#ifndef I386COFF + {"bss", s_bss, 0}, +#endif + {"ffloat", float_cons, 'f'}, + {"dfloat", float_cons, 'd'}, + {"tfloat", float_cons, 'x'}, + {"value", cons, 2}, + {"noopt", s_ignore, 0}, + {"optim", s_ignore, 0}, + {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, + {"code16", set_code_flag, CODE_16BIT}, + {"code32", set_code_flag, CODE_32BIT}, + {"code64", set_code_flag, CODE_64BIT}, + {"intel_syntax", set_intel_syntax, 1}, + {"att_syntax", set_intel_syntax, 0}, + {"file", dwarf2_directive_file, 0}, + {"loc", dwarf2_directive_loc, 0}, + {0, 0, 0} +}; + +/* For interface with expression (). */ +extern char *input_line_pointer; + +/* Hash table for instruction mnemonic lookup. */ +static struct hash_control *op_hash; + +/* Hash table for register lookup. */ +static struct hash_control *reg_hash; + void i386_align_code (fragP, count) fragS *fragP; @@ -401,9 +521,14 @@ i386_align_code (fragP, count) f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 }; + /* ??? We can't use these fillers for x86_64, since they often kills the + upper halves. Solve later. */ + if (flag_code == CODE_64BIT) + count = 1; + if (count > 0 && count <= 15) { - if (flag_16bit_code) + if (flag_code == CODE_16BIT) { memcpy (fragP->fr_literal + fragP->fr_fix, f16_patt[count - 1], count); @@ -418,23 +543,11 @@ i386_align_code (fragP, count) } } -static char *output_invalid PARAMS ((int c)); -static int i386_operand PARAMS ((char *operand_string)); -static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float)); -static const reg_entry *parse_register PARAMS ((char *reg_string, - char **end_op)); - -#ifndef I386COFF -static void s_bss PARAMS ((int)); -#endif - -symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ - static INLINE unsigned int mode_from_disp_size (t) unsigned int t; { - return (t & Disp8) ? 1 : (t & (Disp16 | Disp32)) ? 2 : 0; + return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0; } static INLINE int @@ -464,13 +577,33 @@ fits_in_signed_word (num) { return (-32768 <= num) && (num <= 32767); } +static INLINE int +fits_in_signed_long (num) + offsetT num ATTRIBUTE_UNUSED; +{ +#ifndef BFD64 + return 1; +#else + return (!(((offsetT) -1 << 31) & num) + || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31)); +#endif +} /* fits_in_signed_long() */ +static INLINE int +fits_in_unsigned_long (num) + offsetT num ATTRIBUTE_UNUSED; +{ +#ifndef BFD64 + return 1; +#else + return (num & (((offsetT) 2 << 31) - 1)) == num; +#endif +} /* fits_in_unsigned_long() */ static int smallest_imm_type (num) offsetT num; { - if (cpu_arch_flags != 0 - && cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486)) + if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)) { /* This code is disabled on the 486 because all the Imm1 forms in the opcode table are slower on the i486. They're the @@ -478,15 +611,19 @@ smallest_imm_type (num) displacement, which has another syntax if you really want to use that form. */ if (num == 1) - return Imm1 | Imm8 | Imm8S | Imm16 | Imm32; + return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64; } return (fits_in_signed_byte (num) - ? (Imm8S | Imm8 | Imm16 | Imm32) + ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64) : fits_in_unsigned_byte (num) - ? (Imm8 | Imm16 | Imm32) + ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64) : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) - ? (Imm16 | Imm32) - : (Imm32)); + ? (Imm16 | Imm32 | Imm32S | Imm64) + : fits_in_signed_long (num) + ? (Imm32 | Imm32S | Imm64) + : fits_in_unsigned_long (num) + ? (Imm32 | Imm64) + : Imm64); } static offsetT @@ -501,12 +638,16 @@ offset_in_range (val, size) case 1: mask = ((addressT) 1 << 8) - 1; break; case 2: mask = ((addressT) 1 << 16) - 1; break; case 4: mask = ((addressT) 2 << 31) - 1; break; +#ifdef BFD64 + case 8: mask = ((addressT) 2 << 63) - 1; break; +#endif default: abort (); } /* If BFD64, sign extend val. */ - if ((val & ~(((addressT) 2 << 31) - 1)) == 0) - val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); + if (!use_rela_relocations) + if ((val & ~(((addressT) 2 << 31) - 1)) == 0) + val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); if ((val & ~mask) != 0 && (val & ~mask) != ~mask) { @@ -529,42 +670,46 @@ add_prefix (prefix) int ret = 1; int q; - switch (prefix) - { - default: - abort (); - - case CS_PREFIX_OPCODE: - case DS_PREFIX_OPCODE: - case ES_PREFIX_OPCODE: - case FS_PREFIX_OPCODE: - case GS_PREFIX_OPCODE: - case SS_PREFIX_OPCODE: - q = SEG_PREFIX; - break; + if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16 + && flag_code == CODE_64BIT) + q = REX_PREFIX; + else + switch (prefix) + { + default: + abort (); + + case CS_PREFIX_OPCODE: + case DS_PREFIX_OPCODE: + case ES_PREFIX_OPCODE: + case FS_PREFIX_OPCODE: + case GS_PREFIX_OPCODE: + case SS_PREFIX_OPCODE: + q = SEG_PREFIX; + break; - case REPNE_PREFIX_OPCODE: - case REPE_PREFIX_OPCODE: - ret = 2; - /* fall thru */ - case LOCK_PREFIX_OPCODE: - q = LOCKREP_PREFIX; - break; + case REPNE_PREFIX_OPCODE: + case REPE_PREFIX_OPCODE: + ret = 2; + /* fall thru */ + case LOCK_PREFIX_OPCODE: + q = LOCKREP_PREFIX; + break; - case FWAIT_OPCODE: - q = WAIT_PREFIX; - break; + case FWAIT_OPCODE: + q = WAIT_PREFIX; + break; - case ADDR_PREFIX_OPCODE: - q = ADDR_PREFIX; - break; + case ADDR_PREFIX_OPCODE: + q = ADDR_PREFIX; + break; - case DATA_PREFIX_OPCODE: - q = DATA_PREFIX; - break; - } + case DATA_PREFIX_OPCODE: + q = DATA_PREFIX; + break; + } - if (i.prefix[q]) + if (i.prefix[q] != 0) { as_bad (_("same type of prefix used twice")); return 0; @@ -576,19 +721,31 @@ add_prefix (prefix) } static void -set_16bit_code_flag (new_16bit_code_flag) - int new_16bit_code_flag; +set_code_flag (value) + int value; { - flag_16bit_code = new_16bit_code_flag; + flag_code = value; + cpu_arch_flags &= ~(Cpu64 | CpuNo64); + cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); + if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer)) + { + as_bad (_("64bit mode not supported on this CPU.")); + } + if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386)) + { + as_bad (_("32bit mode not supported on this CPU.")); + } stackop_size = '\0'; } static void -set_16bit_gcc_code_flag (new_16bit_code_flag) - int new_16bit_code_flag; +set_16bit_gcc_code_flag (new_code_flag) + int new_code_flag; { - flag_16bit_code = new_16bit_code_flag; - stackop_size = new_16bit_code_flag ? 'l' : '\0'; + flag_code = new_code_flag; + cpu_arch_flags &= ~(Cpu64 | CpuNo64); + cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64); + stackop_size = 'l'; } static void @@ -599,7 +756,7 @@ set_intel_syntax (syntax_flag) int ask_naked_reg = 0; SKIP_WHITESPACE (); - if (! is_end_of_line[(unsigned char) *input_line_pointer]) + if (!is_end_of_line[(unsigned char) *input_line_pointer]) { char *string = input_line_pointer; int e = get_symbol_end (); @@ -636,7 +793,7 @@ set_cpu_arch (dummy) { SKIP_WHITESPACE (); - if (! is_end_of_line[(unsigned char) *input_line_pointer]) + if (!is_end_of_line[(unsigned char) *input_line_pointer]) { char *string = input_line_pointer; int e = get_symbol_end (); @@ -647,7 +804,8 @@ set_cpu_arch (dummy) if (strcmp (string, cpu_arch[i].name) == 0) { cpu_arch_name = cpu_arch[i].name; - cpu_arch_flags = cpu_arch[i].flags; + cpu_arch_flags = (cpu_arch[i].flags + | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64)); break; } } @@ -659,44 +817,38 @@ set_cpu_arch (dummy) else as_bad (_("missing cpu architecture")); + no_cond_jump_promotion = 0; + if (*input_line_pointer == ',' + && !is_end_of_line[(unsigned char) input_line_pointer[1]]) + { + char *string = ++input_line_pointer; + int e = get_symbol_end (); + + if (strcmp (string, "nojumps") == 0) + no_cond_jump_promotion = 1; + else if (strcmp (string, "jumps") == 0) + ; + else + as_bad (_("no such architecture modifier: `%s'"), string); + + *input_line_pointer = e; + } + demand_empty_rest_of_line (); } -const pseudo_typeS md_pseudo_table[] = +#ifdef BFD_ASSEMBLER +unsigned long +i386_mach () { -#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) - {"align", s_align_bytes, 0}, -#else - {"align", s_align_ptwo, 0}, -#endif - {"arch", set_cpu_arch, 0}, -#ifndef I386COFF - {"bss", s_bss, 0}, + if (!strcmp (default_arch, "x86_64")) + return bfd_mach_x86_64; + else if (!strcmp (default_arch, "i386")) + return bfd_mach_i386_i386; + else + as_fatal (_("Unknown architecture")); +} #endif - {"ffloat", float_cons, 'f'}, - {"dfloat", float_cons, 'd'}, - {"tfloat", float_cons, 'x'}, - {"value", cons, 2}, - {"noopt", s_ignore, 0}, - {"optim", s_ignore, 0}, - {"code16gcc", set_16bit_gcc_code_flag, 1}, - {"code16", set_16bit_code_flag, 1}, - {"code32", set_16bit_code_flag, 0}, - {"intel_syntax", set_intel_syntax, 1}, - {"att_syntax", set_intel_syntax, 0}, - {"file", dwarf2_directive_file, 0}, - {"loc", dwarf2_directive_loc, 0}, - {0, 0, 0} -}; - -/* For interface with expression (). */ -extern char *input_line_pointer; - -/* Hash table for instruction mnemonic lookup. */ -static struct hash_control *op_hash; - -/* Hash table for register lookup. */ -static struct hash_control *reg_hash; void md_begin () @@ -707,8 +859,8 @@ md_begin () op_hash = hash_new (); { - register const template *optab; - register templates *core_optab; + const template *optab; + templates *core_optab; /* Setup for loop. */ optab = i386_optab; @@ -729,7 +881,6 @@ md_begin () (PTR) core_optab); if (hash_err) { - hash_error: as_fatal (_("Internal Error: Can't hash %s: %s"), (optab - 1)->name, hash_err); @@ -745,7 +896,7 @@ md_begin () /* Initialize reg_hash hash table. */ reg_hash = hash_new (); { - register const reg_entry *regtab; + const reg_entry *regtab; for (regtab = i386_regtab; regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); @@ -753,38 +904,40 @@ md_begin () { hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab); if (hash_err) - goto hash_error; + as_fatal (_("Internal Error: Can't hash %s: %s"), + regtab->reg_name, + hash_err); } } /* Fill in lexical tables: mnemonic_chars, operand_chars. */ { - register int c; - register char *p; + int c; + char *p; for (c = 0; c < 256; c++) { - if (isdigit (c)) + if (ISDIGIT (c)) { digit_chars[c] = c; mnemonic_chars[c] = c; register_chars[c] = c; operand_chars[c] = c; } - else if (islower (c)) + else if (ISLOWER (c)) { mnemonic_chars[c] = c; register_chars[c] = c; operand_chars[c] = c; } - else if (isupper (c)) + else if (ISUPPER (c)) { - mnemonic_chars[c] = tolower (c); + mnemonic_chars[c] = TOLOWER (c); register_chars[c] = mnemonic_chars[c]; operand_chars[c] = c; } - if (isalpha (c) || isdigit (c)) + if (ISALPHA (c) || ISDIGIT (c)) identifier_chars[c] = c; else if (c >= 128) { @@ -836,15 +989,23 @@ pi (line, x) char *line; i386_insn *x; { - register template *p; - int i; + unsigned int i; fprintf (stdout, "%s: template ", line); pte (&x->tm); - fprintf (stdout, " modrm: mode %x reg %x reg/mem %x", + fprintf (stdout, " address: base %s index %s scale %x\n", + x->base_reg ? x->base_reg->reg_name : "none", + x->index_reg ? x->index_reg->reg_name : "none", + x->log2_scale_factor); + fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n", x->rm.mode, x->rm.reg, x->rm.regmem); - fprintf (stdout, " base %x index %x scale %x\n", - x->bi.base, x->bi.index, x->bi.scale); + fprintf (stdout, " sib: base %x index %x scale %x\n", + x->sib.base, x->sib.index, x->sib.scale); + fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n", + (x->rex & REX_MODE64) != 0, + (x->rex & REX_EXTX) != 0, + (x->rex & REX_EXTY) != 0, + (x->rex & REX_EXTZ) != 0); for (i = 0; i < x->operands; i++) { fprintf (stdout, " #%d: ", i + 1); @@ -864,7 +1025,7 @@ static void pte (t) template *t; { - int i; + unsigned int i; fprintf (stdout, " %d operands ", t->operands); fprintf (stdout, "opcode %x ", t->base_opcode); if (t->extension_opcode != None) @@ -919,20 +1080,25 @@ struct type_name char *tname; } -type_names[] = +static const type_names[] = { { Reg8, "r8" }, { Reg16, "r16" }, { Reg32, "r32" }, + { Reg64, "r64" }, { Imm8, "i8" }, { Imm8S, "i8s" }, { Imm16, "i16" }, { Imm32, "i32" }, + { Imm32S, "i32s" }, + { Imm64, "i64" }, { Imm1, "i1" }, { BaseIndex, "BaseIndex" }, { Disp8, "d8" }, { Disp16, "d16" }, { Disp32, "d32" }, + { Disp32S, "d32s" }, + { Disp64, "d64" }, { InOutPortReg, "InOutPortReg" }, { ShiftCount, "ShiftCount" }, { Control, "control reg" }, @@ -954,18 +1120,11 @@ static void pt (t) unsigned int t; { - register struct type_name *ty; + const struct type_name *ty; - if (t == Unknown) - { - fprintf (stdout, _("Unknown")); - } - else - { - for (ty = type_names; ty->mask; ty++) - if (t & ty->mask) - fprintf (stdout, "%s, ", ty->tname); - } + for (ty = type_names; ty->mask; ty++) + if (t & ty->mask) + fprintf (stdout, "%s, ", ty->tname); fflush (stdout); } @@ -988,12 +1147,13 @@ tc_i386_force_relocation (fixp) #ifdef BFD_ASSEMBLER static bfd_reloc_code_real_type reloc - PARAMS ((int, int, bfd_reloc_code_real_type)); + PARAMS ((int, int, int, bfd_reloc_code_real_type)); static bfd_reloc_code_real_type -reloc (size, pcrel, other) +reloc (size, pcrel, sign, other) int size; int pcrel; + int sign; bfd_reloc_code_real_type other; { if (other != NO_RELOC) @@ -1001,6 +1161,8 @@ reloc (size, pcrel, other) if (pcrel) { + if (!sign) + as_bad (_("There are no unsigned pc-relative relocations")); switch (size) { case 1: return BFD_RELOC_8_PCREL; @@ -1011,15 +1173,24 @@ reloc (size, pcrel, other) } else { - switch (size) - { - case 1: return BFD_RELOC_8; - case 2: return BFD_RELOC_16; - case 4: return BFD_RELOC_32; - } - as_bad (_("can not do %d byte relocation"), size); + if (sign) + switch (size) + { + case 4: return BFD_RELOC_X86_64_32S; + } + else + switch (size) + { + case 1: return BFD_RELOC_8; + case 2: return BFD_RELOC_16; + case 4: return BFD_RELOC_32; + case 8: return BFD_RELOC_64; + } + as_bad (_("can not do %s %d byte relocation"), + sign ? "signed" : "unsigned", size); } + abort (); return BFD_RELOC_NONE; } @@ -1036,34 +1207,57 @@ tc_i386_fix_adjustable (fixP) /* Prevent all adjustments to global symbols, or else dynamic linking will not work correctly. */ if (S_IS_EXTERNAL (fixP->fx_addsy) - || S_IS_WEAK (fixP->fx_addsy)) + || S_IS_WEAK (fixP->fx_addsy) + /* Don't adjust pc-relative references to merge sections in 64-bit + mode. */ + || (use_rela_relocations + && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0 + && fixP->fx_pcrel)) return 0; #endif /* adjust_reloc_syms doesn't know about the GOT. */ if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF || fixP->fx_r_type == BFD_RELOC_386_PLT32 || fixP->fx_r_type == BFD_RELOC_386_GOT32 + || fixP->fx_r_type == BFD_RELOC_386_TLS_GD + || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM + || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 + || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 + || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 + || fixP->fx_r_type == BFD_RELOC_386_TLS_LE + || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 + || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 + || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) return 0; return 1; } #else -#define reloc(SIZE,PCREL,OTHER) 0 -#define BFD_RELOC_16 0 -#define BFD_RELOC_32 0 -#define BFD_RELOC_16_PCREL 0 -#define BFD_RELOC_32_PCREL 0 -#define BFD_RELOC_386_PLT32 0 -#define BFD_RELOC_386_GOT32 0 -#define BFD_RELOC_386_GOTOFF 0 +#define reloc(SIZE,PCREL,SIGN,OTHER) 0 +#define BFD_RELOC_16 0 +#define BFD_RELOC_32 0 +#define BFD_RELOC_16_PCREL 0 +#define BFD_RELOC_32_PCREL 0 +#define BFD_RELOC_386_PLT32 0 +#define BFD_RELOC_386_GOT32 0 +#define BFD_RELOC_386_GOTOFF 0 +#define BFD_RELOC_386_TLS_GD 0 +#define BFD_RELOC_386_TLS_LDM 0 +#define BFD_RELOC_386_TLS_LDO_32 0 +#define BFD_RELOC_386_TLS_IE_32 0 +#define BFD_RELOC_386_TLS_LE_32 0 +#define BFD_RELOC_386_TLS_LE 0 +#define BFD_RELOC_X86_64_PLT32 0 +#define BFD_RELOC_X86_64_GOT32 0 +#define BFD_RELOC_X86_64_GOTPCREL 0 #endif -static int intel_float_operand PARAMS ((char *mnemonic)); +static int intel_float_operand PARAMS ((const char *mnemonic)); static int intel_float_operand (mnemonic) - char *mnemonic; + const char *mnemonic; { if (mnemonic[0] == 'f' && mnemonic[1] == 'i') return 2; @@ -1082,20 +1276,13 @@ void md_assemble (line) char *line; { - /* Points to template once we've found it. */ - const template *t; - - /* Count the size of the instruction generated. */ - int insn_size = 0; - int j; - char mnemonic[MAX_MNEM_SIZE]; /* Initialize globals. */ memset (&i, '\0', sizeof (i)); for (j = 0; j < MAX_OPERANDS; j++) - i.disp_reloc[j] = NO_RELOC; + i.reloc[j] = NO_RELOC; memset (disp_expressions, '\0', sizeof (disp_expressions)); memset (im_expressions, '\0', sizeof (im_expressions)); save_stack_p = save_stack; @@ -1103,1538 +1290,2221 @@ md_assemble (line) /* First parse an instruction mnemonic & call i386_operand for the operands. We assume that the scrubber has arranged it so that line[0] is the valid start of a (possibly prefixed) mnemonic. */ - { - char *l = line; - char *token_start = l; - char *mnem_p; - - /* Non-zero if we found a prefix only acceptable with string insns. */ - const char *expecting_string_instruction = NULL; - while (1) - { - mnem_p = mnemonic; - while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) - { - mnem_p++; - if (mnem_p >= mnemonic + sizeof (mnemonic)) - { - as_bad (_("no such instruction: `%s'"), token_start); - return; - } - l++; - } - if (!is_space_char (*l) - && *l != END_OF_INSN - && *l != PREFIX_SEPARATOR) - { - as_bad (_("invalid character %s in mnemonic"), - output_invalid (*l)); - return; - } - if (token_start == l) - { - if (*l == PREFIX_SEPARATOR) - as_bad (_("expecting prefix; got nothing")); - else - as_bad (_("expecting mnemonic; got nothing")); - return; - } + line = parse_insn (line, mnemonic); + if (line == NULL) + return; - /* Look up instruction (or prefix) via hash table. */ - current_templates = hash_find (op_hash, mnemonic); + line = parse_operands (line, mnemonic); + if (line == NULL) + return; - if (*l != END_OF_INSN - && (! is_space_char (*l) || l[1] != END_OF_INSN) - && current_templates - && (current_templates->start->opcode_modifier & IsPrefix)) - { - /* If we are in 16-bit mode, do not allow addr16 or data16. - Similarly, in 32-bit mode, do not allow addr32 or data32. */ - if ((current_templates->start->opcode_modifier & (Size16 | Size32)) - && (((current_templates->start->opcode_modifier & Size32) != 0) - ^ flag_16bit_code)) - { - as_bad (_("redundant %s prefix"), - current_templates->start->name); - return; - } - /* Add prefix, checking for repeated prefixes. */ - switch (add_prefix (current_templates->start->base_opcode)) - { - case 0: - return; - case 2: - expecting_string_instruction = current_templates->start->name; - break; - } - /* Skip past PREFIX_SEPARATOR and reset token_start. */ - token_start = ++l; - } - else - break; - } + /* Now we've parsed the mnemonic into a set of templates, and have the + operands at hand. */ + + /* All intel opcodes have reversed operands except for "bound" and + "enter". We also don't reverse intersegment "jmp" and "call" + instructions with 2 immediate operands so that the immediate segment + precedes the offset, as it does when in AT&T mode. "enter" and the + intersegment "jmp" and "call" instructions are the only ones that + have two immediate operands. */ + if (intel_syntax && i.operands > 1 + && (strcmp (mnemonic, "bound") != 0) + && !((i.types[0] & Imm) && (i.types[1] & Imm))) + swap_operands (); + + if (i.imm_operands) + optimize_imm (); + + if (i.disp_operands) + optimize_disp (); + + /* Next, we find a template that matches the given insn, + making sure the overlap of the given operands types is consistent + with the template operand types. */ - if (!current_templates) - { - /* See if we can get a match by trimming off a suffix. */ - switch (mnem_p[-1]) - { - case WORD_MNEM_SUFFIX: - case BYTE_MNEM_SUFFIX: - case SHORT_MNEM_SUFFIX: - case LONG_MNEM_SUFFIX: - i.suffix = mnem_p[-1]; - mnem_p[-1] = '\0'; - current_templates = hash_find (op_hash, mnemonic); - break; + if (!match_template ()) + return; - /* Intel Syntax. */ - case DWORD_MNEM_SUFFIX: - if (intel_syntax) - { - i.suffix = mnem_p[-1]; - mnem_p[-1] = '\0'; - current_templates = hash_find (op_hash, mnemonic); - break; - } - } - if (!current_templates) - { - as_bad (_("no such instruction: `%s'"), token_start); - return; - } - } + /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ + if (SYSV386_COMPAT + && intel_syntax + && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) + i.tm.base_opcode ^= FloatR; - /* Check if instruction is supported on specified architecture. */ - if (cpu_arch_flags != 0) - { - if (current_templates->start->cpu_flags & ~cpu_arch_flags) - { - as_warn (_("`%s' is not supported on `%s'"), - current_templates->start->name, cpu_arch_name); - } - else if ((Cpu386 & ~cpu_arch_flags) && !flag_16bit_code) - { - as_warn (_("use .code16 to ensure correct addressing mode")); - } - } + if (i.tm.opcode_modifier & FWait) + if (!add_prefix (FWAIT_OPCODE)) + return; - /* Check for rep/repne without a string instruction. */ - if (expecting_string_instruction - && !(current_templates->start->opcode_modifier & IsString)) - { - as_bad (_("expecting string instruction after `%s'"), - expecting_string_instruction); + /* Check string instruction segment overrides. */ + if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) + { + if (!check_string ()) return; - } + } - /* There may be operands to parse. */ - if (*l != END_OF_INSN) - { - /* 1 if operand is pending after ','. */ - unsigned int expecting_operand = 0; + if (!process_suffix ()) + return; - /* Non-zero if operand parens not balanced. */ - unsigned int paren_not_balanced; + /* Make still unresolved immediate matches conform to size of immediate + given in i.suffix. */ + if (!finalize_imm ()) + return; - do - { - /* Skip optional white space before operand. */ - if (is_space_char (*l)) - ++l; - if (!is_operand_char (*l) && *l != END_OF_INSN) - { - as_bad (_("invalid character %s before operand %d"), - output_invalid (*l), - i.operands + 1); - return; - } - token_start = l; /* after white space */ - paren_not_balanced = 0; - while (paren_not_balanced || *l != ',') - { - if (*l == END_OF_INSN) - { - if (paren_not_balanced) - { - if (!intel_syntax) - as_bad (_("unbalanced parenthesis in operand %d."), - i.operands + 1); - else - as_bad (_("unbalanced brackets in operand %d."), - i.operands + 1); - return; - } - else - break; /* we are done */ - } - else if (!is_operand_char (*l) && !is_space_char (*l)) - { - as_bad (_("invalid character %s in operand %d"), - output_invalid (*l), - i.operands + 1); - return; - } - if (!intel_syntax) - { - if (*l == '(') - ++paren_not_balanced; - if (*l == ')') - --paren_not_balanced; - } - else - { - if (*l == '[') - ++paren_not_balanced; - if (*l == ']') - --paren_not_balanced; - } - l++; - } - if (l != token_start) - { /* Yes, we've read in another operand. */ - unsigned int operand_ok; - this_operand = i.operands++; - if (i.operands > MAX_OPERANDS) - { - as_bad (_("spurious operands; (%d operands/instruction max)"), - MAX_OPERANDS); - return; - } - /* Now parse operand adding info to 'i' as we go along. */ - END_STRING_AND_SAVE (l); - - if (intel_syntax) - operand_ok = - i386_intel_operand (token_start, - intel_float_operand (mnemonic)); - else - operand_ok = i386_operand (token_start); - - RESTORE_END_STRING (l); - if (!operand_ok) - return; - } - else - { - if (expecting_operand) - { - expecting_operand_after_comma: - as_bad (_("expecting operand after ','; got nothing")); - return; - } - if (*l == ',') - { - as_bad (_("expecting operand before ','; got nothing")); - return; - } - } + if (i.types[0] & Imm1) + i.imm_operands = 0; /* kludge for shift insns. */ + if (i.types[0] & ImplicitRegister) + i.reg_operands--; + if (i.types[1] & ImplicitRegister) + i.reg_operands--; + if (i.types[2] & ImplicitRegister) + i.reg_operands--; - /* Now *l must be either ',' or END_OF_INSN. */ - if (*l == ',') - { - if (*++l == END_OF_INSN) - { - /* Just skip it, if it's \n complain. */ - goto expecting_operand_after_comma; - } - expecting_operand = 1; - } - } - while (*l != END_OF_INSN); - } - } + if (i.tm.opcode_modifier & ImmExt) + { + /* These AMD 3DNow! and Intel Katmai New Instructions have an + opcode suffix which is coded in the same place as an 8-bit + immediate field would be. Here we fake an 8-bit immediate + operand from the opcode suffix stored in tm.extension_opcode. */ - /* Now we've parsed the mnemonic into a set of templates, and have the - operands at hand. + expressionS *exp; - Next, we find a template that matches the given insn, - making sure the overlap of the given operands types is consistent - with the template operand types. */ + assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); -#define MATCH(overlap, given, template) \ - ((overlap & ~JumpAbsolute) \ - && ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute))) + exp = &im_expressions[i.imm_operands++]; + i.op[i.operands].imms = exp; + i.types[i.operands++] = Imm8; + exp->X_op = O_constant; + exp->X_add_number = i.tm.extension_opcode; + i.tm.extension_opcode = None; + } - /* If given types r0 and r1 are registers they must be of the same type - unless the expected operand type register overlap is null. - Note that Acc in a template matches every size of reg. */ -#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ - ( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \ - ((g0) & Reg) == ((g1) & Reg) || \ - ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) + /* For insns with operands there are more diddles to do to the opcode. */ + if (i.operands) + { + if (!process_operands ()) + return; + } + else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) + { + /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ + as_warn (_("translating to `%sp'"), i.tm.name); + } - { - register unsigned int overlap0, overlap1; - unsigned int overlap2; - unsigned int found_reverse_match; - int suffix_check; - - /* All intel opcodes have reversed operands except for "bound" and - "enter". We also don't reverse intersegment "jmp" and "call" - instructions with 2 immediate operands so that the immediate segment - precedes the offset, as it does when in AT&T mode. "enter" and the - intersegment "jmp" and "call" instructions are the only ones that - have two immediate operands. */ - if (intel_syntax && i.operands > 1 - && (strcmp (mnemonic, "bound") != 0) - && !((i.types[0] & Imm) && (i.types[1] & Imm))) + /* Handle conversion of 'int $3' --> special int3 insn. */ + if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) + { + i.tm.base_opcode = INT3_OPCODE; + i.imm_operands = 0; + } + + if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) + && i.op[0].disps->X_op == O_constant) + { + /* Convert "jmp constant" (and "call constant") to a jump (call) to + the absolute address given by the constant. Since ix86 jumps and + calls are pc relative, we need to generate a reloc. */ + i.op[0].disps->X_add_symbol = &abs_symbol; + i.op[0].disps->X_op = O_symbol; + } + + if ((i.tm.opcode_modifier & Rex64) != 0) + i.rex |= REX_MODE64; + + /* For 8 bit registers we need an empty rex prefix. Also if the + instruction already has a prefix, we need to convert old + registers to new ones. */ + + if (((i.types[0] & Reg8) != 0 + && (i.op[0].regs->reg_flags & RegRex64) != 0) + || ((i.types[1] & Reg8) != 0 + && (i.op[1].regs->reg_flags & RegRex64) != 0) + || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0) + && i.rex != 0)) + { + int x; + + i.rex |= REX_OPCODE; + for (x = 0; x < 2; x++) + { + /* Look for 8 bit operand that uses old registers. */ + if ((i.types[x] & Reg8) != 0 + && (i.op[x].regs->reg_flags & RegRex64) == 0) + { + /* In case it is "hi" register, give up. */ + if (i.op[x].regs->reg_num > 3) + as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"), + i.op[x].regs->reg_name); + + /* Otherwise it is equivalent to the extended register. + Since the encoding doesn't change this is merely + cosmetic cleanup for debug output. */ + + i.op[x].regs = i.op[x].regs + 8; + } + } + } + + if (i.rex != 0) + add_prefix (REX_OPCODE | i.rex); + + /* We are ready to output the insn. */ + output_insn (); +} + +static char * +parse_insn (line, mnemonic) + char *line; + char *mnemonic; +{ + char *l = line; + char *token_start = l; + char *mnem_p; + + /* Non-zero if we found a prefix only acceptable with string insns. */ + const char *expecting_string_instruction = NULL; + + while (1) + { + mnem_p = mnemonic; + while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) + { + mnem_p++; + if (mnem_p >= mnemonic + MAX_MNEM_SIZE) + { + as_bad (_("no such instruction: `%s'"), token_start); + return NULL; + } + l++; + } + if (!is_space_char (*l) + && *l != END_OF_INSN + && *l != PREFIX_SEPARATOR + && *l != ',') + { + as_bad (_("invalid character %s in mnemonic"), + output_invalid (*l)); + return NULL; + } + if (token_start == l) + { + if (*l == PREFIX_SEPARATOR) + as_bad (_("expecting prefix; got nothing")); + else + as_bad (_("expecting mnemonic; got nothing")); + return NULL; + } + + /* Look up instruction (or prefix) via hash table. */ + current_templates = hash_find (op_hash, mnemonic); + + if (*l != END_OF_INSN + && (!is_space_char (*l) || l[1] != END_OF_INSN) + && current_templates + && (current_templates->start->opcode_modifier & IsPrefix)) + { + /* If we are in 16-bit mode, do not allow addr16 or data16. + Similarly, in 32-bit mode, do not allow addr32 or data32. */ + if ((current_templates->start->opcode_modifier & (Size16 | Size32)) + && flag_code != CODE_64BIT + && (((current_templates->start->opcode_modifier & Size32) != 0) + ^ (flag_code == CODE_16BIT))) + { + as_bad (_("redundant %s prefix"), + current_templates->start->name); + return NULL; + } + /* Add prefix, checking for repeated prefixes. */ + switch (add_prefix (current_templates->start->base_opcode)) + { + case 0: + return NULL; + case 2: + expecting_string_instruction = current_templates->start->name; + break; + } + /* Skip past PREFIX_SEPARATOR and reset token_start. */ + token_start = ++l; + } + else + break; + } + + if (!current_templates) + { + /* See if we can get a match by trimming off a suffix. */ + switch (mnem_p[-1]) + { + case WORD_MNEM_SUFFIX: + case BYTE_MNEM_SUFFIX: + case QWORD_MNEM_SUFFIX: + i.suffix = mnem_p[-1]; + mnem_p[-1] = '\0'; + current_templates = hash_find (op_hash, mnemonic); + break; + case SHORT_MNEM_SUFFIX: + case LONG_MNEM_SUFFIX: + if (!intel_syntax) + { + i.suffix = mnem_p[-1]; + mnem_p[-1] = '\0'; + current_templates = hash_find (op_hash, mnemonic); + } + break; + + /* Intel Syntax. */ + case 'd': + if (intel_syntax) + { + if (intel_float_operand (mnemonic)) + i.suffix = SHORT_MNEM_SUFFIX; + else + i.suffix = LONG_MNEM_SUFFIX; + mnem_p[-1] = '\0'; + current_templates = hash_find (op_hash, mnemonic); + } + break; + } + if (!current_templates) + { + as_bad (_("no such instruction: `%s'"), token_start); + return NULL; + } + } + + if (current_templates->start->opcode_modifier & (Jump | JumpByte)) + { + /* Check for a branch hint. We allow ",pt" and ",pn" for + predict taken and predict not taken respectively. + I'm not sure that branch hints actually do anything on loop + and jcxz insns (JumpByte) for current Pentium4 chips. They + may work in the future and it doesn't hurt to accept them + now. */ + if (l[0] == ',' && l[1] == 'p') + { + if (l[2] == 't') + { + if (!add_prefix (DS_PREFIX_OPCODE)) + return NULL; + l += 3; + } + else if (l[2] == 'n') + { + if (!add_prefix (CS_PREFIX_OPCODE)) + return NULL; + l += 3; + } + } + } + /* Any other comma loses. */ + if (*l == ',') + { + as_bad (_("invalid character %s in mnemonic"), + output_invalid (*l)); + return NULL; + } + + /* Check if instruction is supported on specified architecture. */ + if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64)) + & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64))) + { + as_warn (_("`%s' is not supported on `%s'"), + current_templates->start->name, cpu_arch_name); + } + else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) + { + as_warn (_("use .code16 to ensure correct addressing mode")); + } + + /* Check for rep/repne without a string instruction. */ + if (expecting_string_instruction + && !(current_templates->start->opcode_modifier & IsString)) + { + as_bad (_("expecting string instruction after `%s'"), + expecting_string_instruction); + return NULL; + } + + return l; +} + +static char * +parse_operands (l, mnemonic) + char *l; + const char *mnemonic; +{ + char *token_start; + + /* 1 if operand is pending after ','. */ + unsigned int expecting_operand = 0; + + /* Non-zero if operand parens not balanced. */ + unsigned int paren_not_balanced; + + while (*l != END_OF_INSN) + { + /* Skip optional white space before operand. */ + if (is_space_char (*l)) + ++l; + if (!is_operand_char (*l) && *l != END_OF_INSN) + { + as_bad (_("invalid character %s before operand %d"), + output_invalid (*l), + i.operands + 1); + return NULL; + } + token_start = l; /* after white space */ + paren_not_balanced = 0; + while (paren_not_balanced || *l != ',') + { + if (*l == END_OF_INSN) + { + if (paren_not_balanced) + { + if (!intel_syntax) + as_bad (_("unbalanced parenthesis in operand %d."), + i.operands + 1); + else + as_bad (_("unbalanced brackets in operand %d."), + i.operands + 1); + return NULL; + } + else + break; /* we are done */ + } + else if (!is_operand_char (*l) && !is_space_char (*l)) + { + as_bad (_("invalid character %s in operand %d"), + output_invalid (*l), + i.operands + 1); + return NULL; + } + if (!intel_syntax) + { + if (*l == '(') + ++paren_not_balanced; + if (*l == ')') + --paren_not_balanced; + } + else + { + if (*l == '[') + ++paren_not_balanced; + if (*l == ']') + --paren_not_balanced; + } + l++; + } + if (l != token_start) + { /* Yes, we've read in another operand. */ + unsigned int operand_ok; + this_operand = i.operands++; + if (i.operands > MAX_OPERANDS) + { + as_bad (_("spurious operands; (%d operands/instruction max)"), + MAX_OPERANDS); + return NULL; + } + /* Now parse operand adding info to 'i' as we go along. */ + END_STRING_AND_SAVE (l); + + if (intel_syntax) + operand_ok = + i386_intel_operand (token_start, + intel_float_operand (mnemonic)); + else + operand_ok = i386_operand (token_start); + + RESTORE_END_STRING (l); + if (!operand_ok) + return NULL; + } + else + { + if (expecting_operand) + { + expecting_operand_after_comma: + as_bad (_("expecting operand after ','; got nothing")); + return NULL; + } + if (*l == ',') + { + as_bad (_("expecting operand before ','; got nothing")); + return NULL; + } + } + + /* Now *l must be either ',' or END_OF_INSN. */ + if (*l == ',') + { + if (*++l == END_OF_INSN) + { + /* Just skip it, if it's \n complain. */ + goto expecting_operand_after_comma; + } + expecting_operand = 1; + } + } + return l; +} + +static void +swap_operands () +{ + union i386_op temp_op; + unsigned int temp_type; + RELOC_ENUM temp_reloc; + int xchg1 = 0; + int xchg2 = 0; + + if (i.operands == 2) + { + xchg1 = 0; + xchg2 = 1; + } + else if (i.operands == 3) + { + xchg1 = 0; + xchg2 = 2; + } + temp_type = i.types[xchg2]; + i.types[xchg2] = i.types[xchg1]; + i.types[xchg1] = temp_type; + temp_op = i.op[xchg2]; + i.op[xchg2] = i.op[xchg1]; + i.op[xchg1] = temp_op; + temp_reloc = i.reloc[xchg2]; + i.reloc[xchg2] = i.reloc[xchg1]; + i.reloc[xchg1] = temp_reloc; + + if (i.mem_operands == 2) + { + const seg_entry *temp_seg; + temp_seg = i.seg[0]; + i.seg[0] = i.seg[1]; + i.seg[1] = temp_seg; + } +} + +/* Try to ensure constant immediates are represented in the smallest + opcode possible. */ +static void +optimize_imm () +{ + char guess_suffix = 0; + int op; + + if (i.suffix) + guess_suffix = i.suffix; + else if (i.reg_operands) + { + /* Figure out a suffix from the last register operand specified. + We can't do this properly yet, ie. excluding InOutPortReg, + but the following works for instructions with immediates. + In any case, we can't set i.suffix yet. */ + for (op = i.operands; --op >= 0;) + if (i.types[op] & Reg) + { + if (i.types[op] & Reg8) + guess_suffix = BYTE_MNEM_SUFFIX; + else if (i.types[op] & Reg16) + guess_suffix = WORD_MNEM_SUFFIX; + else if (i.types[op] & Reg32) + guess_suffix = LONG_MNEM_SUFFIX; + else if (i.types[op] & Reg64) + guess_suffix = QWORD_MNEM_SUFFIX; + break; + } + } + else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) + guess_suffix = WORD_MNEM_SUFFIX; + + for (op = i.operands; --op >= 0;) + if (i.types[op] & Imm) { - union i386_op temp_op; - unsigned int temp_type; -#ifdef BFD_ASSEMBLER - enum bfd_reloc_code_real temp_disp_reloc; -#else - int temp_disp_reloc; -#endif - int xchg1 = 0; - int xchg2 = 0; + switch (i.op[op].imms->X_op) + { + case O_constant: + /* If a suffix is given, this operand may be shortened. */ + switch (guess_suffix) + { + case LONG_MNEM_SUFFIX: + i.types[op] |= Imm32 | Imm64; + break; + case WORD_MNEM_SUFFIX: + i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64; + break; + case BYTE_MNEM_SUFFIX: + i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64; + break; + } + + /* If this operand is at most 16 bits, convert it + to a signed 16 bit number before trying to see + whether it will fit in an even smaller size. + This allows a 16-bit operand such as $0xffe0 to + be recognised as within Imm8S range. */ + if ((i.types[op] & Imm16) + && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) + { + i.op[op].imms->X_add_number = + (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); + } + if ((i.types[op] & Imm32) + && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) + == 0)) + { + i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number + ^ ((offsetT) 1 << 31)) + - ((offsetT) 1 << 31)); + } + i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); + + /* We must avoid matching of Imm32 templates when 64bit + only immediate is available. */ + if (guess_suffix == QWORD_MNEM_SUFFIX) + i.types[op] &= ~Imm32; + break; + + case O_absent: + case O_register: + abort (); + + /* Symbols and expressions. */ + default: + /* Convert symbolic operand to proper sizes for matching. */ + switch (guess_suffix) + { + case QWORD_MNEM_SUFFIX: + i.types[op] = Imm64 | Imm32S; + break; + case LONG_MNEM_SUFFIX: + i.types[op] = Imm32 | Imm64; + break; + case WORD_MNEM_SUFFIX: + i.types[op] = Imm16 | Imm32 | Imm64; + break; + break; + case BYTE_MNEM_SUFFIX: + i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32; + break; + break; + } + break; + } + } +} - if (i.operands == 2) +/* Try to use the smallest displacement type too. */ +static void +optimize_disp () +{ + int op; + + for (op = i.operands; --op >= 0;) + if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant) + { + offsetT disp = i.op[op].disps->X_add_number; + + if (i.types[op] & Disp16) { - xchg1 = 0; - xchg2 = 1; + /* We know this operand is at most 16 bits, so + convert to a signed 16 bit number before trying + to see whether it will fit in an even smaller + size. */ + + disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); } - else if (i.operands == 3) + else if (i.types[op] & Disp32) { - xchg1 = 0; - xchg2 = 2; + /* We know this operand is at most 32 bits, so convert to a + signed 32 bit number before trying to see whether it will + fit in an even smaller size. */ + disp &= (((offsetT) 2 << 31) - 1); + disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); } - temp_type = i.types[xchg2]; - i.types[xchg2] = i.types[xchg1]; - i.types[xchg1] = temp_type; - temp_op = i.op[xchg2]; - i.op[xchg2] = i.op[xchg1]; - i.op[xchg1] = temp_op; - temp_disp_reloc = i.disp_reloc[xchg2]; - i.disp_reloc[xchg2] = i.disp_reloc[xchg1]; - i.disp_reloc[xchg1] = temp_disp_reloc; - - if (i.mem_operands == 2) + if (flag_code == CODE_64BIT) { - const seg_entry *temp_seg; - temp_seg = i.seg[0]; - i.seg[0] = i.seg[1]; - i.seg[1] = temp_seg; + if (fits_in_signed_long (disp)) + i.types[op] |= Disp32S; + if (fits_in_unsigned_long (disp)) + i.types[op] |= Disp32; } + if ((i.types[op] & (Disp32 | Disp32S | Disp16)) + && fits_in_signed_byte (disp)) + i.types[op] |= Disp8; } +} + +static int +match_template () +{ + /* Points to template once we've found it. */ + const template *t; + unsigned int overlap0, overlap1, overlap2; + unsigned int found_reverse_match; + int suffix_check; + +#define MATCH(overlap, given, template) \ + ((overlap & ~JumpAbsolute) \ + && (((given) & (BaseIndex | JumpAbsolute)) \ + == ((overlap) & (BaseIndex | JumpAbsolute)))) + + /* If given types r0 and r1 are registers they must be of the same type + unless the expected operand type register overlap is null. + Note that Acc in a template matches every size of reg. */ +#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \ + (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \ + || ((g0) & Reg) == ((g1) & Reg) \ + || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 ) + + overlap0 = 0; + overlap1 = 0; + overlap2 = 0; + found_reverse_match = 0; + suffix_check = (i.suffix == BYTE_MNEM_SUFFIX + ? No_bSuf + : (i.suffix == WORD_MNEM_SUFFIX + ? No_wSuf + : (i.suffix == SHORT_MNEM_SUFFIX + ? No_sSuf + : (i.suffix == LONG_MNEM_SUFFIX + ? No_lSuf + : (i.suffix == QWORD_MNEM_SUFFIX + ? No_qSuf + : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX + ? No_xSuf : 0)))))); + + for (t = current_templates->start; + t < current_templates->end; + t++) + { + /* Must have right number of operands. */ + if (i.operands != t->operands) + continue; + + /* Check the suffix, except for some instructions in intel mode. */ + if ((t->opcode_modifier & suffix_check) + && !(intel_syntax + && (t->opcode_modifier & IgnoreSize)) + && !(intel_syntax + && t->base_opcode == 0xd9 + && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ + || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ + continue; + + /* Do not verify operands when there are none. */ + else if (!t->operands) + { + if (t->cpu_flags & ~cpu_arch_flags) + continue; + /* We've found a match; break out of loop. */ + break; + } + + overlap0 = i.types[0] & t->operand_types[0]; + switch (t->operands) + { + case 1: + if (!MATCH (overlap0, i.types[0], t->operand_types[0])) + continue; + break; + case 2: + case 3: + overlap1 = i.types[1] & t->operand_types[1]; + if (!MATCH (overlap0, i.types[0], t->operand_types[0]) + || !MATCH (overlap1, i.types[1], t->operand_types[1]) + || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], + t->operand_types[0], + overlap1, i.types[1], + t->operand_types[1])) + { + /* Check if other direction is valid ... */ + if ((t->opcode_modifier & (D | FloatD)) == 0) + continue; + + /* Try reversing direction of operands. */ + overlap0 = i.types[0] & t->operand_types[1]; + overlap1 = i.types[1] & t->operand_types[0]; + if (!MATCH (overlap0, i.types[0], t->operand_types[1]) + || !MATCH (overlap1, i.types[1], t->operand_types[0]) + || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], + t->operand_types[1], + overlap1, i.types[1], + t->operand_types[0])) + { + /* Does not match either direction. */ + continue; + } + /* found_reverse_match holds which of D or FloatDR + we've found. */ + found_reverse_match = t->opcode_modifier & (D | FloatDR); + } + /* Found a forward 2 operand match here. */ + else if (t->operands == 3) + { + /* Here we make use of the fact that there are no + reverse match 3 operand instructions, and all 3 + operand instructions only need to be checked for + register consistency between operands 2 and 3. */ + overlap2 = i.types[2] & t->operand_types[2]; + if (!MATCH (overlap2, i.types[2], t->operand_types[2]) + || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], + t->operand_types[1], + overlap2, i.types[2], + t->operand_types[2])) + + continue; + } + /* Found either forward/reverse 2 or 3 operand match here: + slip through to break. */ + } + if (t->cpu_flags & ~cpu_arch_flags) + { + found_reverse_match = 0; + continue; + } + /* We've found a match; break out of loop. */ + break; + } + + if (t == current_templates->end) + { + /* We found no match. */ + as_bad (_("suffix or operands invalid for `%s'"), + current_templates->start->name); + return 0; + } + + if (!quiet_warnings) + { + if (!intel_syntax + && ((i.types[0] & JumpAbsolute) + != (t->operand_types[0] & JumpAbsolute))) + { + as_warn (_("indirect %s without `*'"), t->name); + } + + if ((t->opcode_modifier & (IsPrefix | IgnoreSize)) + == (IsPrefix | IgnoreSize)) + { + /* Warn them that a data or address size prefix doesn't + affect assembly of the next line of code. */ + as_warn (_("stand-alone `%s' prefix"), t->name); + } + } + + /* Copy the template we found. */ + i.tm = *t; + if (found_reverse_match) + { + /* If we found a reverse match we must alter the opcode + direction bit. found_reverse_match holds bits to change + (different for int & float insns). */ + + i.tm.base_opcode ^= found_reverse_match; + + i.tm.operand_types[0] = t->operand_types[1]; + i.tm.operand_types[1] = t->operand_types[0]; + } + + return 1; +} + +static int +check_string () +{ + int mem_op = (i.types[0] & AnyMem) ? 0 : 1; + if ((i.tm.operand_types[mem_op] & EsSeg) != 0) + { + if (i.seg[0] != NULL && i.seg[0] != &es) + { + as_bad (_("`%s' operand %d must use `%%es' segment"), + i.tm.name, + mem_op + 1); + return 0; + } + /* There's only ever one segment override allowed per instruction. + This instruction possibly has a legal segment override on the + second operand, so copy the segment to where non-string + instructions store it, allowing common code. */ + i.seg[0] = i.seg[1]; + } + else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) + { + if (i.seg[1] != NULL && i.seg[1] != &es) + { + as_bad (_("`%s' operand %d must use `%%es' segment"), + i.tm.name, + mem_op + 2); + return 0; + } + } + return 1; +} + +static int +process_suffix () +{ + /* If matched instruction specifies an explicit instruction mnemonic + suffix, use it. */ + if (i.tm.opcode_modifier & (Size16 | Size32 | Size64)) + { + if (i.tm.opcode_modifier & Size16) + i.suffix = WORD_MNEM_SUFFIX; + else if (i.tm.opcode_modifier & Size64) + i.suffix = QWORD_MNEM_SUFFIX; + else + i.suffix = LONG_MNEM_SUFFIX; + } + else if (i.reg_operands) + { + /* If there's no instruction mnemonic suffix we try to invent one + based on register operands. */ + if (!i.suffix) + { + /* We take i.suffix from the last register operand specified, + Destination register type is more significant than source + register type. */ + int op; + for (op = i.operands; --op >= 0;) + if ((i.types[op] & Reg) + && !(i.tm.operand_types[op] & InOutPortReg)) + { + i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : + (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : + (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX : + LONG_MNEM_SUFFIX); + break; + } + } + else if (i.suffix == BYTE_MNEM_SUFFIX) + { + if (!check_byte_reg ()) + return 0; + } + else if (i.suffix == LONG_MNEM_SUFFIX) + { + if (!check_long_reg ()) + return 0; + } + else if (i.suffix == QWORD_MNEM_SUFFIX) + { + if (!check_qword_reg ()) + return 0; + } + else if (i.suffix == WORD_MNEM_SUFFIX) + { + if (!check_word_reg ()) + return 0; + } + else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) + /* Do nothing if the instruction is going to ignore the prefix. */ + ; + else + abort (); + } + else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) + { + i.suffix = stackop_size; + } + + /* Change the opcode based on the operand size given by i.suffix; + We need not change things for byte insns. */ + + if (!i.suffix && (i.tm.opcode_modifier & W)) + { + as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); + return 0; + } + + /* For movzx and movsx, need to check the register type. */ + if (intel_syntax + && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe) + && i.suffix == BYTE_MNEM_SUFFIX) + { + unsigned int prefix = DATA_PREFIX_OPCODE; + + if ((i.op[1].regs->reg_type & Reg16) != 0) + if (!add_prefix (prefix)) + return 0; + } + + if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) + { + /* It's not a byte, select word/dword operation. */ + if (i.tm.opcode_modifier & W) + { + if (i.tm.opcode_modifier & ShortForm) + i.tm.base_opcode |= 8; + else + i.tm.base_opcode |= 1; + } + + /* Now select between word & dword operations via the operand + size prefix, except for instructions that will ignore this + prefix anyway. */ + if (i.suffix != QWORD_MNEM_SUFFIX + && (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT) + && !(i.tm.opcode_modifier & IgnoreSize)) + { + unsigned int prefix = DATA_PREFIX_OPCODE; + if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ + prefix = ADDR_PREFIX_OPCODE; + + if (!add_prefix (prefix)) + return 0; + } + + if (i.suffix != QWORD_MNEM_SUFFIX && (flag_code == CODE_64BIT) + && !(i.tm.opcode_modifier & IgnoreSize) + && (i.tm.opcode_modifier & JumpByte)) + { + if (!add_prefix (ADDR_PREFIX_OPCODE)) + return 0; + } + + /* Set mode64 for an operand. */ + if (i.suffix == QWORD_MNEM_SUFFIX + && (i.tm.opcode_modifier & NoRex64) == 0) + { + i.rex |= REX_MODE64; + if (flag_code < CODE_64BIT) + { + as_bad (_("64bit operations available only in 64bit modes.")); + return 0; + } + } + + /* Size floating point instruction. */ + if (i.suffix == LONG_MNEM_SUFFIX) + { + if (i.tm.opcode_modifier & FloatMF) + i.tm.base_opcode ^= 4; + } + } + + return 1; +} + +static int +check_byte_reg () +{ + int op; + for (op = i.operands; --op >= 0;) + { + /* If this is an eight bit register, it's OK. If it's the 16 or + 32 bit version of an eight bit register, we will just use the + low portion, and that's OK too. */ + if (i.types[op] & Reg8) + continue; + + /* movzx and movsx should not generate this warning. */ + if (intel_syntax + && (i.tm.base_opcode == 0xfb7 + || i.tm.base_opcode == 0xfb6 + || i.tm.base_opcode == 0x63 + || i.tm.base_opcode == 0xfbe + || i.tm.base_opcode == 0xfbf)) + continue; + + if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 +#if 0 + /* Check that the template allows eight bit regs. This + kills insns such as `orb $1,%edx', which maybe should be + allowed. */ + && (i.tm.operand_types[op] & (Reg8 | InOutPortReg)) +#endif + ) + { + /* Prohibit these changes in the 64bit mode, since the + lowering is more complicated. */ + if (flag_code == CODE_64BIT + && (i.tm.operand_types[op] & InOutPortReg) == 0) + { + as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), + i.op[op].regs->reg_name, + i.suffix); + return 0; + } +#if REGISTER_WARNINGS + if (!quiet_warnings + && (i.tm.operand_types[op] & InOutPortReg) == 0) + as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), + (i.op[op].regs + (i.types[op] & Reg16 + ? REGNAM_AL - REGNAM_AX + : REGNAM_AL - REGNAM_EAX))->reg_name, + i.op[op].regs->reg_name, + i.suffix); +#endif + continue; + } + /* Any other register is bad. */ + if (i.types[op] & (Reg | RegMMX | RegXMM + | SReg2 | SReg3 + | Control | Debug | Test + | FloatReg | FloatAcc)) + { + as_bad (_("`%%%s' not allowed with `%s%c'"), + i.op[op].regs->reg_name, + i.tm.name, + i.suffix); + return 0; + } + } + return 1; +} + +static int +check_long_reg () +{ + int op; - if (i.imm_operands) + for (op = i.operands; --op >= 0;) + /* Reject eight bit registers, except where the template requires + them. (eg. movzb) */ + if ((i.types[op] & Reg8) != 0 + && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) { - /* Try to ensure constant immediates are represented in the smallest - opcode possible. */ - char guess_suffix = 0; - int op; - - if (i.suffix) - guess_suffix = i.suffix; - else if (i.reg_operands) + as_bad (_("`%%%s' not allowed with `%s%c'"), + i.op[op].regs->reg_name, + i.tm.name, + i.suffix); + return 0; + } + /* Warn if the e prefix on a general reg is missing. */ + else if ((!quiet_warnings || flag_code == CODE_64BIT) + && (i.types[op] & Reg16) != 0 + && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) + { + /* Prohibit these changes in the 64bit mode, since the + lowering is more complicated. */ + if (flag_code == CODE_64BIT) { - /* Figure out a suffix from the last register operand specified. - We can't do this properly yet, ie. excluding InOutPortReg, - but the following works for instructions with immediates. - In any case, we can't set i.suffix yet. */ - for (op = i.operands; --op >= 0;) - if (i.types[op] & Reg) - { - if (i.types[op] & Reg8) - guess_suffix = BYTE_MNEM_SUFFIX; - else if (i.types[op] & Reg16) - guess_suffix = WORD_MNEM_SUFFIX; - break; - } + as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), + i.op[op].regs->reg_name, + i.suffix); + return 0; } - else if (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) - guess_suffix = WORD_MNEM_SUFFIX; - - for (op = i.operands; --op >= 0;) - if ((i.types[op] & Imm) - && i.op[op].imms->X_op == O_constant) - { - /* If a suffix is given, this operand may be shortened. */ - switch (guess_suffix) - { - case WORD_MNEM_SUFFIX: - i.types[op] |= Imm16; - break; - case BYTE_MNEM_SUFFIX: - i.types[op] |= Imm16 | Imm8 | Imm8S; - break; - } - - /* If this operand is at most 16 bits, convert it to a - signed 16 bit number before trying to see whether it will - fit in an even smaller size. This allows a 16-bit operand - such as $0xffe0 to be recognised as within Imm8S range. */ - if ((i.types[op] & Imm16) - && (i.op[op].imms->X_add_number & ~(offsetT)0xffff) == 0) - { - i.op[op].imms->X_add_number = - (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); - } - i.types[op] |= smallest_imm_type ((long) i.op[op].imms->X_add_number); - } +#if REGISTER_WARNINGS + else + as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), + (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name, + i.op[op].regs->reg_name, + i.suffix); +#endif } - - if (i.disp_operands) + /* Warn if the r prefix on a general reg is missing. */ + else if ((i.types[op] & Reg64) != 0 + && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) { - /* Try to use the smallest displacement type too. */ - int op; - - for (op = i.operands; --op >= 0;) - if ((i.types[op] & Disp) - && i.op[op].imms->X_op == O_constant) - { - offsetT disp = i.op[op].disps->X_add_number; - - if (i.types[op] & Disp16) - { - /* We know this operand is at most 16 bits, so - convert to a signed 16 bit number before trying - to see whether it will fit in an even smaller - size. */ - - disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); - } - if (fits_in_signed_byte (disp)) - i.types[op] |= Disp8; - } + as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), + i.op[op].regs->reg_name, + i.suffix); + return 0; } + return 1; +} - overlap0 = 0; - overlap1 = 0; - overlap2 = 0; - found_reverse_match = 0; - suffix_check = (i.suffix == BYTE_MNEM_SUFFIX - ? No_bSuf - : (i.suffix == WORD_MNEM_SUFFIX - ? No_wSuf - : (i.suffix == SHORT_MNEM_SUFFIX - ? No_sSuf - : (i.suffix == LONG_MNEM_SUFFIX - ? No_lSuf - : (i.suffix == DWORD_MNEM_SUFFIX - ? No_dSuf - : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0)))))); - - for (t = current_templates->start; - t < current_templates->end; - t++) - { - /* Must have right number of operands. */ - if (i.operands != t->operands) - continue; - - /* Check the suffix, except for some instructions in intel mode. */ - if ((t->opcode_modifier & suffix_check) - && !(intel_syntax - && (t->opcode_modifier & IgnoreSize)) - && !(intel_syntax - && t->base_opcode == 0xd9 - && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */ - || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */ - continue; - - else if (!t->operands) - /* 0 operands always matches. */ - break; - - overlap0 = i.types[0] & t->operand_types[0]; - switch (t->operands) - { - case 1: - if (!MATCH (overlap0, i.types[0], t->operand_types[0])) - continue; - break; - case 2: - case 3: - overlap1 = i.types[1] & t->operand_types[1]; - if (!MATCH (overlap0, i.types[0], t->operand_types[0]) - || !MATCH (overlap1, i.types[1], t->operand_types[1]) - || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], - t->operand_types[0], - overlap1, i.types[1], - t->operand_types[1])) - { - /* Check if other direction is valid ... */ - if ((t->opcode_modifier & (D|FloatD)) == 0) - continue; - - /* Try reversing direction of operands. */ - overlap0 = i.types[0] & t->operand_types[1]; - overlap1 = i.types[1] & t->operand_types[0]; - if (!MATCH (overlap0, i.types[0], t->operand_types[1]) - || !MATCH (overlap1, i.types[1], t->operand_types[0]) - || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0], - t->operand_types[1], - overlap1, i.types[1], - t->operand_types[0])) - { - /* Does not match either direction. */ - continue; - } - /* found_reverse_match holds which of D or FloatDR - we've found. */ - found_reverse_match = t->opcode_modifier & (D|FloatDR); - break; - } - /* Found a forward 2 operand match here. */ - if (t->operands == 3) - { - /* Here we make use of the fact that there are no - reverse match 3 operand instructions, and all 3 - operand instructions only need to be checked for - register consistency between operands 2 and 3. */ - overlap2 = i.types[2] & t->operand_types[2]; - if (!MATCH (overlap2, i.types[2], t->operand_types[2]) - || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1], - t->operand_types[1], - overlap2, i.types[2], - t->operand_types[2])) +static int +check_qword_reg () +{ + int op; - continue; - } - /* Found either forward/reverse 2 or 3 operand match here: - slip through to break. */ - } - /* We've found a match; break out of loop. */ - break; + for (op = i.operands; --op >= 0; ) + /* Reject eight bit registers, except where the template requires + them. (eg. movzb) */ + if ((i.types[op] & Reg8) != 0 + && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) + { + as_bad (_("`%%%s' not allowed with `%s%c'"), + i.op[op].regs->reg_name, + i.tm.name, + i.suffix); + return 0; } - if (t == current_templates->end) + /* Warn if the e prefix on a general reg is missing. */ + else if (((i.types[op] & Reg16) != 0 + || (i.types[op] & Reg32) != 0) + && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0) { - /* We found no match. */ - as_bad (_("suffix or operands invalid for `%s'"), - current_templates->start->name); - return; + /* Prohibit these changes in the 64bit mode, since the + lowering is more complicated. */ + as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), + i.op[op].regs->reg_name, + i.suffix); + return 0; } + return 1; +} - if (!quiet_warnings) +static int +check_word_reg () +{ + int op; + for (op = i.operands; --op >= 0;) + /* Reject eight bit registers, except where the template requires + them. (eg. movzb) */ + if ((i.types[op] & Reg8) != 0 + && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) { - if (!intel_syntax - && ((i.types[0] & JumpAbsolute) - != (t->operand_types[0] & JumpAbsolute))) - { - as_warn (_("indirect %s without `*'"), t->name); - } - - if ((t->opcode_modifier & (IsPrefix|IgnoreSize)) - == (IsPrefix|IgnoreSize)) + as_bad (_("`%%%s' not allowed with `%s%c'"), + i.op[op].regs->reg_name, + i.tm.name, + i.suffix); + return 0; + } + /* Warn if the e prefix on a general reg is present. */ + else if ((!quiet_warnings || flag_code == CODE_64BIT) + && (i.types[op] & Reg32) != 0 + && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0) + { + /* Prohibit these changes in the 64bit mode, since the + lowering is more complicated. */ + if (flag_code == CODE_64BIT) { - /* Warn them that a data or address size prefix doesn't - affect assembly of the next line of code. */ - as_warn (_("stand-alone `%s' prefix"), t->name); + as_bad (_("Incorrect register `%%%s' used with `%c' suffix"), + i.op[op].regs->reg_name, + i.suffix); + return 0; } + else +#if REGISTER_WARNINGS + as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), + (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name, + i.op[op].regs->reg_name, + i.suffix); +#endif } + return 1; +} - /* Copy the template we found. */ - i.tm = *t; - if (found_reverse_match) - { - /* If we found a reverse match we must alter the opcode - direction bit. found_reverse_match holds bits to change - (different for int & float insns). */ +static int +finalize_imm () +{ + unsigned int overlap0, overlap1, overlap2; - i.tm.base_opcode ^= found_reverse_match; + overlap0 = i.types[0] & i.tm.operand_types[0]; + if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S)) + && overlap0 != Imm8 && overlap0 != Imm8S + && overlap0 != Imm16 && overlap0 != Imm32S + && overlap0 != Imm32 && overlap0 != Imm64) + { + if (i.suffix) + { + overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX + ? Imm8 | Imm8S + : (i.suffix == WORD_MNEM_SUFFIX + ? Imm16 + : (i.suffix == QWORD_MNEM_SUFFIX + ? Imm64 | Imm32S + : Imm32))); + } + else if (overlap0 == (Imm16 | Imm32S | Imm32) + || overlap0 == (Imm16 | Imm32) + || overlap0 == (Imm16 | Imm32S)) + { + overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) + ? Imm16 : Imm32S); + } + if (overlap0 != Imm8 && overlap0 != Imm8S + && overlap0 != Imm16 && overlap0 != Imm32S + && overlap0 != Imm32 && overlap0 != Imm64) + { + as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); + return 0; + } + } + i.types[0] = overlap0; - i.tm.operand_types[0] = t->operand_types[1]; - i.tm.operand_types[1] = t->operand_types[0]; - } + overlap1 = i.types[1] & i.tm.operand_types[1]; + if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32)) + && overlap1 != Imm8 && overlap1 != Imm8S + && overlap1 != Imm16 && overlap1 != Imm32S + && overlap1 != Imm32 && overlap1 != Imm64) + { + if (i.suffix) + { + overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX + ? Imm8 | Imm8S + : (i.suffix == WORD_MNEM_SUFFIX + ? Imm16 + : (i.suffix == QWORD_MNEM_SUFFIX + ? Imm64 | Imm32S + : Imm32))); + } + else if (overlap1 == (Imm16 | Imm32 | Imm32S) + || overlap1 == (Imm16 | Imm32) + || overlap1 == (Imm16 | Imm32S)) + { + overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0) + ? Imm16 : Imm32S); + } + if (overlap1 != Imm8 && overlap1 != Imm8S + && overlap1 != Imm16 && overlap1 != Imm32S + && overlap1 != Imm32 && overlap1 != Imm64) + { + as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix); + return 0; + } + } + i.types[1] = overlap1; - /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ - if (SYSV386_COMPAT - && intel_syntax - && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) - i.tm.base_opcode ^= FloatR; + overlap2 = i.types[2] & i.tm.operand_types[2]; + assert ((overlap2 & Imm) == 0); + i.types[2] = overlap2; - if (i.tm.opcode_modifier & FWait) - if (! add_prefix (FWAIT_OPCODE)) - return; + return 1; +} - /* Check string instruction segment overrides. */ - if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0) - { - int mem_op = (i.types[0] & AnyMem) ? 0 : 1; - if ((i.tm.operand_types[mem_op] & EsSeg) != 0) - { - if (i.seg[0] != NULL && i.seg[0] != &es) - { - as_bad (_("`%s' operand %d must use `%%es' segment"), - i.tm.name, - mem_op + 1); - return; - } - /* There's only ever one segment override allowed per instruction. - This instruction possibly has a legal segment override on the - second operand, so copy the segment to where non-string - instructions store it, allowing common code. */ - i.seg[0] = i.seg[1]; - } - else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0) - { - if (i.seg[1] != NULL && i.seg[1] != &es) - { - as_bad (_("`%s' operand %d must use `%%es' segment"), - i.tm.name, - mem_op + 2); - return; - } - } - } +static int +process_operands () +{ + /* Default segment register this instruction will use for memory + accesses. 0 means unknown. This is only for optimizing out + unnecessary segment overrides. */ + const seg_entry *default_seg = 0; + + /* The imul $imm, %reg instruction is converted into + imul $imm, %reg, %reg, and the clr %reg instruction + is converted into xor %reg, %reg. */ + if (i.tm.opcode_modifier & regKludge) + { + unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; + /* Pretend we saw the extra register operand. */ + assert (i.op[first_reg_op + 1].regs == 0); + i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; + i.types[first_reg_op + 1] = i.types[first_reg_op]; + i.reg_operands = 2; + } - /* If matched instruction specifies an explicit instruction mnemonic - suffix, use it. */ - if (i.tm.opcode_modifier & (Size16 | Size32)) - { - if (i.tm.opcode_modifier & Size16) - i.suffix = WORD_MNEM_SUFFIX; - else - i.suffix = LONG_MNEM_SUFFIX; - } - else if (i.reg_operands) - { - /* If there's no instruction mnemonic suffix we try to invent one - based on register operands. */ - if (!i.suffix) - { - /* We take i.suffix from the last register operand specified, - Destination register type is more significant than source - register type. */ - int op; - for (op = i.operands; --op >= 0;) - if ((i.types[op] & Reg) - && !(i.tm.operand_types[op] & InOutPortReg)) - { - i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX : - (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX : - LONG_MNEM_SUFFIX); - break; - } - } - else if (i.suffix == BYTE_MNEM_SUFFIX) - { - int op; - for (op = i.operands; --op >= 0;) - { - /* If this is an eight bit register, it's OK. If it's - the 16 or 32 bit version of an eight bit register, - we will just use the low portion, and that's OK too. */ - if (i.types[op] & Reg8) - continue; + if (i.tm.opcode_modifier & ShortForm) + { + /* The register or float register operand is in operand 0 or 1. */ + unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; + /* Register goes in low 3 bits of opcode. */ + i.tm.base_opcode |= i.op[op].regs->reg_num; + if ((i.op[op].regs->reg_flags & RegRex) != 0) + i.rex |= REX_EXTZ; + if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) + { + /* Warn about some common errors, but press on regardless. + The first case can be generated by gcc (<= 2.8.1). */ + if (i.operands == 2) + { + /* Reversed arguments on faddp, fsubp, etc. */ + as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, + i.op[1].regs->reg_name, + i.op[0].regs->reg_name); + } + else + { + /* Extraneous `l' suffix on fp insn. */ + as_warn (_("translating to `%s %%%s'"), i.tm.name, + i.op[0].regs->reg_name); + } + } + } + else if (i.tm.opcode_modifier & Modrm) + { + /* The opcode is completed (modulo i.tm.extension_opcode which + must be put into the modrm byte). + Now, we make the modrm & index base bytes based on all the + info we've collected. */ - /* movzx and movsx should not generate this warning. */ - if (intel_syntax - && (i.tm.base_opcode == 0xfb7 - || i.tm.base_opcode == 0xfb6 - || i.tm.base_opcode == 0xfbe - || i.tm.base_opcode == 0xfbf)) - continue; + default_seg = build_modrm_byte (); + } + else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) + { + if (i.tm.base_opcode == POP_SEG_SHORT + && i.op[0].regs->reg_num == 1) + { + as_bad (_("you can't `pop %%cs'")); + return 0; + } + i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); + if ((i.op[0].regs->reg_flags & RegRex) != 0) + i.rex |= REX_EXTZ; + } + else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32) + { + default_seg = &ds; + } + else if ((i.tm.opcode_modifier & IsString) != 0) + { + /* For the string instructions that allow a segment override + on one of their operands, the default segment is ds. */ + default_seg = &ds; + } - if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4 -#if 0 - /* Check that the template allows eight bit regs - This kills insns such as `orb $1,%edx', which - maybe should be allowed. */ - && (i.tm.operand_types[op] & (Reg8|InOutPortReg)) -#endif - ) - { -#if REGISTER_WARNINGS - if (!quiet_warnings - && (i.tm.operand_types[op] & InOutPortReg) == 0) - as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), - (i.op[op].regs - (i.types[op] & Reg16 ? 8 : 16))->reg_name, - i.op[op].regs->reg_name, - i.suffix); -#endif - continue; - } - /* Any other register is bad. */ - if (i.types[op] & (Reg | RegMMX | RegXMM - | SReg2 | SReg3 - | Control | Debug | Test - | FloatReg | FloatAcc)) - { - as_bad (_("`%%%s' not allowed with `%s%c'"), - i.op[op].regs->reg_name, - i.tm.name, - i.suffix); - return; - } - } - } - else if (i.suffix == LONG_MNEM_SUFFIX) - { - int op; + /* If a segment was explicitly specified, + and the specified segment is not the default, + use an opcode prefix to select it. + If we never figured out what the default segment is, + then default_seg will be zero at this point, + and the specified segment prefix will always be used. */ + if ((i.seg[0]) && (i.seg[0] != default_seg)) + { + if (!add_prefix (i.seg[0]->seg_prefix)) + return 0; + } + return 1; +} + +static const seg_entry * +build_modrm_byte () +{ + const seg_entry *default_seg = 0; + + /* i.reg_operands MUST be the number of real register operands; + implicit registers do not count. */ + if (i.reg_operands == 2) + { + unsigned int source, dest; + source = ((i.types[0] + & (Reg | RegMMX | RegXMM + | SReg2 | SReg3 + | Control | Debug | Test)) + ? 0 : 1); + dest = source + 1; + + i.rm.mode = 3; + /* One of the register operands will be encoded in the i.tm.reg + field, the other in the combined i.tm.mode and i.tm.regmem + fields. If no form of this instruction supports a memory + destination operand, then we assume the source operand may + sometimes be a memory operand and so we need to store the + destination in the i.rm.reg field. */ + if ((i.tm.operand_types[dest] & AnyMem) == 0) + { + i.rm.reg = i.op[dest].regs->reg_num; + i.rm.regmem = i.op[source].regs->reg_num; + if ((i.op[dest].regs->reg_flags & RegRex) != 0) + i.rex |= REX_EXTX; + if ((i.op[source].regs->reg_flags & RegRex) != 0) + i.rex |= REX_EXTZ; + } + else + { + i.rm.reg = i.op[source].regs->reg_num; + i.rm.regmem = i.op[dest].regs->reg_num; + if ((i.op[dest].regs->reg_flags & RegRex) != 0) + i.rex |= REX_EXTZ; + if ((i.op[source].regs->reg_flags & RegRex) != 0) + i.rex |= REX_EXTX; + } + } + else + { /* If it's not 2 reg operands... */ + if (i.mem_operands) + { + unsigned int fake_zero_displacement = 0; + unsigned int op = ((i.types[0] & AnyMem) + ? 0 + : (i.types[1] & AnyMem) ? 1 : 2); - for (op = i.operands; --op >= 0;) - /* Reject eight bit registers, except where the template - requires them. (eg. movzb) */ - if ((i.types[op] & Reg8) != 0 - && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0) + default_seg = &ds; + + if (i.base_reg == 0) + { + i.rm.mode = 0; + if (!i.disp_operands) + fake_zero_displacement = 1; + if (i.index_reg == 0) { - as_bad (_("`%%%s' not allowed with `%s%c'"), - i.op[op].regs->reg_name, - i.tm.name, - i.suffix); - return; + /* Operand is just */ + if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0) + && (flag_code != CODE_64BIT)) + { + i.rm.regmem = NO_BASE_REGISTER_16; + i.types[op] &= ~Disp; + i.types[op] |= Disp16; + } + else if (flag_code != CODE_64BIT + || (i.prefix[ADDR_PREFIX] != 0)) + { + i.rm.regmem = NO_BASE_REGISTER; + i.types[op] &= ~Disp; + i.types[op] |= Disp32; + } + else + { + /* 64bit mode overwrites the 32bit absolute + addressing by RIP relative addressing and + absolute addressing is encoded by one of the + redundant SIB forms. */ + i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; + i.sib.base = NO_BASE_REGISTER; + i.sib.index = NO_INDEX_REGISTER; + i.types[op] &= ~Disp; + i.types[op] |= Disp32S; + } } -#if REGISTER_WARNINGS - /* Warn if the e prefix on a general reg is missing. */ - else if (!quiet_warnings - && (i.types[op] & Reg16) != 0 - && (i.tm.operand_types[op] & (Reg32|Acc)) != 0) + else /* !i.base_reg && i.index_reg */ { - as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), - (i.op[op].regs + 8)->reg_name, - i.op[op].regs->reg_name, - i.suffix); + i.sib.index = i.index_reg->reg_num; + i.sib.base = NO_BASE_REGISTER; + i.sib.scale = i.log2_scale_factor; + i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; + i.types[op] &= ~Disp; + if (flag_code != CODE_64BIT) + i.types[op] |= Disp32; /* Must be 32 bit */ + else + i.types[op] |= Disp32S; + if ((i.index_reg->reg_flags & RegRex) != 0) + i.rex |= REX_EXTY; } -#endif - } - else if (i.suffix == WORD_MNEM_SUFFIX) - { - int op; - for (op = i.operands; --op >= 0;) - /* Reject eight bit registers, except where the template - requires them. (eg. movzb) */ - if ((i.types[op] & Reg8) != 0 - && (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0) + } + /* RIP addressing for 64bit mode. */ + else if (i.base_reg->reg_type == BaseIndex) + { + i.rm.regmem = NO_BASE_REGISTER; + i.types[op] &= ~Disp; + i.types[op] |= Disp32S; + i.flags[op] = Operand_PCrel; + } + else if (i.base_reg->reg_type & Reg16) + { + switch (i.base_reg->reg_num) { - as_bad (_("`%%%s' not allowed with `%s%c'"), - i.op[op].regs->reg_name, - i.tm.name, - i.suffix); - return; + case 3: /* (%bx) */ + if (i.index_reg == 0) + i.rm.regmem = 7; + else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ + i.rm.regmem = i.index_reg->reg_num - 6; + break; + case 5: /* (%bp) */ + default_seg = &ss; + if (i.index_reg == 0) + { + i.rm.regmem = 6; + if ((i.types[op] & Disp) == 0) + { + /* fake (%bp) into 0(%bp) */ + i.types[op] |= Disp8; + fake_zero_displacement = 1; + } + } + else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ + i.rm.regmem = i.index_reg->reg_num - 6 + 2; + break; + default: /* (%si) -> 4 or (%di) -> 5 */ + i.rm.regmem = i.base_reg->reg_num - 6 + 4; } -#if REGISTER_WARNINGS - /* Warn if the e prefix on a general reg is present. */ - else if (!quiet_warnings - && (i.types[op] & Reg32) != 0 - && (i.tm.operand_types[op] & (Reg16|Acc)) != 0) + i.rm.mode = mode_from_disp_size (i.types[op]); + } + else /* i.base_reg and 32/64 bit mode */ + { + if (flag_code == CODE_64BIT + && (i.types[op] & Disp)) + { + if (i.types[op] & Disp8) + i.types[op] = Disp8 | Disp32S; + else + i.types[op] = Disp32S; + } + i.rm.regmem = i.base_reg->reg_num; + if ((i.base_reg->reg_flags & RegRex) != 0) + i.rex |= REX_EXTZ; + i.sib.base = i.base_reg->reg_num; + /* x86-64 ignores REX prefix bit here to avoid decoder + complications. */ + if ((i.base_reg->reg_num & 7) == EBP_REG_NUM) + { + default_seg = &ss; + if (i.disp_operands == 0) + { + fake_zero_displacement = 1; + i.types[op] |= Disp8; + } + } + else if (i.base_reg->reg_num == ESP_REG_NUM) { - as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"), - (i.op[op].regs - 8)->reg_name, - i.op[op].regs->reg_name, - i.suffix); + default_seg = &ss; } + i.sib.scale = i.log2_scale_factor; + if (i.index_reg == 0) + { + /* (%esp) becomes two byte modrm with no index + register. We've already stored the code for esp + in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. + Any base register besides %esp will not use the + extra modrm byte. */ + i.sib.index = NO_INDEX_REGISTER; +#if !SCALE1_WHEN_NO_INDEX + /* Another case where we force the second modrm byte. */ + if (i.log2_scale_factor) + i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; #endif - } - else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize)) - /* Do nothing if the instruction is going to ignore the prefix. */ - ; - else - abort (); - } - else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix) - { - i.suffix = stackop_size; - } - - /* Make still unresolved immediate matches conform to size of immediate - given in i.suffix. Note: overlap2 cannot be an immediate! */ - if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32)) - && overlap0 != Imm8 && overlap0 != Imm8S - && overlap0 != Imm16 && overlap0 != Imm32) - { - if (i.suffix) - { - overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : - (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); - } - else if (overlap0 == (Imm16 | Imm32)) - { - overlap0 = - (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; - } - else - { - as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); - return; - } - } - if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32)) - && overlap1 != Imm8 && overlap1 != Imm8S - && overlap1 != Imm16 && overlap1 != Imm32) - { - if (i.suffix) - { - overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) : - (i.suffix == WORD_MNEM_SUFFIX ? Imm16 : Imm32)); - } - else if (overlap1 == (Imm16 | Imm32)) - { - overlap1 = - (flag_16bit_code ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32; - } - else - { - as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")); - return; - } - } - assert ((overlap2 & Imm) == 0); - - i.types[0] = overlap0; - if (overlap0 & ImplicitRegister) - i.reg_operands--; - if (overlap0 & Imm1) - i.imm_operands = 0; /* kludge for shift insns. */ - - i.types[1] = overlap1; - if (overlap1 & ImplicitRegister) - i.reg_operands--; - - i.types[2] = overlap2; - if (overlap2 & ImplicitRegister) - i.reg_operands--; - - /* Finalize opcode. First, we change the opcode based on the operand - size given by i.suffix: We need not change things for byte insns. */ + } + else + { + i.sib.index = i.index_reg->reg_num; + i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; + if ((i.index_reg->reg_flags & RegRex) != 0) + i.rex |= REX_EXTY; + } + i.rm.mode = mode_from_disp_size (i.types[op]); + } - if (!i.suffix && (i.tm.opcode_modifier & W)) - { - as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")); - return; - } + if (fake_zero_displacement) + { + /* Fakes a zero displacement assuming that i.types[op] + holds the correct displacement size. */ + expressionS *exp; + + assert (i.op[op].disps == 0); + exp = &disp_expressions[i.disp_operands++]; + i.op[op].disps = exp; + exp->X_op = O_constant; + exp->X_add_number = 0; + exp->X_add_symbol = (symbolS *) 0; + exp->X_op_symbol = (symbolS *) 0; + } + } - /* For movzx and movsx, need to check the register type. */ - if (intel_syntax - && (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe)) - if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX) + /* Fill in i.rm.reg or i.rm.regmem field with register operand + (if any) based on i.tm.extension_opcode. Again, we must be + careful to make sure that segment/control/debug/test/MMX + registers are coded into the i.rm.reg field. */ + if (i.reg_operands) { - unsigned int prefix = DATA_PREFIX_OPCODE; + unsigned int op = + ((i.types[0] + & (Reg | RegMMX | RegXMM + | SReg2 | SReg3 + | Control | Debug | Test)) + ? 0 + : ((i.types[1] + & (Reg | RegMMX | RegXMM + | SReg2 | SReg3 + | Control | Debug | Test)) + ? 1 + : 2)); + /* If there is an extension opcode to put here, the register + number must be put into the regmem field. */ + if (i.tm.extension_opcode != None) + { + i.rm.regmem = i.op[op].regs->reg_num; + if ((i.op[op].regs->reg_flags & RegRex) != 0) + i.rex |= REX_EXTZ; + } + else + { + i.rm.reg = i.op[op].regs->reg_num; + if ((i.op[op].regs->reg_flags & RegRex) != 0) + i.rex |= REX_EXTX; + } - if ((i.op[1].regs->reg_type & Reg16) != 0) - if (!add_prefix (prefix)) - return; + /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we + must set it to 3 to indicate this is a register operand + in the regmem field. */ + if (!i.mem_operands) + i.rm.mode = 3; } - if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX) - { - /* It's not a byte, select word/dword operation. */ - if (i.tm.opcode_modifier & W) - { - if (i.tm.opcode_modifier & ShortForm) - i.tm.base_opcode |= 8; - else - i.tm.base_opcode |= 1; - } - /* Now select between word & dword operations via the operand - size prefix, except for instructions that will ignore this - prefix anyway. */ - if (((intel_syntax && (i.suffix == DWORD_MNEM_SUFFIX)) - || i.suffix == LONG_MNEM_SUFFIX) == flag_16bit_code - && !(i.tm.opcode_modifier & IgnoreSize)) - { - unsigned int prefix = DATA_PREFIX_OPCODE; - if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */ - prefix = ADDR_PREFIX_OPCODE; + /* Fill in i.rm.reg field with extension opcode (if any). */ + if (i.tm.extension_opcode != None) + i.rm.reg = i.tm.extension_opcode; + } + return default_seg; +} - if (! add_prefix (prefix)) - return; - } - /* Size floating point instruction. */ - if (i.suffix == LONG_MNEM_SUFFIX - || (intel_syntax && i.suffix == DWORD_MNEM_SUFFIX)) - { - if (i.tm.opcode_modifier & FloatMF) - i.tm.base_opcode ^= 4; - } - } +static void +output_branch () +{ + char *p; + int code16; + int prefix; + relax_substateT subtype; + symbolS *sym; + offsetT off; + + code16 = 0; + if (flag_code == CODE_16BIT) + code16 = CODE16; + + prefix = 0; + if (i.prefix[DATA_PREFIX] != 0) + { + prefix = 1; + i.prefixes -= 1; + code16 ^= CODE16; + } + /* Pentium4 branch hints. */ + if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ + || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) + { + prefix++; + i.prefixes--; + } + if (i.prefix[REX_PREFIX] != 0) + { + prefix++; + i.prefixes--; + } - if (i.tm.opcode_modifier & ImmExt) - { - /* These AMD 3DNow! and Intel Katmai New Instructions have an - opcode suffix which is coded in the same place as an 8-bit - immediate field would be. Here we fake an 8-bit immediate - operand from the opcode suffix stored in tm.extension_opcode. */ + if (i.prefixes != 0 && !intel_syntax) + as_warn (_("skipping prefixes on this instruction")); + + /* It's always a symbol; End frag & setup for relax. + Make sure there is enough room in this frag for the largest + instruction we may generate in md_convert_frag. This is 2 + bytes for the opcode and room for the prefix and largest + displacement. */ + frag_grow (prefix + 2 + 4); + /* Prefix and 1 opcode byte go in fr_fix. */ + p = frag_more (prefix + 1); + if (i.prefix[DATA_PREFIX] != 0) + *p++ = DATA_PREFIX_OPCODE; + if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE + || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE) + *p++ = i.prefix[SEG_PREFIX]; + if (i.prefix[REX_PREFIX] != 0) + *p++ = i.prefix[REX_PREFIX]; + *p = i.tm.base_opcode; + + if ((unsigned char) *p == JUMP_PC_RELATIVE) + subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL); + else if ((cpu_arch_flags & Cpu386) != 0) + subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL); + else + subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL); + subtype |= code16; - expressionS *exp; + sym = i.op[0].disps->X_add_symbol; + off = i.op[0].disps->X_add_number; - assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS); + if (i.op[0].disps->X_op != O_constant + && i.op[0].disps->X_op != O_symbol) + { + /* Handle complex expressions. */ + sym = make_expr_symbol (i.op[0].disps); + off = 0; + } - exp = &im_expressions[i.imm_operands++]; - i.op[i.operands].imms = exp; - i.types[i.operands++] = Imm8; - exp->X_op = O_constant; - exp->X_add_number = i.tm.extension_opcode; - i.tm.extension_opcode = None; - } + /* 1 possible extra opcode + 4 byte displacement go in var part. + Pass reloc in fr_var. */ + frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); +} - /* For insns with operands there are more diddles to do to the opcode. */ - if (i.operands) - { - /* Default segment register this instruction will use - for memory accesses. 0 means unknown. - This is only for optimizing out unnecessary segment overrides. */ - const seg_entry *default_seg = 0; - - /* The imul $imm, %reg instruction is converted into - imul $imm, %reg, %reg, and the clr %reg instruction - is converted into xor %reg, %reg. */ - if (i.tm.opcode_modifier & regKludge) - { - unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1; - /* Pretend we saw the extra register operand. */ - assert (i.op[first_reg_op + 1].regs == 0); - i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; - i.types[first_reg_op + 1] = i.types[first_reg_op]; - i.reg_operands = 2; - } +static void +output_jump () +{ + char *p; + int size; - if (i.tm.opcode_modifier & ShortForm) - { - /* The register or float register operand is in operand 0 or 1. */ - unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1; - /* Register goes in low 3 bits of opcode. */ - i.tm.base_opcode |= i.op[op].regs->reg_num; - if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) - { - /* Warn about some common errors, but press on regardless. - The first case can be generated by gcc (<= 2.8.1). */ - if (i.operands == 2) - { - /* Reversed arguments on faddp, fsubp, etc. */ - as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name, - i.op[1].regs->reg_name, - i.op[0].regs->reg_name); - } - else - { - /* Extraneous `l' suffix on fp insn. */ - as_warn (_("translating to `%s %%%s'"), i.tm.name, - i.op[0].regs->reg_name); - } - } - } - else if (i.tm.opcode_modifier & Modrm) - { - /* The opcode is completed (modulo i.tm.extension_opcode which - must be put into the modrm byte). - Now, we make the modrm & index base bytes based on all the - info we've collected. */ - - /* i.reg_operands MUST be the number of real register operands; - implicit registers do not count. */ - if (i.reg_operands == 2) - { - unsigned int source, dest; - source = ((i.types[0] - & (Reg | RegMMX | RegXMM - | SReg2 | SReg3 - | Control | Debug | Test)) - ? 0 : 1); - dest = source + 1; - - i.rm.mode = 3; - /* One of the register operands will be encoded in the - i.tm.reg field, the other in the combined i.tm.mode - and i.tm.regmem fields. If no form of this - instruction supports a memory destination operand, - then we assume the source operand may sometimes be - a memory operand and so we need to store the - destination in the i.rm.reg field. */ - if ((i.tm.operand_types[dest] & AnyMem) == 0) - { - i.rm.reg = i.op[dest].regs->reg_num; - i.rm.regmem = i.op[source].regs->reg_num; - } - else - { - i.rm.reg = i.op[source].regs->reg_num; - i.rm.regmem = i.op[dest].regs->reg_num; - } - } - else - { /* If it's not 2 reg operands... */ - if (i.mem_operands) - { - unsigned int fake_zero_displacement = 0; - unsigned int op = ((i.types[0] & AnyMem) - ? 0 - : (i.types[1] & AnyMem) ? 1 : 2); - - default_seg = &ds; - - if (! i.base_reg) - { - i.rm.mode = 0; - if (! i.disp_operands) - fake_zero_displacement = 1; - if (! i.index_reg) - { - /* Operand is just */ - if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) - { - i.rm.regmem = NO_BASE_REGISTER_16; - i.types[op] &= ~Disp; - i.types[op] |= Disp16; - } - else - { - i.rm.regmem = NO_BASE_REGISTER; - i.types[op] &= ~Disp; - i.types[op] |= Disp32; - } - } - else /* ! i.base_reg && i.index_reg */ - { - i.sib.index = i.index_reg->reg_num; - i.sib.base = NO_BASE_REGISTER; - i.sib.scale = i.log2_scale_factor; - i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; - i.types[op] &= ~Disp; - i.types[op] |= Disp32; /* Must be 32 bit. */ - } - } - else if (i.base_reg->reg_type & Reg16) - { - switch (i.base_reg->reg_num) - { - case 3: /* (%bx) */ - if (! i.index_reg) - i.rm.regmem = 7; - else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ - i.rm.regmem = i.index_reg->reg_num - 6; - break; - case 5: /* (%bp) */ - default_seg = &ss; - if (! i.index_reg) - { - i.rm.regmem = 6; - if ((i.types[op] & Disp) == 0) - { - /* fake (%bp) into 0(%bp) */ - i.types[op] |= Disp8; - fake_zero_displacement = 1; - } - } - else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ - i.rm.regmem = i.index_reg->reg_num - 6 + 2; - break; - default: /* (%si) -> 4 or (%di) -> 5 */ - i.rm.regmem = i.base_reg->reg_num - 6 + 4; - } - i.rm.mode = mode_from_disp_size (i.types[op]); - } - else /* i.base_reg and 32 bit mode */ - { - i.rm.regmem = i.base_reg->reg_num; - i.sib.base = i.base_reg->reg_num; - if (i.base_reg->reg_num == EBP_REG_NUM) - { - default_seg = &ss; - if (i.disp_operands == 0) - { - fake_zero_displacement = 1; - i.types[op] |= Disp8; - } - } - else if (i.base_reg->reg_num == ESP_REG_NUM) - { - default_seg = &ss; - } - i.sib.scale = i.log2_scale_factor; - if (! i.index_reg) - { - /* (%esp) becomes two byte modrm - with no index register. We've already - stored the code for esp in i.rm.regmem - ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any - base register besides %esp will not use - the extra modrm byte. */ - i.sib.index = NO_INDEX_REGISTER; -#if ! SCALE1_WHEN_NO_INDEX - /* Another case where we force the second - modrm byte. */ - if (i.log2_scale_factor) - i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; -#endif - } - else - { - i.sib.index = i.index_reg->reg_num; - i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING; - } - i.rm.mode = mode_from_disp_size (i.types[op]); - } + if (i.tm.opcode_modifier & JumpByte) + { + /* This is a loop or jecxz type instruction. */ + size = 1; + if (i.prefix[ADDR_PREFIX] != 0) + { + FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); + i.prefixes -= 1; + } + /* Pentium4 branch hints. */ + if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */ + || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */) + { + FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]); + i.prefixes--; + } + } + else + { + int code16; - if (fake_zero_displacement) - { - /* Fakes a zero displacement assuming that i.types[op] - holds the correct displacement size. */ - expressionS *exp; - - assert (i.op[op].disps == 0); - exp = &disp_expressions[i.disp_operands++]; - i.op[op].disps = exp; - exp->X_op = O_constant; - exp->X_add_number = 0; - exp->X_add_symbol = (symbolS *) 0; - exp->X_op_symbol = (symbolS *) 0; - } - } - - /* Fill in i.rm.reg or i.rm.regmem field with register - operand (if any) based on i.tm.extension_opcode. - Again, we must be careful to make sure that - segment/control/debug/test/MMX registers are coded - into the i.rm.reg field. */ - if (i.reg_operands) - { - unsigned int op = - ((i.types[0] - & (Reg | RegMMX | RegXMM - | SReg2 | SReg3 - | Control | Debug | Test)) - ? 0 - : ((i.types[1] - & (Reg | RegMMX | RegXMM - | SReg2 | SReg3 - | Control | Debug | Test)) - ? 1 - : 2)); - /* If there is an extension opcode to put here, the - register number must be put into the regmem field. */ - if (i.tm.extension_opcode != None) - i.rm.regmem = i.op[op].regs->reg_num; - else - i.rm.reg = i.op[op].regs->reg_num; - - /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 - we must set it to 3 to indicate this is a register - operand in the regmem field. */ - if (!i.mem_operands) - i.rm.mode = 3; - } - - /* Fill in i.rm.reg field with extension opcode (if any). */ - if (i.tm.extension_opcode != None) - i.rm.reg = i.tm.extension_opcode; - } - } - else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm)) - { - if (i.tm.base_opcode == POP_SEG_SHORT - && i.op[0].regs->reg_num == 1) - { - as_bad (_("you can't `pop %%cs'")); - return; - } - i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); - } - else if ((i.tm.base_opcode & ~(D|W)) == MOV_AX_DISP32) - { - default_seg = &ds; - } - else if ((i.tm.opcode_modifier & IsString) != 0) - { - /* For the string instructions that allow a segment override - on one of their operands, the default segment is ds. */ - default_seg = &ds; - } + code16 = 0; + if (flag_code == CODE_16BIT) + code16 = CODE16; - /* If a segment was explicitly specified, - and the specified segment is not the default, - use an opcode prefix to select it. - If we never figured out what the default segment is, - then default_seg will be zero at this point, - and the specified segment prefix will always be used. */ - if ((i.seg[0]) && (i.seg[0] != default_seg)) - { - if (! add_prefix (i.seg[0]->seg_prefix)) - return; - } - } - else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0) - { - /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ - as_warn (_("translating to `%sp'"), i.tm.name); - } - } + if (i.prefix[DATA_PREFIX] != 0) + { + FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); + i.prefixes -= 1; + code16 ^= CODE16; + } - /* Handle conversion of 'int $3' --> special int3 insn. */ - if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3) - { - i.tm.base_opcode = INT3_OPCODE; - i.imm_operands = 0; + size = 4; + if (code16) + size = 2; } - if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword)) - && i.op[0].disps->X_op == O_constant) + if (i.prefix[REX_PREFIX] != 0) { - /* Convert "jmp constant" (and "call constant") to a jump (call) to - the absolute address given by the constant. Since ix86 jumps and - calls are pc relative, we need to generate a reloc. */ - i.op[0].disps->X_add_symbol = &abs_symbol; - i.op[0].disps->X_op = O_symbol; + FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]); + i.prefixes -= 1; } - /* We are ready to output the insn. */ - { - register char *p; + if (i.prefixes != 0 && !intel_syntax) + as_warn (_("skipping prefixes on this instruction")); - /* Output jumps. */ - if (i.tm.opcode_modifier & Jump) - { - int size; - int code16; - int prefix; + p = frag_more (1 + size); + *p++ = i.tm.base_opcode; - code16 = 0; - if (flag_16bit_code) - code16 = CODE16; + fix_new_exp (frag_now, p - frag_now->fr_literal, size, + i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); +} - prefix = 0; - if (i.prefix[DATA_PREFIX]) - { - prefix = 1; - i.prefixes -= 1; - code16 ^= CODE16; - } +static void +output_interseg_jump () +{ + char *p; + int size; + int prefix; + int code16; - size = 4; - if (code16) - size = 2; - - if (i.prefixes != 0 && !intel_syntax) - as_warn (_("skipping prefixes on this instruction")); - - /* It's always a symbol; End frag & setup for relax. - Make sure there is enough room in this frag for the largest - instruction we may generate in md_convert_frag. This is 2 - bytes for the opcode and room for the prefix and largest - displacement. */ - frag_grow (prefix + 2 + size); - insn_size += prefix + 1; - /* Prefix and 1 opcode byte go in fr_fix. */ - p = frag_more (prefix + 1); - if (prefix) - *p++ = DATA_PREFIX_OPCODE; - *p = i.tm.base_opcode; - /* 1 possible extra opcode + displacement go in var part. - Pass reloc in fr_var. */ - frag_var (rs_machine_dependent, - 1 + size, - i.disp_reloc[0], - ((unsigned char) *p == JUMP_PC_RELATIVE - ? ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL) | code16 - : ENCODE_RELAX_STATE (COND_JUMP, SMALL) | code16), - i.op[0].disps->X_add_symbol, - i.op[0].disps->X_add_number, - p); - } - else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) - { - int size; + code16 = 0; + if (flag_code == CODE_16BIT) + code16 = CODE16; - if (i.tm.opcode_modifier & JumpByte) - { - /* This is a loop or jecxz type instruction. */ - size = 1; - if (i.prefix[ADDR_PREFIX]) - { - insn_size += 1; - FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE); - i.prefixes -= 1; - } - } - else - { - int code16; + prefix = 0; + if (i.prefix[DATA_PREFIX] != 0) + { + prefix = 1; + i.prefixes -= 1; + code16 ^= CODE16; + } + if (i.prefix[REX_PREFIX] != 0) + { + prefix++; + i.prefixes -= 1; + } - code16 = 0; - if (flag_16bit_code) - code16 = CODE16; + size = 4; + if (code16) + size = 2; - if (i.prefix[DATA_PREFIX]) - { - insn_size += 1; - FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE); - i.prefixes -= 1; - code16 ^= CODE16; - } + if (i.prefixes != 0 && !intel_syntax) + as_warn (_("skipping prefixes on this instruction")); - size = 4; - if (code16) - size = 2; - } + /* 1 opcode; 2 segment; offset */ + p = frag_more (prefix + 1 + 2 + size); - if (i.prefixes != 0 && !intel_syntax) - as_warn (_("skipping prefixes on this instruction")); + if (i.prefix[DATA_PREFIX] != 0) + *p++ = DATA_PREFIX_OPCODE; - if (fits_in_unsigned_byte (i.tm.base_opcode)) - { - insn_size += 1 + size; - p = frag_more (1 + size); - } - else - { - /* Opcode can be at most two bytes. */ - insn_size += 2 + size; - p = frag_more (2 + size); - *p++ = (i.tm.base_opcode >> 8) & 0xff; - } - *p++ = i.tm.base_opcode & 0xff; + if (i.prefix[REX_PREFIX] != 0) + *p++ = i.prefix[REX_PREFIX]; - fix_new_exp (frag_now, p - frag_now->fr_literal, size, - i.op[0].disps, 1, reloc (size, 1, i.disp_reloc[0])); - } - else if (i.tm.opcode_modifier & JumpInterSegment) - { - int size; - int prefix; - int code16; + *p++ = i.tm.base_opcode; + if (i.op[1].imms->X_op == O_constant) + { + offsetT n = i.op[1].imms->X_add_number; - code16 = 0; - if (flag_16bit_code) - code16 = CODE16; + if (size == 2 + && !fits_in_unsigned_word (n) + && !fits_in_signed_word (n)) + { + as_bad (_("16-bit jump out of range")); + return; + } + md_number_to_chars (p, n, size); + } + else + fix_new_exp (frag_now, p - frag_now->fr_literal, size, + i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); + if (i.op[0].imms->X_op != O_constant) + as_bad (_("can't handle non absolute segment in `%s'"), + i.tm.name); + md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); +} - prefix = 0; - if (i.prefix[DATA_PREFIX]) - { - prefix = 1; - i.prefixes -= 1; - code16 ^= CODE16; - } +static void +output_insn () +{ + /* Tie dwarf2 debug info to the address at the start of the insn. + We can't do this after the insn has been output as the current + frag may have been closed off. eg. by frag_var. */ + dwarf2_emit_insn (0); + + /* Output jumps. */ + if (i.tm.opcode_modifier & Jump) + output_branch (); + else if (i.tm.opcode_modifier & (JumpByte | JumpDword)) + output_jump (); + else if (i.tm.opcode_modifier & JumpInterSegment) + output_interseg_jump (); + else + { + /* Output normal instructions here. */ + char *p; + unsigned char *q; + + /* All opcodes on i386 have either 1 or 2 bytes. We may use third + byte for the SSE instructions to specify a prefix they require. */ + if (i.tm.base_opcode & 0xff0000) + add_prefix ((i.tm.base_opcode >> 16) & 0xff); + + /* The prefix bytes. */ + for (q = i.prefix; + q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); + q++) + { + if (*q) + { + p = frag_more (1); + md_number_to_chars (p, (valueT) *q, 1); + } + } - size = 4; - if (code16) - size = 2; + /* Now the opcode; be careful about word order here! */ + if (fits_in_unsigned_byte (i.tm.base_opcode)) + { + FRAG_APPEND_1_CHAR (i.tm.base_opcode); + } + else + { + p = frag_more (2); + /* Put out high byte first: can't use md_number_to_chars! */ + *p++ = (i.tm.base_opcode >> 8) & 0xff; + *p = i.tm.base_opcode & 0xff; + } - if (i.prefixes != 0 && !intel_syntax) - as_warn (_("skipping prefixes on this instruction")); + /* Now the modrm byte and sib byte (if present). */ + if (i.tm.opcode_modifier & Modrm) + { + p = frag_more (1); + md_number_to_chars (p, + (valueT) (i.rm.regmem << 0 + | i.rm.reg << 3 + | i.rm.mode << 6), + 1); + /* If i.rm.regmem == ESP (4) + && i.rm.mode != (Register mode) + && not 16 bit + ==> need second modrm byte. */ + if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING + && i.rm.mode != 3 + && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) + { + p = frag_more (1); + md_number_to_chars (p, + (valueT) (i.sib.base << 0 + | i.sib.index << 3 + | i.sib.scale << 6), + 1); + } + } - /* 1 opcode; 2 segment; offset */ - insn_size += prefix + 1 + 2 + size; - p = frag_more (prefix + 1 + 2 + size); - if (prefix) - *p++ = DATA_PREFIX_OPCODE; - *p++ = i.tm.base_opcode; - if (i.op[1].imms->X_op == O_constant) - { - offsetT n = i.op[1].imms->X_add_number; + if (i.disp_operands) + output_disp (); - if (size == 2 - && !fits_in_unsigned_word (n) - && !fits_in_signed_word (n)) - { - as_bad (_("16-bit jump out of range")); - return; - } - md_number_to_chars (p, n, size); - } - else - fix_new_exp (frag_now, p - frag_now->fr_literal, size, - i.op[1].imms, 0, reloc (size, 0, i.disp_reloc[0])); - if (i.op[0].imms->X_op != O_constant) - as_bad (_("can't handle non absolute segment in `%s'"), - i.tm.name); - md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2); - } - else - { - /* Output normal instructions here. */ - unsigned char *q; + if (i.imm_operands) + output_imm (); + } - /* The prefix bytes. */ - for (q = i.prefix; - q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); - q++) - { - if (*q) - { - insn_size += 1; - p = frag_more (1); - md_number_to_chars (p, (valueT) *q, 1); - } - } +#ifdef DEBUG386 + if (flag_debug) + { + pi (line, &i); + } +#endif /* DEBUG386 */ +} - /* Now the opcode; be careful about word order here! */ - if (fits_in_unsigned_byte (i.tm.base_opcode)) - { - insn_size += 1; - FRAG_APPEND_1_CHAR (i.tm.base_opcode); - } - else if (fits_in_unsigned_word (i.tm.base_opcode)) - { - insn_size += 2; - p = frag_more (2); - /* Put out high byte first: can't use md_number_to_chars! */ - *p++ = (i.tm.base_opcode >> 8) & 0xff; - *p = i.tm.base_opcode & 0xff; - } - else - { /* Opcode is either 3 or 4 bytes. */ - if (i.tm.base_opcode & 0xff000000) - { - insn_size += 4; - p = frag_more (4); - *p++ = (i.tm.base_opcode >> 24) & 0xff; - } - else - { - insn_size += 3; - p = frag_more (3); - } - *p++ = (i.tm.base_opcode >> 16) & 0xff; - *p++ = (i.tm.base_opcode >> 8) & 0xff; - *p = (i.tm.base_opcode) & 0xff; - } +static void +output_disp () +{ + char *p; + unsigned int n; - /* Now the modrm byte and sib byte (if present). */ - if (i.tm.opcode_modifier & Modrm) - { - insn_size += 1; - p = frag_more (1); - md_number_to_chars (p, - (valueT) (i.rm.regmem << 0 - | i.rm.reg << 3 - | i.rm.mode << 6), - 1); - /* If i.rm.regmem == ESP (4) - && i.rm.mode != (Register mode) - && not 16 bit - ==> need second modrm byte. */ - if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING - && i.rm.mode != 3 - && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0)) - { - insn_size += 1; - p = frag_more (1); - md_number_to_chars (p, - (valueT) (i.sib.base << 0 - | i.sib.index << 3 - | i.sib.scale << 6), - 1); - } - } + for (n = 0; n < i.operands; n++) + { + if (i.types[n] & Disp) + { + if (i.op[n].disps->X_op == O_constant) + { + int size; + offsetT val; - if (i.disp_operands) - { - register unsigned int n; + size = 4; + if (i.types[n] & (Disp8 | Disp16 | Disp64)) + { + size = 2; + if (i.types[n] & Disp8) + size = 1; + if (i.types[n] & Disp64) + size = 8; + } + val = offset_in_range (i.op[n].disps->X_add_number, + size); + p = frag_more (size); + md_number_to_chars (p, val, size); + } + else + { + int size = 4; + int sign = 0; + int pcrel = (i.flags[n] & Operand_PCrel) != 0; + + /* The PC relative address is computed relative + to the instruction boundary, so in case immediate + fields follows, we need to adjust the value. */ + if (pcrel && i.imm_operands) + { + int imm_size = 4; + unsigned int n1; - for (n = 0; n < i.operands; n++) - { - if (i.types[n] & Disp) - { - if (i.op[n].disps->X_op == O_constant) + for (n1 = 0; n1 < i.operands; n1++) + if (i.types[n1] & Imm) { - int size; - offsetT val; - - size = 4; - if (i.types[n] & (Disp8 | Disp16)) + if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64)) { - size = 2; - if (i.types[n] & Disp8) - size = 1; + imm_size = 2; + if (i.types[n1] & (Imm8 | Imm8S)) + imm_size = 1; + if (i.types[n1] & Imm64) + imm_size = 8; } - val = offset_in_range (i.op[n].disps->X_add_number, - size); - insn_size += size; - p = frag_more (size); - md_number_to_chars (p, val, size); + break; } - else - { - int size = 4; + /* We should find the immediate. */ + if (n1 == i.operands) + abort (); + i.op[n].disps->X_add_number -= imm_size; + } - if (i.types[n] & Disp16) - size = 2; + if (i.types[n] & Disp32S) + sign = 1; - insn_size += size; - p = frag_more (size); - fix_new_exp (frag_now, p - frag_now->fr_literal, size, - i.op[n].disps, 0, - reloc (size, 0, i.disp_reloc[n])); - } - } - } - } + if (i.types[n] & (Disp16 | Disp64)) + { + size = 2; + if (i.types[n] & Disp64) + size = 8; + } - /* Output immediate. */ - if (i.imm_operands) - { - register unsigned int n; + p = frag_more (size); + fix_new_exp (frag_now, p - frag_now->fr_literal, size, + i.op[n].disps, pcrel, + reloc (size, pcrel, sign, i.reloc[n])); + } + } + } +} - for (n = 0; n < i.operands; n++) - { - if (i.types[n] & Imm) - { - if (i.op[n].imms->X_op == O_constant) - { - int size; - offsetT val; +static void +output_imm () +{ + char *p; + unsigned int n; - size = 4; - if (i.types[n] & (Imm8 | Imm8S | Imm16)) - { - size = 2; - if (i.types[n] & (Imm8 | Imm8S)) - size = 1; - } - val = offset_in_range (i.op[n].imms->X_add_number, - size); - insn_size += size; - p = frag_more (size); - md_number_to_chars (p, val, size); - } - else - { - /* Not absolute_section. - Need a 32-bit fixup (don't support 8bit - non-absolute imms). Try to support other - sizes ... */ + for (n = 0; n < i.operands; n++) + { + if (i.types[n] & Imm) + { + if (i.op[n].imms->X_op == O_constant) + { + int size; + offsetT val; + + size = 4; + if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) + { + size = 2; + if (i.types[n] & (Imm8 | Imm8S)) + size = 1; + else if (i.types[n] & Imm64) + size = 8; + } + val = offset_in_range (i.op[n].imms->X_add_number, + size); + p = frag_more (size); + md_number_to_chars (p, val, size); + } + else + { + /* Not absolute_section. + Need a 32-bit fixup (don't support 8bit + non-absolute imms). Try to support other + sizes ... */ + RELOC_ENUM reloc_type; + int size = 4; + int sign = 0; + + if ((i.types[n] & (Imm32S)) + && i.suffix == QWORD_MNEM_SUFFIX) + sign = 1; + if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64)) + { + size = 2; + if (i.types[n] & (Imm8 | Imm8S)) + size = 1; + if (i.types[n] & Imm64) + size = 8; + } + + p = frag_more (size); + reloc_type = reloc (size, 0, sign, i.reloc[n]); #ifdef BFD_ASSEMBLER - enum bfd_reloc_code_real reloc_type; -#else - int reloc_type; + if (reloc_type == BFD_RELOC_32 + && GOT_symbol + && GOT_symbol == i.op[n].imms->X_add_symbol + && (i.op[n].imms->X_op == O_symbol + || (i.op[n].imms->X_op == O_add + && ((symbol_get_value_expression + (i.op[n].imms->X_op_symbol)->X_op) + == O_subtract)))) + { + /* We don't support dynamic linking on x86-64 yet. */ + if (flag_code == CODE_64BIT) + abort (); + reloc_type = BFD_RELOC_386_GOTPC; + i.op[n].imms->X_add_number += 3; + } #endif - int size = 4; + fix_new_exp (frag_now, p - frag_now->fr_literal, size, + i.op[n].imms, 0, reloc_type); + } + } + } +} + +#ifndef LEX_AT +static char *lex_got PARAMS ((RELOC_ENUM *, int *)); + +/* Parse operands of the form + @GOTOFF+ + and similar .plt or .got references. + + If we find one, set up the correct relocation in RELOC and copy the + input string, minus the `@GOTOFF' into a malloc'd buffer for + parsing by the calling routine. Return this buffer, and if ADJUST + is non-null set it to the length of the string we removed from the + input line. Otherwise return NULL. */ +static char * +lex_got (reloc, adjust) + RELOC_ENUM *reloc; + int *adjust; +{ + static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" }; + static const struct { + const char *str; + const RELOC_ENUM rel[NUM_FLAG_CODE]; + } gotrel[] = { + { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } }, + { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } }, + { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } }, + { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, 0 } }, + { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } }, + { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, 0 } }, + { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, 0 } }, + { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } }, + { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, 0 } }, + { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } } + }; + char *cp; + unsigned int j; + + for (cp = input_line_pointer; *cp != '@'; cp++) + if (is_end_of_line[(unsigned char) *cp]) + return NULL; + + for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) + { + int len; + + len = strlen (gotrel[j].str); + if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) + { + if (gotrel[j].rel[(unsigned int) flag_code] != 0) + { + int first, second; + char *tmpbuf, *past_reloc; + + *reloc = gotrel[j].rel[(unsigned int) flag_code]; + if (adjust) + *adjust = len; + + if (GOT_symbol == NULL) + GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); + + /* Replace the relocation token with ' ', so that + errors like foo@GOTOFF1 will be detected. */ + + /* The length of the first part of our input line. */ + first = cp - input_line_pointer; + + /* The second part goes from after the reloc token until + (and including) an end_of_line char. Don't use strlen + here as the end_of_line char may not be a NUL. */ + past_reloc = cp + 1 + len; + for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; ) + ; + second = cp - past_reloc; + + /* Allocate and copy string. The trailing NUL shouldn't + be necessary, but be safe. */ + tmpbuf = xmalloc (first + second + 2); + memcpy (tmpbuf, input_line_pointer, first); + tmpbuf[first] = ' '; + memcpy (tmpbuf + first + 1, past_reloc, second); + tmpbuf[first + second + 1] = '\0'; + return tmpbuf; + } + + as_bad (_("@%s reloc is not supported in %s bit mode"), + gotrel[j].str, mode_name[(unsigned int) flag_code]); + return NULL; + } + } + + /* Might be a symbol version string. Don't as_bad here. */ + return NULL; +} + +/* x86_cons_fix_new is called via the expression parsing code when a + reloc is needed. We use this hook to get the correct .got reloc. */ +static RELOC_ENUM got_reloc = NO_RELOC; + +void +x86_cons_fix_new (frag, off, len, exp) + fragS *frag; + unsigned int off; + unsigned int len; + expressionS *exp; +{ + RELOC_ENUM r = reloc (len, 0, 0, got_reloc); + got_reloc = NO_RELOC; + fix_new_exp (frag, off, len, exp, 0, r); +} - if (i.types[n] & Imm16) - size = 2; - else if (i.types[n] & (Imm8 | Imm8S)) - size = 1; +void +x86_cons (exp, size) + expressionS *exp; + int size; +{ + if (size == 4) + { + /* Handle @GOTOFF and the like in an expression. */ + char *save; + char *gotfree_input_line; + int adjust; - insn_size += size; - p = frag_more (size); - reloc_type = reloc (size, 0, i.disp_reloc[0]); -#ifdef BFD_ASSEMBLER - if (reloc_type == BFD_RELOC_32 - && GOT_symbol - && GOT_symbol == i.op[n].imms->X_add_symbol - && (i.op[n].imms->X_op == O_symbol - || (i.op[n].imms->X_op == O_add - && ((symbol_get_value_expression - (i.op[n].imms->X_op_symbol)->X_op) - == O_subtract)))) - { - reloc_type = BFD_RELOC_386_GOTPC; - i.op[n].imms->X_add_number += 3; - } -#endif - fix_new_exp (frag_now, p - frag_now->fr_literal, size, - i.op[n].imms, 0, reloc_type); - } - } - } - } - } + save = input_line_pointer; + gotfree_input_line = lex_got (&got_reloc, &adjust); + if (gotfree_input_line) + input_line_pointer = gotfree_input_line; - dwarf2_emit_insn (insn_size); + expression (exp); -#ifdef DEBUG386 - if (flag_debug) - { - pi (line, &i); - } -#endif /* DEBUG386 */ - } + if (gotfree_input_line) + { + /* expression () has merrily parsed up to the end of line, + or a comma - in the wrong buffer. Transfer how far + input_line_pointer has moved to the right buffer. */ + input_line_pointer = (save + + (input_line_pointer - gotfree_input_line) + + adjust); + free (gotfree_input_line); + } + } + else + expression (exp); } - +#endif + static int i386_immediate PARAMS ((char *)); static int @@ -2642,6 +3512,9 @@ i386_immediate (imm_start) char *imm_start; { char *save_input_line_pointer; +#ifndef LEX_AT + char *gotfree_input_line; +#endif segT exp_seg = 0; expressionS *exp; @@ -2661,64 +3534,22 @@ i386_immediate (imm_start) input_line_pointer = imm_start; #ifndef LEX_AT - { - /* We can have operands of the form - @GOTOFF+ - Take the easy way out here and copy everything - into a temporary buffer... */ - register char *cp; - - cp = strchr (input_line_pointer, '@'); - if (cp != NULL) - { - char *tmpbuf; - int len = 0; - int first; - - /* GOT relocations are not supported in 16 bit mode. */ - if (flag_16bit_code) - as_bad (_("GOT relocations not supported in 16 bit mode")); - - if (GOT_symbol == NULL) - GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); - - if (strncmp (cp + 1, "PLT", 3) == 0) - { - i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; - len = 3; - } - else if (strncmp (cp + 1, "GOTOFF", 6) == 0) - { - i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; - len = 6; - } - else if (strncmp (cp + 1, "GOT", 3) == 0) - { - i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; - len = 3; - } - else - as_bad (_("bad reloc specifier in expression")); - - /* Replace the relocation token with ' ', so that errors like - foo@GOTOFF1 will be detected. */ - first = cp - input_line_pointer; - tmpbuf = (char *) alloca (strlen (input_line_pointer)); - memcpy (tmpbuf, input_line_pointer, first); - tmpbuf[first] = ' '; - strcpy (tmpbuf + first + 1, cp + 1 + len); - input_line_pointer = tmpbuf; - } - } + gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); + if (gotfree_input_line) + input_line_pointer = gotfree_input_line; #endif exp_seg = expression (exp); SKIP_WHITESPACE (); if (*input_line_pointer) - as_bad (_("ignoring junk `%s' after expression"), input_line_pointer); + as_bad (_("junk `%s' after expression"), input_line_pointer); input_line_pointer = save_input_line_pointer; +#ifndef LEX_AT + if (gotfree_input_line) + free (gotfree_input_line); +#endif if (exp->X_op == O_absent || exp->X_op == O_big) { @@ -2730,11 +3561,14 @@ i386_immediate (imm_start) exp->X_add_symbol = (symbolS *) 0; exp->X_op_symbol = (symbolS *) 0; } - - if (exp->X_op == O_constant) + else if (exp->X_op == O_constant) { /* Size it properly later. */ - i.types[this_operand] |= Imm32; + i.types[this_operand] |= Imm64; + /* If BFD64, sign extend val. */ + if (!use_rela_relocations) + if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) + exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); } #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) else if (1 @@ -2762,46 +3596,47 @@ i386_immediate (imm_start) { /* This is an address. The size of the address will be determined later, depending on destination register, - suffix, or the default for the section. We exclude - Imm8S here so that `push $foo' and other instructions - with an Imm8S form will use Imm16 or Imm32. */ - i.types[this_operand] |= (Imm8 | Imm16 | Imm32); + suffix, or the default for the section. */ + i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64; } return 1; } -static int i386_scale PARAMS ((char *)); +static char *i386_scale PARAMS ((char *)); -static int +static char * i386_scale (scale) char *scale; { - if (!isdigit (*scale)) - goto bad_scale; + offsetT val; + char *save = input_line_pointer; + + input_line_pointer = scale; + val = get_absolute_expression (); - switch (*scale) + switch (val) { - case '0': - case '1': + case 0: + case 1: i.log2_scale_factor = 0; break; - case '2': + case 2: i.log2_scale_factor = 1; break; - case '4': + case 4: i.log2_scale_factor = 2; break; - case '8': + case 8: i.log2_scale_factor = 3; break; default: - bad_scale: as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"), scale); - return 0; + input_line_pointer = save; + return NULL; } - if (i.log2_scale_factor != 0 && ! i.index_reg) + if (i.log2_scale_factor != 0 && i.index_reg == 0) { as_warn (_("scale factor of %d without an index register"), 1 << i.log2_scale_factor); @@ -2809,7 +3644,9 @@ i386_scale (scale) i.log2_scale_factor = 0; #endif } - return 1; + scale = input_line_pointer; + input_line_pointer = save; + return scale; } static int i386_displacement PARAMS ((char *, char *)); @@ -2819,12 +3656,20 @@ i386_displacement (disp_start, disp_end) char *disp_start; char *disp_end; { - register expressionS *exp; + expressionS *exp; segT exp_seg = 0; char *save_input_line_pointer; +#ifndef LEX_AT + char *gotfree_input_line; +#endif int bigdisp = Disp32; - if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0)) + if (flag_code == CODE_64BIT) + { + if (i.prefix[ADDR_PREFIX] == 0) + bigdisp = Disp64; + } + else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) bigdisp = Disp16; i.types[this_operand] |= bigdisp; @@ -2880,85 +3725,54 @@ i386_displacement (disp_start, disp_end) } #endif #ifndef LEX_AT - { - /* We can have operands of the form - @GOTOFF+ - Take the easy way out here and copy everything - into a temporary buffer... */ - register char *cp; - - cp = strchr (input_line_pointer, '@'); - if (cp != NULL) - { - char *tmpbuf; - int len = 0; - int first; - - /* GOT relocations are not supported in 16 bit mode. */ - if (flag_16bit_code) - as_bad (_("GOT relocations not supported in 16 bit mode")); - - if (GOT_symbol == NULL) - GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME); - - if (strncmp (cp + 1, "PLT", 3) == 0) - { - i.disp_reloc[this_operand] = BFD_RELOC_386_PLT32; - len = 3; - } - else if (strncmp (cp + 1, "GOTOFF", 6) == 0) - { - i.disp_reloc[this_operand] = BFD_RELOC_386_GOTOFF; - len = 6; - } - else if (strncmp (cp + 1, "GOT", 3) == 0) - { - i.disp_reloc[this_operand] = BFD_RELOC_386_GOT32; - len = 3; - } - else - as_bad (_("bad reloc specifier in expression")); - - /* Replace the relocation token with ' ', so that errors like - foo@GOTOFF1 will be detected. */ - first = cp - input_line_pointer; - tmpbuf = (char *) alloca (strlen (input_line_pointer)); - memcpy (tmpbuf, input_line_pointer, first); - tmpbuf[first] = ' '; - strcpy (tmpbuf + first + 1, cp + 1 + len); - input_line_pointer = tmpbuf; - } - } + gotfree_input_line = lex_got (&i.reloc[this_operand], NULL); + if (gotfree_input_line) + input_line_pointer = gotfree_input_line; #endif exp_seg = expression (exp); + SKIP_WHITESPACE (); + if (*input_line_pointer) + as_bad (_("junk `%s' after expression"), input_line_pointer); +#if GCC_ASM_O_HACK + RESTORE_END_STRING (disp_end + 1); +#endif + RESTORE_END_STRING (disp_end); + input_line_pointer = save_input_line_pointer; +#ifndef LEX_AT + if (gotfree_input_line) + free (gotfree_input_line); +#endif + #ifdef BFD_ASSEMBLER /* We do this to make sure that the section symbol is in the symbol table. We will ultimately change the relocation to be relative to the beginning of the section. */ - if (i.disp_reloc[this_operand] == BFD_RELOC_386_GOTOFF) + if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF + || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) { - if (S_IS_LOCAL(exp->X_add_symbol) + if (exp->X_op != O_symbol) + { + as_bad (_("bad expression used with @%s"), + (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL + ? "GOTPCREL" + : "GOTOFF")); + return 0; + } + + if (S_IS_LOCAL (exp->X_add_symbol) && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section) section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); - assert (exp->X_op == O_symbol); exp->X_op = O_subtract; exp->X_op_symbol = GOT_symbol; - i.disp_reloc[this_operand] = BFD_RELOC_32; + if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) + i.reloc[this_operand] = BFD_RELOC_32_PCREL; + else + i.reloc[this_operand] = BFD_RELOC_32; } #endif - SKIP_WHITESPACE (); - if (*input_line_pointer) - as_bad (_("ignoring junk `%s' after expression"), - input_line_pointer); -#if GCC_ASM_O_HACK - RESTORE_END_STRING (disp_end + 1); -#endif - RESTORE_END_STRING (disp_end); - input_line_pointer = save_input_line_pointer; - if (exp->X_op == O_absent || exp->X_op == O_big) { /* Missing or bad expr becomes absolute 0. */ @@ -2988,10 +3802,12 @@ i386_displacement (disp_start, disp_end) return 0; } #endif + else if (flag_code == CODE_64BIT) + i.types[this_operand] |= Disp32S | Disp32; return 1; } -static int i386_index_check PARAMS((const char *)); +static int i386_index_check PARAMS ((const char *)); /* Make sure the memory operand we've been dealt is valid. Return 1 on success, 0 on a failure. */ @@ -3000,32 +3816,71 @@ static int i386_index_check (operand_string) const char *operand_string; { + int ok; #if INFER_ADDR_PREFIX int fudged = 0; tryprefix: #endif - if (flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) - /* 16 bit mode checks. */ - ? ((i.base_reg - && ((i.base_reg->reg_type & (Reg16|BaseIndex)) - != (Reg16|BaseIndex))) - || (i.index_reg - && (((i.index_reg->reg_type & (Reg16|BaseIndex)) - != (Reg16|BaseIndex)) - || ! (i.base_reg - && i.base_reg->reg_num < 6 - && i.index_reg->reg_num >= 6 - && i.log2_scale_factor == 0)))) - /* 32 bit mode checks. */ - : ((i.base_reg - && (i.base_reg->reg_type & Reg32) == 0) - || (i.index_reg - && ((i.index_reg->reg_type & (Reg32|BaseIndex)) - != (Reg32|BaseIndex))))) + ok = 1; + if (flag_code == CODE_64BIT) + { + if (i.prefix[ADDR_PREFIX] == 0) + { + /* 64bit checks. */ + if ((i.base_reg + && ((i.base_reg->reg_type & Reg64) == 0) + && (i.base_reg->reg_type != BaseIndex + || i.index_reg)) + || (i.index_reg + && ((i.index_reg->reg_type & (Reg64 | BaseIndex)) + != (Reg64 | BaseIndex)))) + ok = 0; + } + else + { + /* 32bit checks. */ + if ((i.base_reg + && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) + || (i.index_reg + && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex)) + != (Reg32 | BaseIndex)))) + ok = 0; + } + } + else + { + if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)) + { + /* 16bit checks. */ + if ((i.base_reg + && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex)) + != (Reg16 | BaseIndex))) + || (i.index_reg + && (((i.index_reg->reg_type & (Reg16 | BaseIndex)) + != (Reg16 | BaseIndex)) + || !(i.base_reg + && i.base_reg->reg_num < 6 + && i.index_reg->reg_num >= 6 + && i.log2_scale_factor == 0)))) + ok = 0; + } + else + { + /* 32bit checks. */ + if ((i.base_reg + && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32) + || (i.index_reg + && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex)) + != (Reg32 | BaseIndex)))) + ok = 0; + } + } + if (!ok) { #if INFER_ADDR_PREFIX - if (i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') + if (flag_code != CODE_64BIT + && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0') { i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE; i.prefixes += 1; @@ -3034,8 +3889,8 @@ i386_index_check (operand_string) FIXME. There doesn't seem to be any real need for separate Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. Removing them would probably clean up the code quite a lot. */ - if (i.types[this_operand] & (Disp16|Disp32)) - i.types[this_operand] ^= (Disp16|Disp32); + if (i.types[this_operand] & (Disp16 | Disp32)) + i.types[this_operand] ^= (Disp16 | Disp32); fudged = 1; goto tryprefix; } @@ -3046,7 +3901,7 @@ i386_index_check (operand_string) #endif as_bad (_("`%s' is not a valid %s bit base/index expression"), operand_string, - flag_16bit_code ^ (i.prefix[ADDR_PREFIX] != 0) ? "16" : "32"); + flag_code_names[flag_code]); return 0; } return 1; @@ -3159,7 +4014,7 @@ i386_operand (operand_string) } else if (is_digit_char (*op_string) || is_identifier_char (*op_string) - || *op_string == '(' ) + || *op_string == '(') { /* This is a memory reference of some sort. */ char *base_string; @@ -3249,7 +4104,7 @@ i386_operand (operand_string) if (is_space_char (*base_string)) ++base_string; } - else if (*base_string != ')' ) + else if (*base_string != ')') { as_bad (_("expecting `,' or `)' after index register in `%s'"), operand_string); @@ -3263,12 +4118,14 @@ i386_operand (operand_string) } /* Check for scale factor. */ - if (isdigit ((unsigned char) *base_string)) + if (*base_string != ')') { - if (!i386_scale (base_string)) + char *end_scale = i386_scale (base_string); + + if (!end_scale) return 0; - ++base_string; + base_string = end_scale; if (is_space_char (*base_string)) ++base_string; if (*base_string != ')') @@ -3352,8 +4209,8 @@ i386_operand (operand_string) int md_estimate_size_before_relax (fragP, segment) - register fragS *fragP; - register segT segment; + fragS *fragP; + segT segment; { /* We've already got fragP->fr_subtype right; all we have to do is check for un-relaxable symbols. On an ELF system, we can't relax @@ -3369,11 +4226,7 @@ md_estimate_size_before_relax (fragP, segment) /* Symbol is undefined in this segment, or we need to keep a reloc so that weak symbols can be overridden. */ int size = (fragP->fr_subtype & CODE16) ? 2 : 4; -#ifdef BFD_ASSEMBLER - enum bfd_reloc_code_real reloc_type; -#else - int reloc_type; -#endif + RELOC_ENUM reloc_type; unsigned char *opcode; int old_fr_fix; @@ -3387,10 +4240,10 @@ md_estimate_size_before_relax (fragP, segment) old_fr_fix = fragP->fr_fix; opcode = (unsigned char *) fragP->fr_opcode; - switch (opcode[0]) + switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)) { - case JUMP_PC_RELATIVE: - /* Make jmp (0xeb) a dword displacement jump. */ + case UNCOND_JUMP: + /* Make jmp (0xeb) a (d)word displacement jump. */ opcode[0] = 0xe9; fragP->fr_fix += size; fix_new (fragP, old_fr_fix, size, @@ -3399,9 +4252,40 @@ md_estimate_size_before_relax (fragP, segment) reloc_type); break; - default: + case COND_JUMP86: + if (size == 2 + && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC)) + { + /* Negate the condition, and branch past an + unconditional jump. */ + opcode[0] ^= 1; + opcode[1] = 3; + /* Insert an unconditional jump. */ + opcode[2] = 0xe9; + /* We added two extra opcode bytes, and have a two byte + offset. */ + fragP->fr_fix += 2 + 2; + fix_new (fragP, old_fr_fix + 2, 2, + fragP->fr_symbol, + fragP->fr_offset, 1, + reloc_type); + break; + } + /* Fall through. */ + + case COND_JUMP: + if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC) + { + fragP->fr_fix += 1; + fix_new (fragP, old_fr_fix, 1, + fragP->fr_symbol, + fragP->fr_offset, 1, + BFD_RELOC_8_PCREL); + break; + } + /* This changes the byte-displacement jump 0x7N - to the dword-displacement jump 0x0f,0x8N. */ + to the (d)word-displacement jump 0x0f,0x8N. */ opcode[1] = opcode[0] + 0x10; opcode[0] = TWO_BYTE_OPCODE_ESCAPE; /* We've added an opcode byte. */ @@ -3411,12 +4295,22 @@ md_estimate_size_before_relax (fragP, segment) fragP->fr_offset, 1, reloc_type); break; + + default: + BAD_CASE (fragP->fr_subtype); + break; } frag_wane (fragP); return fragP->fr_fix - old_fr_fix; } - /* Guess a short jump. */ - return 1; + + /* Guess size depending on current relax state. Initially the relax + state will correspond to a short jump and we return 1, because + the variable part of the frag (the branch offset) is one byte + long. However, we can relax a section more than once and in that + case we must either set fr_subtype back to the unrelaxed state, + or return the value for the appropriate branch. */ + return md_relax_table[fragP->fr_subtype].rlx_length; } /* Called after relax() is finished. @@ -3433,16 +4327,16 @@ void md_convert_frag (headers, sec, fragP) object_headers *headers ATTRIBUTE_UNUSED; segT sec ATTRIBUTE_UNUSED; - register fragS *fragP; + fragS *fragP; #else void md_convert_frag (abfd, sec, fragP) bfd *abfd ATTRIBUTE_UNUSED; segT sec ATTRIBUTE_UNUSED; - register fragS *fragP; + fragS *fragP; #endif { - register unsigned char *opcode; + unsigned char *opcode; unsigned char *where_to_put_displacement = NULL; offsetT target_address; offsetT opcode_address; @@ -3453,10 +4347,6 @@ md_convert_frag (abfd, sec, fragP) /* Address we want to reach in file space. */ target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; -#ifdef BFD_ASSEMBLER - /* Not needed otherwise? */ - target_address += symbol_get_frag (fragP->fr_symbol)->fr_address; -#endif /* Address opcode resides at in file space. */ opcode_address = fragP->fr_address + fragP->fr_fix; @@ -3464,51 +4354,65 @@ md_convert_frag (abfd, sec, fragP) /* Displacement from opcode start to fill into instruction. */ displacement_from_opcode_start = target_address - opcode_address; - switch (fragP->fr_subtype) + if ((fragP->fr_subtype & BIG) == 0) { - case ENCODE_RELAX_STATE (COND_JUMP, SMALL): - case ENCODE_RELAX_STATE (COND_JUMP, SMALL16): - case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL): - case ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL16): /* Don't have to change opcode. */ extension = 1; /* 1 opcode + 1 displacement */ where_to_put_displacement = &opcode[1]; - break; + } + else + { + if (no_cond_jump_promotion + && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP) + as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required")); - case ENCODE_RELAX_STATE (COND_JUMP, BIG): - extension = 5; /* 2 opcode + 4 displacement */ - opcode[1] = opcode[0] + 0x10; - opcode[0] = TWO_BYTE_OPCODE_ESCAPE; - where_to_put_displacement = &opcode[2]; - break; + switch (fragP->fr_subtype) + { + case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): + extension = 4; /* 1 opcode + 4 displacement */ + opcode[0] = 0xe9; + where_to_put_displacement = &opcode[1]; + break; - case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG): - extension = 4; /* 1 opcode + 4 displacement */ - opcode[0] = 0xe9; - where_to_put_displacement = &opcode[1]; - break; + case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): + extension = 2; /* 1 opcode + 2 displacement */ + opcode[0] = 0xe9; + where_to_put_displacement = &opcode[1]; + break; - case ENCODE_RELAX_STATE (COND_JUMP, BIG16): - extension = 3; /* 2 opcode + 2 displacement */ - opcode[1] = opcode[0] + 0x10; - opcode[0] = TWO_BYTE_OPCODE_ESCAPE; - where_to_put_displacement = &opcode[2]; - break; + case ENCODE_RELAX_STATE (COND_JUMP, BIG): + case ENCODE_RELAX_STATE (COND_JUMP86, BIG): + extension = 5; /* 2 opcode + 4 displacement */ + opcode[1] = opcode[0] + 0x10; + opcode[0] = TWO_BYTE_OPCODE_ESCAPE; + where_to_put_displacement = &opcode[2]; + break; - case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16): - extension = 2; /* 1 opcode + 2 displacement */ - opcode[0] = 0xe9; - where_to_put_displacement = &opcode[1]; - break; + case ENCODE_RELAX_STATE (COND_JUMP, BIG16): + extension = 3; /* 2 opcode + 2 displacement */ + opcode[1] = opcode[0] + 0x10; + opcode[0] = TWO_BYTE_OPCODE_ESCAPE; + where_to_put_displacement = &opcode[2]; + break; - default: - BAD_CASE (fragP->fr_subtype); - break; + case ENCODE_RELAX_STATE (COND_JUMP86, BIG16): + extension = 4; + opcode[0] ^= 1; + opcode[1] = 3; + opcode[2] = 0xe9; + where_to_put_displacement = &opcode[3]; + break; + + default: + BAD_CASE (fragP->fr_subtype); + break; + } } + /* Now put displacement after opcode. */ md_number_to_chars ((char *) where_to_put_displacement, (valueT) (displacement_from_opcode_start - extension), - SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); + DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)); fragP->fr_fix += extension; } @@ -3557,19 +4461,17 @@ md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) the same (little-endian) format, so we don't need to care about which we are handling. */ -int -md_apply_fix3 (fixP, valp, seg) +void +md_apply_fix3 (fixP, valP, seg) /* The fix we're to put in. */ fixS *fixP; - /* Pointer to the value of the bits. */ - valueT *valp; - + valueT * valP; /* Segment fix is from. */ segT seg ATTRIBUTE_UNUSED; { - register char *p = fixP->fx_where + fixP->fx_frag->fr_literal; - valueT value = *valp; + char *p = fixP->fx_where + fixP->fx_frag->fr_literal; + valueT value = * valP; #if defined (BFD_ASSEMBLER) && !defined (TE_Mach) if (fixP->fx_pcrel) @@ -3598,7 +4500,7 @@ md_apply_fix3 (fixP, valp, seg) if ((fixP->fx_r_type == BFD_RELOC_32_PCREL || fixP->fx_r_type == BFD_RELOC_16_PCREL || fixP->fx_r_type == BFD_RELOC_8_PCREL) - && fixP->fx_addsy) + && fixP->fx_addsy && !use_rela_relocations) { #ifndef OBJ_AOUT if (OUTPUT_FLAVOR == bfd_target_elf_flavour @@ -3616,10 +4518,10 @@ md_apply_fix3 (fixP, valp, seg) if ((fseg == seg || (symbol_section_p (fixP->fx_addsy) && fseg != absolute_section)) - && ! S_IS_EXTERNAL (fixP->fx_addsy) - && ! S_IS_WEAK (fixP->fx_addsy) + && !S_IS_EXTERNAL (fixP->fx_addsy) + && !S_IS_WEAK (fixP->fx_addsy) && S_IS_DEFINED (fixP->fx_addsy) - && ! S_IS_COMMON (fixP->fx_addsy)) + && !S_IS_COMMON (fixP->fx_addsy)) { /* Yes, we add the values in twice. This is because bfd_perform_relocation subtracts them out again. I think @@ -3645,6 +4547,7 @@ md_apply_fix3 (fixP, valp, seg) switch (fixP->fx_r_type) { case BFD_RELOC_386_PLT32: + case BFD_RELOC_X86_64_PLT32: /* Make the jump instruction point to the address of the operand. At runtime we merely add the offset to the actual PLT entry. */ value = -4; @@ -3692,25 +4595,44 @@ md_apply_fix3 (fixP, valp, seg) value -= 1; break; case BFD_RELOC_386_GOT32: + case BFD_RELOC_386_TLS_GD: + case BFD_RELOC_386_TLS_LDM: + case BFD_RELOC_386_TLS_LDO_32: + case BFD_RELOC_386_TLS_IE_32: + case BFD_RELOC_386_TLS_LE_32: + case BFD_RELOC_386_TLS_LE: + case BFD_RELOC_X86_64_GOT32: value = 0; /* Fully resolved at runtime. No addend. */ break; case BFD_RELOC_386_GOTOFF: + case BFD_RELOC_X86_64_GOTPCREL: break; case BFD_RELOC_VTABLE_INHERIT: case BFD_RELOC_VTABLE_ENTRY: fixP->fx_done = 0; - return 1; + return; default: break; } #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ - *valp = value; + * valP = value; #endif /* defined (BFD_ASSEMBLER) && !defined (TE_Mach) */ - md_number_to_chars (p, value, fixP->fx_size); - return 1; + /* Are we finished with this relocation now? */ + if (fixP->fx_addsy == NULL && fixP->fx_pcrel == 0) + fixP->fx_done = 1; +#ifdef BFD_ASSEMBLER + else if (use_rela_relocations) + { + fixP->fx_no_overflow = 1; + /* Remember value for tc_gen_reloc. */ + fixP->fx_addnumber = value; + value = 0; + } +#endif + md_number_to_chars (p, value, fixP->fx_size); } #define MAX_LITTLENUMS 6 @@ -3773,7 +4695,7 @@ static char * output_invalid (c) int c; { - if (isprint (c)) + if (ISPRINT (c)) sprintf (output_invalid_buf, "'%c'", c); else sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); @@ -3844,6 +4766,13 @@ parse_register (reg_string, end_op) } } + if (r != NULL + && (r->reg_flags & (RegRex64 | RegRex)) != 0 + && flag_code != CODE_64BIT) + { + return (const reg_entry *) NULL; + } + return r; } @@ -3852,7 +4781,14 @@ const char *md_shortopts = "kVQ:sq"; #else const char *md_shortopts = "q"; #endif + struct option md_longopts[] = { +#define OPTION_32 (OPTION_MD_BASE + 0) + {"32", no_argument, NULL, OPTION_32}, +#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) +#define OPTION_64 (OPTION_MD_BASE + 1) + {"64", no_argument, NULL, OPTION_64}, +#endif {NULL, no_argument, NULL, 0} }; size_t md_longopts_size = sizeof (md_longopts); @@ -3885,10 +4821,31 @@ md_parse_option (c, arg) case 's': /* -s: On i386 Solaris, this tells the native assembler to use - .stab instead of .stab.excl. We always use .stab anyhow. */ + .stab instead of .stab.excl. We always use .stab anyhow. */ + break; + + case OPTION_64: + { + const char **list, **l; + + list = bfd_target_list (); + for (l = list; *l != NULL; l++) + if (strcmp (*l, "elf64-x86-64") == 0) + { + default_arch = "x86_64"; + break; + } + if (*l == NULL) + as_fatal (_("No compiled in support for x86_64")); + free (list); + } break; #endif + case OPTION_32: + default_arch = "i386"; + break; + default: return 0; } @@ -3913,15 +4870,20 @@ md_show_usage (stream) } #ifdef BFD_ASSEMBLER -#if ((defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_COFF)) \ - || (defined (OBJ_MAYBE_ELF) && defined (OBJ_MAYBE_AOUT)) \ - || (defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT))) +#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ + || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) /* Pick the target format to use. */ const char * i386_target_format () { + if (!strcmp (default_arch, "x86_64")) + set_code_flag (CODE_64BIT); + else if (!strcmp (default_arch, "i386")) + set_code_flag (CODE_32BIT); + else + as_fatal (_("Unknown architecture")); switch (OUTPUT_FLAVOR) { #ifdef OBJ_MAYBE_AOUT @@ -3932,9 +4894,13 @@ i386_target_format () case bfd_target_coff_flavour: return "coff-i386"; #endif -#ifdef OBJ_MAYBE_ELF +#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF) case bfd_target_elf_flavour: - return "elf32-i386"; + { + if (flag_code == CODE_64BIT) + use_rela_relocations = 1; + return flag_code == CODE_64BIT ? "elf64-x86-64" : "elf32-i386"; + } #endif default: abort (); @@ -3943,6 +4909,48 @@ i386_target_format () } #endif /* OBJ_MAYBE_ more than one */ + +#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) +void i386_elf_emit_arch_note () +{ + if (OUTPUT_FLAVOR == bfd_target_elf_flavour + && cpu_arch_name != NULL) + { + char *p; + asection *seg = now_seg; + subsegT subseg = now_subseg; + Elf_Internal_Note i_note; + Elf_External_Note e_note; + asection *note_secp; + int len; + + /* Create the .note section. */ + note_secp = subseg_new (".note", 0); + bfd_set_section_flags (stdoutput, + note_secp, + SEC_HAS_CONTENTS | SEC_READONLY); + + /* Process the arch string. */ + len = strlen (cpu_arch_name); + + i_note.namesz = len + 1; + i_note.descsz = 0; + i_note.type = NT_ARCH; + p = frag_more (sizeof (e_note.namesz)); + md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); + p = frag_more (sizeof (e_note.descsz)); + md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); + p = frag_more (sizeof (e_note.type)); + md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type)); + p = frag_more (len + 1); + strcpy (p, cpu_arch_name); + + frag_align (2, 0, 0); + + subseg_set (seg, subseg); + } +} +#endif #endif /* BFD_ASSEMBLER */ symbolS * @@ -4010,7 +5018,7 @@ static void s_bss (ignore) int ignore ATTRIBUTE_UNUSED; { - register int temp; + int temp; temp = get_absolute_expression (); subseg_set (bss_section, (subsegT) temp); @@ -4027,7 +5035,19 @@ i386_validate_fix (fixp) { if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) { - fixp->fx_r_type = BFD_RELOC_386_GOTOFF; + /* GOTOFF relocation are nonsense in 64bit mode. */ + if (fixp->fx_r_type == BFD_RELOC_32_PCREL) + { + if (flag_code != CODE_64BIT) + abort (); + fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; + } + else + { + if (flag_code == CODE_64BIT) + abort (); + fixp->fx_r_type = BFD_RELOC_386_GOTOFF; + } fixp->fx_subsy = 0; } } @@ -4042,10 +5062,20 @@ tc_gen_reloc (section, fixp) switch (fixp->fx_r_type) { + case BFD_RELOC_X86_64_PLT32: + case BFD_RELOC_X86_64_GOT32: + case BFD_RELOC_X86_64_GOTPCREL: case BFD_RELOC_386_PLT32: case BFD_RELOC_386_GOT32: case BFD_RELOC_386_GOTOFF: case BFD_RELOC_386_GOTPC: + case BFD_RELOC_386_TLS_GD: + case BFD_RELOC_386_TLS_LDM: + case BFD_RELOC_386_TLS_LDO_32: + case BFD_RELOC_386_TLS_IE_32: + case BFD_RELOC_386_TLS_LE_32: + case BFD_RELOC_386_TLS_LE: + case BFD_RELOC_X86_64_32S: case BFD_RELOC_RVA: case BFD_RELOC_VTABLE_ENTRY: case BFD_RELOC_VTABLE_INHERIT: @@ -4057,8 +5087,9 @@ tc_gen_reloc (section, fixp) switch (fixp->fx_size) { default: - as_bad (_("can not do %d byte pc-relative relocation"), - fixp->fx_size); + as_bad_where (fixp->fx_file, fixp->fx_line, + _("can not do %d byte pc-relative relocation"), + fixp->fx_size); code = BFD_RELOC_32_PCREL; break; case 1: code = BFD_RELOC_8_PCREL; break; @@ -4071,12 +5102,17 @@ tc_gen_reloc (section, fixp) switch (fixp->fx_size) { default: - as_bad (_("can not do %d byte relocation"), fixp->fx_size); + as_bad_where (fixp->fx_file, fixp->fx_line, + _("can not do %d byte relocation"), + fixp->fx_size); code = BFD_RELOC_32; break; case 1: code = BFD_RELOC_8; break; case 2: code = BFD_RELOC_16; break; case 4: code = BFD_RELOC_32; break; +#ifdef BFD64 + case 8: code = BFD_RELOC_64; break; +#endif } } break; @@ -4085,22 +5121,51 @@ tc_gen_reloc (section, fixp) if (code == BFD_RELOC_32 && GOT_symbol && fixp->fx_addsy == GOT_symbol) - code = BFD_RELOC_386_GOTPC; + { + /* We don't support GOTPC on 64bit targets. */ + if (flag_code == CODE_64BIT) + abort (); + code = BFD_RELOC_386_GOTPC; + } rel = (arelent *) xmalloc (sizeof (arelent)); rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); rel->address = fixp->fx_frag->fr_address + fixp->fx_where; - /* HACK: Since i386 ELF uses Rel instead of Rela, encode the - vtable entry to be used in the relocation's section offset. */ - if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) - rel->address = fixp->fx_offset; + if (!use_rela_relocations) + { + /* HACK: Since i386 ELF uses Rel instead of Rela, encode the + vtable entry to be used in the relocation's section offset. */ + if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) + rel->address = fixp->fx_offset; - if (fixp->fx_pcrel) - rel->addend = fixp->fx_addnumber; + if (fixp->fx_pcrel) + rel->addend = fixp->fx_addnumber; + else + rel->addend = 0; + } + /* Use the rela in 64bit mode. */ else - rel->addend = 0; + { + if (!fixp->fx_pcrel) + rel->addend = fixp->fx_offset; + else + switch (code) + { + case BFD_RELOC_X86_64_PLT32: + case BFD_RELOC_X86_64_GOT32: + case BFD_RELOC_X86_64_GOTPCREL: + rel->addend = fixp->fx_offset - fixp->fx_size; + break; + default: + rel->addend = (section->vma + - fixp->fx_size + + fixp->fx_addnumber + + md_pcrel_from (fixp)); + break; + } + } rel->howto = bfd_reloc_type_lookup (stdoutput, code); if (rel->howto == NULL) @@ -4116,7 +5181,7 @@ tc_gen_reloc (section, fixp) return rel; } -#else /* ! BFD_ASSEMBLER */ +#else /* !BFD_ASSEMBLER */ #if (defined(OBJ_AOUT) | defined(OBJ_BOUT)) void @@ -4182,7 +5247,7 @@ tc_coff_sizemachdep (frag) #endif /* I386COFF */ -#endif /* ! BFD_ASSEMBLER */ +#endif /* !BFD_ASSEMBLER */ /* Parse operands using Intel syntax. This implements a recursive descent parser based on the BNF grammar published in Appendix B of the MASM 6.1 @@ -4210,16 +5275,16 @@ tc_coff_sizemachdep (frag) dataType BYTE | WORD | DWORD | QWORD | XWORD digits decdigit - | digits decdigit - | digits hexdigit + | digits decdigit + | digits hexdigit decdigit [0-9] e05 e05 addOp e06 - | e06 + | e06 e06 e06 mulOp e09 - | e09 + | e09 e09 OFFSET e10 | e09 PTR e10 @@ -4227,10 +5292,10 @@ tc_coff_sizemachdep (frag) | e10 e10 e10 [ expr ] - | e11 + | e11 e11 ( expr ) - | [ expr ] + | [ expr ] | constant | dataType | id @@ -4238,16 +5303,16 @@ tc_coff_sizemachdep (frag) | register => expr SHORT e05 - | e05 + | e05 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX - | BP | EBP | SP | ESP | DI | EDI | SI | ESI + | BP | EBP | SP | ESP | DI | EDI | SI | ESI hexdigit a | b | c | d | e | f - | A | B | C | D | E | F + | A | B | C | D | E | F id alpha - | id alpha + | id alpha | id decdigit mulOp * | / | MOD @@ -4255,13 +5320,13 @@ tc_coff_sizemachdep (frag) quote " | ' register specialRegister - | gpRegister + | gpRegister | byteRegister segmentRegister CS | DS | ES | FS | GS | SS specialRegister CR0 | CR2 | CR3 - | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 + | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 | TR3 | TR4 | TR5 | TR6 | TR7 We simplify the grammar in obvious places (e.g., register parsing is @@ -4269,32 +5334,32 @@ tc_coff_sizemachdep (frag) to implement a recursive-descent parser. expr SHORT e05 - | e05 + | e05 e05 e06 e05' e05' addOp e06 e05' - | Empty + | Empty e06 e09 e06' e06' mulOp e09 e06' - | Empty + | Empty e09 OFFSET e10 e09' - | e10 e09' + | e10 e09' e09' PTR e10 e09' - | : e10 e09' + | : e10 e09' | Empty e10 e11 e10' e10' [ expr ] e10' - | Empty + | Empty e11 ( expr ) - | [ expr ] + | [ expr ] | BYTE | WORD | DWORD @@ -4330,7 +5395,8 @@ struct intel_token static struct intel_token cur_token, prev_token; -/* Token codes for the intel parser. */ +/* Token codes for the intel parser. Since T_SHORT is already used + by COFF, undefine it first to prevent a warning. */ #define T_NIL -1 #define T_CONST 1 #define T_REG 2 @@ -4339,6 +5405,7 @@ static struct intel_token cur_token, prev_token; #define T_DWORD 5 #define T_QWORD 6 #define T_XWORD 7 +#undef T_SHORT #define T_SHORT 8 #define T_OFFSET 9 #define T_PTR 10 @@ -4373,7 +5440,7 @@ i386_intel_operand (operand_string, got_a_float) cur_token.str = prev_token.str = NULL; /* Initialize parser structure. */ - p = intel_parser.op_string = (char *)malloc (strlen (operand_string) + 1); + p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1); if (p == NULL) abort (); strcpy (intel_parser.op_string, operand_string); @@ -4381,7 +5448,7 @@ i386_intel_operand (operand_string, got_a_float) intel_parser.op_modifier = -1; intel_parser.is_mem = 0; intel_parser.reg = NULL; - intel_parser.disp = (char *)malloc (strlen (operand_string) + 1); + intel_parser.disp = (char *) malloc (strlen (operand_string) + 1); if (intel_parser.disp == NULL) abort (); intel_parser.disp[0] = '\0'; @@ -4429,7 +5496,7 @@ i386_intel_operand (operand_string, got_a_float) } /* expr SHORT e05 - | e05 */ + | e05 */ static int intel_expr () { @@ -4477,7 +5544,7 @@ intel_e05_1 () /* e06 e09 e06' e06' mulOp e09 e06' - | Empty */ + | Empty */ static int intel_e06 () { @@ -4502,10 +5569,10 @@ intel_e06_1 () } /* e09 OFFSET e10 e09' - | e10 e09' + | e10 e09' e09' PTR e10 e09' - | : e10 e09' + | : e10 e09' | Empty */ static int intel_e09 () @@ -4551,7 +5618,12 @@ intel_e09_1 () } else if (prev_token.code == T_QWORD) - i.suffix = DWORD_MNEM_SUFFIX; + { + if (intel_parser.got_a_float == 1) /* "f..." */ + i.suffix = LONG_MNEM_SUFFIX; + else + i.suffix = QWORD_MNEM_SUFFIX; + } else if (prev_token.code == T_XWORD) i.suffix = LONG_DOUBLE_MNEM_SUFFIX; @@ -4570,7 +5642,10 @@ intel_e09_1 () /* e09 : e10 e09' */ else if (cur_token.code == ':') { - intel_parser.is_mem = 1; + /* Mark as a memory operand only if it's not already known to be an + offset expression. */ + if (intel_parser.op_modifier != OFFSET_FLAT) + intel_parser.is_mem = 1; return (intel_match_token (':') && intel_e10 () && intel_e09_1 ()); } @@ -4583,7 +5658,7 @@ intel_e09_1 () /* e10 e11 e10' e10' [ expr ] e10' - | Empty */ + | Empty */ static int intel_e10 () { @@ -4597,13 +5672,30 @@ intel_e10_1 () if (cur_token.code == '[') { intel_match_token ('['); - intel_parser.is_mem = 1; + + /* Mark as a memory operand only if it's not already known to be an + offset expression. If it's an offset expression, we need to keep + the brace in. */ + if (intel_parser.op_modifier != OFFSET_FLAT) + intel_parser.is_mem = 1; + else + strcat (intel_parser.disp, "["); /* Add a '+' to the displacement string if necessary. */ - if (*intel_parser.disp != '\0') + if (*intel_parser.disp != '\0' + && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') strcat (intel_parser.disp, "+"); - return (intel_expr () && intel_match_token (']') && intel_e10_1 ()); + if (intel_expr () && intel_match_token (']')) + { + /* Preserve brackets when the operand is an offset expression. */ + if (intel_parser.op_modifier == OFFSET_FLAT) + strcat (intel_parser.disp, "]"); + + return intel_e10_1 (); + } + else + return 0; } /* e10' Empty */ @@ -4612,7 +5704,7 @@ intel_e10_1 () } /* e11 ( expr ) - | [ expr ] + | [ expr ] | BYTE | WORD | DWORD @@ -4633,10 +5725,10 @@ intel_e11 () strcat (intel_parser.disp, "("); if (intel_expr () && intel_match_token (')')) - { - strcat (intel_parser.disp, ")"); - return 1; - } + { + strcat (intel_parser.disp, ")"); + return 1; + } else return 0; } @@ -4645,7 +5737,14 @@ intel_e11 () else if (cur_token.code == '[') { intel_match_token ('['); - intel_parser.is_mem = 1; + + /* Mark as a memory operand only if it's not already known to be an + offset expression. If it's an offset expression, we need to keep + the brace in. */ + if (intel_parser.op_modifier != OFFSET_FLAT) + intel_parser.is_mem = 1; + else + strcat (intel_parser.disp, "["); /* Operands for jump/call inside brackets denote absolute addresses. */ if (current_templates->start->opcode_modifier & Jump @@ -4655,10 +5754,20 @@ intel_e11 () i.types[this_operand] |= JumpAbsolute; /* Add a '+' to the displacement string if necessary. */ - if (*intel_parser.disp != '\0') + if (*intel_parser.disp != '\0' + && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') strcat (intel_parser.disp, "+"); - return (intel_expr () && intel_match_token (']')); + if (intel_expr () && intel_match_token (']')) + { + /* Preserve brackets when the operand is an offset expression. */ + if (intel_parser.op_modifier == OFFSET_FLAT) + strcat (intel_parser.disp, "]"); + + return 1; + } + else + return 0; } /* e11 BYTE @@ -4683,7 +5792,11 @@ intel_e11 () { strcat (intel_parser.disp, cur_token.str); intel_match_token (cur_token.code); - intel_parser.is_mem = 1; + + /* Mark as a memory operand only if it's not already known to be an + offset expression. */ + if (intel_parser.op_modifier != OFFSET_FLAT) + intel_parser.is_mem = 1; return 1; } @@ -4814,8 +5927,7 @@ intel_e11 () /* The identifier represents a memory reference only if it's not preceded by an offset modifier. */ - if (intel_parser.op_modifier != OFFSET_FLAT - && intel_parser.op_modifier != FLAT) + if (intel_parser.op_modifier != OFFSET_FLAT) intel_parser.is_mem = 1; return 1; @@ -4823,7 +5935,7 @@ intel_e11 () /* e11 constant */ else if (cur_token.code == T_CONST - || cur_token.code == '-' + || cur_token.code == '-' || cur_token.code == '+') { char *save_str; @@ -4841,9 +5953,9 @@ intel_e11 () } } - save_str = (char *)malloc (strlen (cur_token.str) + 1); + save_str = (char *) malloc (strlen (cur_token.str) + 1); if (save_str == NULL) - abort(); + abort (); strcpy (save_str, cur_token.str); /* Get the next token to check for register scaling. */ @@ -4913,7 +6025,7 @@ intel_e11 () token from the operand string. */ static int intel_match_token (code) - int code; + int code; { if (cur_token.code == code) { @@ -4959,9 +6071,9 @@ intel_get_token () /* The new token cannot be larger than the remainder of the operand string. */ - new_token.str = (char *)malloc (strlen (intel_parser.op_string) + 1); + new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1); if (new_token.str == NULL) - abort(); + abort (); new_token.str[0] = '\0'; if (strchr ("0123456789", *intel_parser.op_string))