X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fconfig%2Ftc-m68hc11.c;h=2586902ff1344f0c537a6700d102db6f01f1d03f;hb=c9e03e8be9f3e216d282f5ad02c0b8c8d15405ed;hp=c0549ab7dda0fc73b2250c7fe0d9747f173131b8;hpb=85a396941012a60ef70ccc3de7de675e67d31325;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/config/tc-m68hc11.c b/gas/config/tc-m68hc11.c index c0549ab7dd..2586902ff1 100644 --- a/gas/config/tc-m68hc11.c +++ b/gas/config/tc-m68hc11.c @@ -1,6 +1,6 @@ /* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12. - Copyright (C) 1999, 2000 Free Software Foundation. - Written by Stephane Carrez (stcarrez@worldnet.fr) + Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) This file is part of GAS, the GNU Assembler. @@ -20,11 +20,12 @@ Boston, MA 02111-1307, USA. */ #include -#include #include "as.h" +#include "safe-ctype.h" #include "subsegs.h" #include "opcode/m68hc11.h" #include "dwarf2dbg.h" +#include "elf/m68hc11.h" const char comment_chars[] = ";!"; const char line_comment_chars[] = "#*"; @@ -49,6 +50,8 @@ const char FLT_CHARS[] = "dD"; /* This macro has no side-effects. */ #define ENCODE_RELAX(what,length) (((what) << 2) + (length)) +#define RELAX_STATE(s) ((s) >> 2) +#define RELAX_LENGTH(s) ((s) & 3) #define IS_OPCODE(C1,C2) (((C1) & 0x0FF) == ((C2) & 0x0FF)) @@ -61,8 +64,7 @@ const char FLT_CHARS[] = "dD"; How many bytes this mode will add to the size of the frag. Which mode to go to if the offset won't fit in this one. */ -relax_typeS md_relax_table[] = -{ +relax_typeS md_relax_table[] = { {1, 1, 0, 0}, /* First entries aren't used. */ {1, 1, 0, 0}, /* For no good reason except. */ {1, 1, 0, 0}, /* that the VAX doesn't either. */ @@ -85,7 +87,7 @@ relax_typeS md_relax_table[] = /* Relax for indexed offset: 5-bits, 9-bits, 16-bits. */ {(15), (-16), 0, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9)}, {(255), (-256), 1, ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16)}, - {0, 0, 1, 0}, + {0, 0, 2, 0}, {1, 1, 0, 0}, /* Relax for dbeq/ibeq/tbeq r,: @@ -105,8 +107,7 @@ relax_typeS md_relax_table[] = }; /* 68HC11 and 68HC12 registers. They are numbered according to the 68HC12. */ -typedef enum register_id -{ +typedef enum register_id { REG_NONE = -1, REG_A = 0, REG_B = 1, @@ -118,16 +119,14 @@ typedef enum register_id REG_PC = 8 } register_id; -typedef struct operand -{ +typedef struct operand { expressionS exp; register_id reg1; register_id reg2; int mode; } operand; -struct m68hc11_opcode_def -{ +struct m68hc11_opcode_def { long format; int min_operands; int max_operands; @@ -139,15 +138,12 @@ struct m68hc11_opcode_def static struct m68hc11_opcode_def *m68hc11_opcode_defs = 0; static int m68hc11_nb_opcode_defs = 0; -typedef struct alias -{ +typedef struct alias { const char *name; const char *alias; -} -alias; +} alias; -static alias alias_opcodes[] = -{ +static alias alias_opcodes[] = { {"cpd", "cmpd"}, {"cpx", "cmpx"}, {"cpy", "cmpy"}, @@ -157,6 +153,10 @@ static alias alias_opcodes[] = /* Local functions. */ static register_id reg_name_search PARAMS ((char *)); static register_id register_name PARAMS ((void)); +static int cmp_opcode PARAMS ((struct m68hc11_opcode *, + struct m68hc11_opcode *)); +static char *print_opcode_format PARAMS ((struct m68hc11_opcode *, int)); +static char *skip_whites PARAMS ((char *)); static int check_range PARAMS ((long, int)); static void print_opcode_list PARAMS ((void)); static void get_default_target PARAMS ((void)); @@ -164,12 +164,35 @@ static void print_insn_format PARAMS ((char *)); static int get_operand PARAMS ((operand *, int, long)); static void fixup8 PARAMS ((expressionS *, int, int)); static void fixup16 PARAMS ((expressionS *, int, int)); +static void fixup24 PARAMS ((expressionS *, int, int)); +static unsigned char convert_branch PARAMS ((unsigned char)); +static char *m68hc11_new_insn PARAMS ((int)); +static void build_dbranch_insn PARAMS ((struct m68hc11_opcode *, + operand *, int, int)); +static int build_indexed_byte PARAMS ((operand *, int, int)); +static int build_reg_mode PARAMS ((operand *, int)); + +static struct m68hc11_opcode *find + PARAMS ((struct m68hc11_opcode_def *, operand *, int)); static struct m68hc11_opcode *find_opcode PARAMS ((struct m68hc11_opcode_def *, operand *, int *)); static void build_jump_insn PARAMS ((struct m68hc11_opcode *, operand *, int, int)); static void build_insn PARAMS ((struct m68hc11_opcode *, operand *, int)); +static int relaxable_symbol PARAMS ((symbolS *)); + +/* Pseudo op to indicate a relax group. */ +static void s_m68hc11_relax PARAMS((int)); + +/* Pseudo op to control the ELF flags. */ +static void s_m68hc11_mode PARAMS ((int)); + +/* Mark the symbols with STO_M68HC12_FAR to indicate the functions + are using 'rtc' for returning. It is necessary to use 'call' + to invoke them. This is also used by the debugger to correctly + find the stack frame. */ +static void s_m68hc11_mark_symbol PARAMS ((int)); /* Controls whether relative branches can be turned into long branches. When the relative offset is too large, the insn are changed: @@ -218,6 +241,9 @@ static int num_opcodes; /* The opcodes sorted by name and filtered by current cpu. */ static struct m68hc11_opcode *m68hc11_sorted_opcodes; +/* ELF flags to set in the output file header. */ +static int elf_flags = E_M68HC11_F64; + /* These are the machine dependent pseudo-ops. These are included so the assembler can work on the output from the SUN C compiler, which generates these. */ @@ -227,25 +253,40 @@ static struct m68hc11_opcode *m68hc11_sorted_opcodes; pseudo-op name without dot function to call to execute this pseudo-op Integer arg to pass to the function. */ -const pseudo_typeS md_pseudo_table[] = -{ +const pseudo_typeS md_pseudo_table[] = { /* The following pseudo-ops are supported for MRI compatibility. */ {"fcb", cons, 1}, {"fdb", cons, 2}, {"fcc", stringer, 1}, {"rmb", s_space, 0}, - {"file", dwarf2_directive_file, 0}, + + /* Dwarf2 support for Gcc. */ + {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0}, {"loc", dwarf2_directive_loc, 0}, + /* Motorola ALIS. */ + {"xrefb", s_ignore, 0}, /* Same as xref */ + + /* Gcc driven relaxation. */ + {"relax", s_m68hc11_relax, 0}, + + /* .mode instruction (ala SH). */ + {"mode", s_m68hc11_mode, 0}, + + /* .far instruction. */ + {"far", s_m68hc11_mark_symbol, STO_M68HC12_FAR}, + + /* .interrupt instruction. */ + {"interrupt", s_m68hc11_mark_symbol, STO_M68HC12_INTERRUPT}, + {0, 0, 0} }; /* Options and initialization. */ -CONST char *md_shortopts = "Sm:"; +const char *md_shortopts = "Sm:"; -struct option md_longopts[] = -{ +struct option md_longopts[] = { #define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE) {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, @@ -264,6 +305,18 @@ struct option md_longopts[] = #define OPTION_GENERATE_EXAMPLE (OPTION_MD_BASE + 5) {"generate-example", no_argument, NULL, OPTION_GENERATE_EXAMPLE}, +#define OPTION_MSHORT (OPTION_MD_BASE + 6) + {"mshort", no_argument, NULL, OPTION_MSHORT}, + +#define OPTION_MLONG (OPTION_MD_BASE + 7) + {"mlong", no_argument, NULL, OPTION_MLONG}, + +#define OPTION_MSHORT_DOUBLE (OPTION_MD_BASE + 8) + {"mshort-double", no_argument, NULL, OPTION_MSHORT_DOUBLE}, + +#define OPTION_MLONG_DOUBLE (OPTION_MD_BASE + 9) + {"mlong-double", no_argument, NULL, OPTION_MLONG_DOUBLE}, + {NULL, no_argument, NULL, 0} }; size_t md_longopts_size = sizeof (md_longopts); @@ -297,6 +350,16 @@ m68hc11_mach () return 0; } +/* Listing header selected according to cpu. */ +const char * +m68hc11_listing_header () +{ + if (current_architecture & cpu6811) + return "M68HC11 GAS "; + else + return "M68HC12 GAS "; +} + void md_show_usage (stream) FILE *stream; @@ -305,6 +368,10 @@ md_show_usage (stream) fprintf (stream, _("\ Motorola 68HC11/68HC12 options:\n\ -m68hc11 | -m68hc12 specify the processor [default %s]\n\ + -mshort use 16-bit int ABI (default)\n\ + -mlong use 32-bit int ABI\n\ + -mshort-double use 32-bit double ABI\n\ + -mlong-double use 64-bit double ABI (default)\n\ --force-long-branchs always turn relative branchs into absolute ones\n\ -S,--short-branchs do not turn relative branchs into absolute ones\n\ when the offset is out of range\n\ @@ -380,7 +447,7 @@ md_parse_option (c, arg) get_default_target (); switch (c) { - /* -S means keep external to 2 bits offset rather than 16 bits one. */ + /* -S means keep external to 2 bit offset rather than 16 bit one. */ case OPTION_SHORT_BRANCHS: case 'S': flag_fixed_branchs = 1; @@ -406,6 +473,22 @@ md_parse_option (c, arg) flag_print_opcodes = 2; break; + case OPTION_MSHORT: + elf_flags &= ~E_M68HC11_I32; + break; + + case OPTION_MLONG: + elf_flags |= E_M68HC11_I32; + break; + + case OPTION_MSHORT_DOUBLE: + elf_flags &= ~E_M68HC11_F64; + break; + + case OPTION_MLONG_DOUBLE: + elf_flags |= E_M68HC11_F64; + break; + case 'm': if (strcasecmp (arg, "68hc11") == 0) current_architecture = cpu6811; @@ -507,6 +590,10 @@ cmp_opcode (op1, op2) return strcmp (op1->name, op2->name); } +#define IS_CALL_SYMBOL(MODE) \ +(((MODE) & (M6812_OP_PAGE|M6811_OP_IND16)) \ + == ((M6812_OP_PAGE|M6811_OP_IND16))) + /* Initialize the assembler. Create the opcode hash table (sorted on the names) with the M6811 opcode table (from opcode library). */ @@ -591,9 +678,15 @@ md_begin () expect++; if (opcodes->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)) expect++; + /* Special case for call instruction. */ + if ((opcodes->format & M6812_OP_PAGE) + && !(opcodes->format & M6811_OP_IND16)) + expect++; if (expect < opc->min_operands) opc->min_operands = expect; + if (IS_CALL_SYMBOL (opcodes->format)) + expect++; if (expect > opc->max_operands) opc->max_operands = expect; } @@ -673,6 +766,15 @@ print_opcode_format (opcode, example) p = &p[strlen (p)]; } + if (format & M6812_OP_PAGE) + { + if (example) + sprintf (p, ", %d", rand () & 0x0FF); + else + strcpy (p, ", "); + p = &p[strlen (p)]; + } + if (format & M6811_OP_DIRECT) { if (example) @@ -795,7 +897,7 @@ print_insn_format (name) { char *fmt; - fmt = print_opcode_format (opcode, 0, 0); + fmt = print_opcode_format (opcode, 0); sprintf (buf, "\t%-5.5s %s", opcode->name, fmt); as_bad ("%s", buf); @@ -878,19 +980,19 @@ register_name () /* Parse a string of operands and return an array of expressions. - Operand mode[0] mode[1] exp[0] exp[1] - #n M6811_OP_IMM16 - O_* - * M6811_OP_DIRECT - O_* - .{+-} M6811_OP_JUMP_REL - O_* - M6811_OP_IND16 - O_* - ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register - n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register - n,+r M6812_PRE_INC " " - n,r- M6812_POST_DEC " " - n,r+ M6812_POST_INC " " - A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register - [D,r] M6811_OP_IDX_2 M6812_OP_REG O_register O_register - [n,r] M6811_OP_IDX_1 M6812_OP_REG O_constant O_register */ + Operand mode[0] mode[1] exp[0] exp[1] + #n M6811_OP_IMM16 - O_* + * M6811_OP_DIRECT - O_* + .{+-} M6811_OP_JUMP_REL - O_* + M6811_OP_IND16 - O_* + ,r N,r M6812_OP_IDX M6812_OP_REG O_constant O_register + n,-r M6812_PRE_DEC M6812_OP_REG O_constant O_register + n,+r M6812_PRE_INC " " + n,r- M6812_POST_DEC " " + n,r+ M6812_POST_INC " " + A,r B,r D,r M6811_OP_REG M6812_OP_REG O_register O_register + [D,r] M6811_OP_D_IDX M6812_OP_REG O_register O_register + [n,r] M6811_OP_D_IDX_2 M6812_OP_REG O_constant O_register */ static int get_operand (oper, which, opmode) operand *oper; @@ -952,7 +1054,7 @@ get_operand (oper, which, opmode) as_bad (_("Indirect indexed addressing is not valid for 68HC11.")); p++; - mode = M6812_OP_IDX_2; + mode = M6812_OP_D_IDX; p = skip_whites (p); } else if (*p == ',') /* Special handling of ,x and ,y. */ @@ -974,7 +1076,7 @@ get_operand (oper, which, opmode) } input_line_pointer = p; - if (mode == M6811_OP_NONE || mode == M6812_OP_IDX_2) + if (mode == M6811_OP_NONE || mode == M6812_OP_D_IDX) reg = register_name (); else reg = REG_NONE; @@ -982,7 +1084,7 @@ get_operand (oper, which, opmode) if (reg != REG_NONE) { p = skip_whites (input_line_pointer); - if (*p == ']' && mode == M6812_OP_IDX_2) + if (*p == ']' && mode == M6812_OP_D_IDX) { as_bad (_("Missing second register or offset for indexed-indirect mode.")); @@ -993,7 +1095,7 @@ get_operand (oper, which, opmode) oper->mode = mode | M6812_OP_REG; if (*p != ',') { - if (mode == M6812_OP_IDX_2) + if (mode == M6812_OP_D_IDX) { as_bad (_("Missing second register for indexed-indirect mode.")); return -1; @@ -1007,7 +1109,7 @@ get_operand (oper, which, opmode) if (reg != REG_NONE) { p = skip_whites (input_line_pointer); - if (mode == M6812_OP_IDX_2) + if (mode == M6812_OP_D_IDX) { if (*p != ']') { @@ -1015,6 +1117,7 @@ get_operand (oper, which, opmode) return -1; } p++; + oper->mode = M6812_OP_D_IDX; } input_line_pointer = p; @@ -1067,12 +1170,16 @@ get_operand (oper, which, opmode) p = input_line_pointer; if (mode == M6811_OP_NONE || mode == M6811_OP_DIRECT - || mode == M6812_OP_IDX_2) + || mode == M6812_OP_D_IDX) { p = skip_whites (input_line_pointer); if (*p == ',') { + int possible_mode = M6811_OP_NONE; + char *old_input_line; + + old_input_line = p; p++; /* 68HC12 pre increment or decrement. */ @@ -1080,23 +1187,36 @@ get_operand (oper, which, opmode) { if (*p == '-') { - mode = M6812_PRE_DEC; + possible_mode = M6812_PRE_DEC; p++; - if (current_architecture & cpu6811) - as_bad (_("Pre-decrement mode is not valid for 68HC11")); } else if (*p == '+') { - mode = M6812_PRE_INC; + possible_mode = M6812_PRE_INC; p++; - if (current_architecture & cpu6811) - as_bad (_("Pre-increment mode is not valid for 68HC11")); } p = skip_whites (p); } input_line_pointer = p; reg = register_name (); + /* Backtrack if we have a valid constant expression and + it does not correspond to the offset of the 68HC12 indexed + addressing mode (as in N,x). */ + if (reg == REG_NONE && mode == M6811_OP_NONE + && possible_mode != M6811_OP_NONE) + { + oper->mode = M6811_OP_IND16 | M6811_OP_JUMP_REL; + input_line_pointer = skip_whites (old_input_line); + return 1; + } + + if (possible_mode != M6811_OP_NONE) + mode = possible_mode; + + if ((current_architecture & cpu6811) + && possible_mode != M6811_OP_NONE) + as_bad (_("Pre-increment mode is not valid for 68HC11")); /* Backtrack. */ if (which == 0 && opmode & M6812_OP_IDX_P2 && reg != REG_X && reg != REG_Y @@ -1112,7 +1232,7 @@ get_operand (oper, which, opmode) as_bad (_("Wrong register in register indirect mode.")); return -1; } - if (mode == M6812_OP_IDX_2) + if (mode == M6812_OP_D_IDX) { p = skip_whites (input_line_pointer); if (*p++ != ']') @@ -1121,6 +1241,9 @@ get_operand (oper, which, opmode) return -1; } input_line_pointer = p; + oper->reg1 = reg; + oper->mode = M6812_OP_D_IDX_2; + return 1; } if (reg != REG_NONE) { @@ -1155,6 +1278,7 @@ get_operand (oper, which, opmode) oper->mode = mode; return 1; } + input_line_pointer = old_input_line; } if (mode == M6812_OP_D_IDX_2) @@ -1191,13 +1315,14 @@ check_range (num, mode) if (mode & M6812_AUTO_INC_DEC) return (num != 0 && num <= 8 && num >= -8); - /* The 68HC12 supports 5, 9 and 16-bits offsets. */ + /* The 68HC12 supports 5, 9 and 16-bit offsets. */ if (mode & (M6812_INDEXED_IND | M6812_INDEXED | M6812_OP_IDX)) mode = M6811_OP_IND16; if (mode & M6812_OP_JUMP_REL16) mode = M6811_OP_IND16; + mode &= ~M6811_OP_BRANCH; switch (mode) { case M6811_OP_IX: @@ -1207,6 +1332,7 @@ check_range (num, mode) case M6811_OP_BITMASK: case M6811_OP_IMM8: + case M6812_OP_PAGE: return (((num & 0xFFFFFF00) == 0) || ((num & 0xFFFFFF00) == 0xFFFFFF00)) ? 1 : 0; @@ -1214,6 +1340,7 @@ check_range (num, mode) return (num >= -128 && num <= 127) ? 1 : 0; case M6811_OP_IND16: + case M6811_OP_IND16 | M6812_OP_PAGE: case M6811_OP_IMM16: return (((num & 0xFFFF0000) == 0) || ((num & 0xFFFF0000) == 0xFFFF0000)) ? 1 : 0; @@ -1278,7 +1405,7 @@ fixup8 (oper, mode, opmode) fixS *fixp; fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 1, - oper, true, BFD_RELOC_8_PCREL); + oper, TRUE, BFD_RELOC_8_PCREL); fixp->fx_pcrel_adjust = 1; } else @@ -1286,11 +1413,13 @@ fixup8 (oper, mode, opmode) /* Now create an 8-bit fixup. If there was some %hi or %lo modifier, generate the reloc accordingly. */ fix_new_exp (frag_now, f - frag_now->fr_literal, 1, - oper, false, + oper, FALSE, ((opmode & M6811_OP_HIGH_ADDR) ? BFD_RELOC_M68HC11_HI8 : ((opmode & M6811_OP_LOW_ADDR) - ? BFD_RELOC_M68HC11_LO8 : BFD_RELOC_8))); + ? BFD_RELOC_M68HC11_LO8 + : ((mode & M6812_OP_PAGE) + ? BFD_RELOC_M68HC11_PAGE : BFD_RELOC_8)))); } number_to_chars_bigendian (f, 0, 1); } @@ -1300,7 +1429,7 @@ fixup8 (oper, mode, opmode) } } -/* Put a 2 bytes expression described by 'oper'. If this expression contains +/* Put a 2 byte expression described by 'oper'. If this expression contains unresolved symbols, generate a 16-bit fixup. */ static void fixup16 (oper, mode, opmode) @@ -1328,9 +1457,11 @@ fixup16 (oper, mode, opmode) /* Now create a 16-bit fixup. */ fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2, oper, - (mode & M6812_OP_JUMP_REL16 ? true : false), + (mode & M6812_OP_JUMP_REL16 ? TRUE : FALSE), (mode & M6812_OP_JUMP_REL16 - ? BFD_RELOC_16_PCREL : BFD_RELOC_16)); + ? BFD_RELOC_16_PCREL + : (mode & M6812_OP_PAGE) + ? BFD_RELOC_M68HC11_LO16 : BFD_RELOC_16)); number_to_chars_bigendian (f, 0, 2); if (mode & M6812_OP_JUMP_REL16) fixp->fx_pcrel_adjust = 2; @@ -1340,6 +1471,42 @@ fixup16 (oper, mode, opmode) as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op); } } + +/* Put a 3 byte expression described by 'oper'. If this expression contains + unresolved symbols, generate a 24-bit fixup. */ +static void +fixup24 (oper, mode, opmode) + expressionS *oper; + int mode; + int opmode ATTRIBUTE_UNUSED; +{ + char *f; + + f = frag_more (3); + + if (oper->X_op == O_constant) + { + if (!check_range (oper->X_add_number, mode)) + { + as_bad (_("Operand out of 16-bit range: `%ld'."), + oper->X_add_number); + } + number_to_chars_bigendian (f, oper->X_add_number & 0x0FFFFFF, 3); + } + else if (oper->X_op != O_register) + { + fixS *fixp; + + /* Now create a 24-bit fixup. */ + fixp = fix_new_exp (frag_now, f - frag_now->fr_literal, 2, + oper, FALSE, BFD_RELOC_M68HC11_24); + number_to_chars_bigendian (f, 0, 3); + } + else + { + as_fatal (_("Operand `%x' not recognized in fixup16."), oper->X_op); + } +} /* 68HC11 and 68HC12 code generation. */ @@ -1371,9 +1538,7 @@ m68hc11_new_insn (size) f = frag_more (size); - /* Emit line number information in dwarf2 debug sections. */ - if (debug_type == DEBUG_DWARF2) - dwarf2_generate_asm_lineno (size); + dwarf2_emit_insn (size); return f; } @@ -1387,9 +1552,10 @@ build_jump_insn (opcode, operands, nb_operands, jmp_mode) int jmp_mode; { unsigned char code; - int insn_size; char *f; unsigned long n; + fragS *frag; + int where; /* The relative branch convertion is not supported for brclr and brset. */ @@ -1398,7 +1564,6 @@ build_jump_insn (opcode, operands, nb_operands, jmp_mode) assert (operands[0].reg1 == REG_NONE && operands[0].reg2 == REG_NONE); code = opcode->opcode; - insn_size = 1; n = operands[0].exp.X_add_number; @@ -1411,6 +1576,12 @@ build_jump_insn (opcode, operands, nb_operands, jmp_mode) && (!check_range (n, opcode->format) && (jmp_mode == 1 || flag_fixed_branchs == 0)))) { + frag = frag_now; + where = frag_now_fix (); + + fix_new (frag_now, frag_now_fix (), 1, + &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP); + if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR) { code = convert_branch (code); @@ -1465,6 +1636,12 @@ build_jump_insn (opcode, operands, nb_operands, jmp_mode) } else if (opcode->format & M6812_OP_JUMP_REL16) { + frag = frag_now; + where = frag_now_fix (); + + fix_new (frag_now, frag_now_fix (), 1, + &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP); + f = m68hc11_new_insn (2); number_to_chars_bigendian (f, M6811_OPCODE_PAGE2, 1); number_to_chars_bigendian (f + 1, code, 1); @@ -1474,6 +1651,12 @@ build_jump_insn (opcode, operands, nb_operands, jmp_mode) { char *opcode; + frag = frag_now; + where = frag_now_fix (); + + fix_new (frag_now, frag_now_fix (), 1, + &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP); + /* Branch offset must fit in 8-bits, don't do some relax. */ if (jmp_mode == 0 && flag_fixed_branchs) { @@ -1485,12 +1668,14 @@ build_jump_insn (opcode, operands, nb_operands, jmp_mode) /* bra/bsr made be changed into jmp/jsr. */ else if (code == M6811_BSR || code == M6811_BRA || code == M6812_BSR) { - opcode = m68hc11_new_insn (2); + /* Allocate worst case storage. */ + opcode = m68hc11_new_insn (3); number_to_chars_bigendian (opcode, code, 1); number_to_chars_bigendian (opcode + 1, 0, 1); - frag_var (rs_machine_dependent, 2, 1, - ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF), - operands[0].exp.X_add_symbol, (offsetT) n, opcode); + frag_variant (rs_machine_dependent, 1, 1, + ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF), + operands[0].exp.X_add_symbol, (offsetT) n, + opcode); } else if (current_architecture & cpu6812) { @@ -1522,7 +1707,6 @@ build_dbranch_insn (opcode, operands, nb_operands, jmp_mode) int jmp_mode; { unsigned char code; - int insn_size; char *f; unsigned long n; @@ -1533,7 +1717,6 @@ build_dbranch_insn (opcode, operands, nb_operands, jmp_mode) assert (operands[0].reg1 != REG_NONE); code = opcode->opcode & 0x0FF; - insn_size = 1; f = m68hc11_new_insn (1); number_to_chars_bigendian (f, code, 1); @@ -1669,7 +1852,7 @@ build_indexed_byte (op, format, move_insn) return 1; } - if (mode & M6812_OP_IDX) + if (mode & (M6812_OP_IDX | M6812_OP_D_IDX_2)) { switch (op->reg1) { @@ -1702,11 +1885,12 @@ build_indexed_byte (op, format, move_insn) if (move_insn && !(val >= -16 && val <= 15)) { - as_bad (_("Offset out of 5-bit range for movw/movb insn.")); + as_bad (_("Offset out of 5-bit range for movw/movb insn: %ld."), + val); return -1; } - if (val >= -16 && val <= 15 && !(mode & M6812_OP_IDX_2)) + if (val >= -16 && val <= 15 && !(mode & M6812_OP_D_IDX_2)) { byte = byte << 6; byte |= val & 0x1f; @@ -1714,7 +1898,7 @@ build_indexed_byte (op, format, move_insn) number_to_chars_bigendian (f, byte, 1); return 1; } - else if (val >= -256 && val <= 255 && !(mode & M6812_OP_IDX_2)) + else if (val >= -256 && val <= 255 && !(mode & M6812_OP_D_IDX_2)) { byte = byte << 3; byte |= 0xe0; @@ -1728,7 +1912,7 @@ build_indexed_byte (op, format, move_insn) else { byte = byte << 3; - if (mode & M6812_OP_IDX_2) + if (mode & M6812_OP_D_IDX_2) byte |= 0xe3; else byte |= 0xe2; @@ -1739,21 +1923,47 @@ build_indexed_byte (op, format, move_insn) return 3; } } - f = frag_more (1); - number_to_chars_bigendian (f, byte, 1); -#if 0 - fix_new_exp (frag_now, f - frag_now->fr_literal, 2, - &op->exp, false, BFD_RELOC_16); -#endif - frag_var (rs_machine_dependent, 2, 2, - ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF), - op->exp.X_add_symbol, val, f); + if (mode & M6812_OP_D_IDX_2) + { + byte = (byte << 3) | 0xe3; + f = frag_more (1); + number_to_chars_bigendian (f, byte, 1); + + fixup16 (&op->exp, 0, 0); + } + else if (op->reg1 != REG_PC) + { + symbolS *sym; + offsetT off; + + f = frag_more (1); + number_to_chars_bigendian (f, byte, 1); + sym = op->exp.X_add_symbol; + off = op->exp.X_add_number; + if (op->exp.X_op != O_symbol) + { + sym = make_expr_symbol (&op->exp); + off = 0; + } + frag_var (rs_machine_dependent, 2, 2, + ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF), + sym, off, f); + } + else + { + f = frag_more (1); + number_to_chars_bigendian (f, byte, 1); + frag_var (rs_machine_dependent, 2, 2, + ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF), + op->exp.X_add_symbol, + op->exp.X_add_number, f); + } return 3; } - if (mode & M6812_OP_REG) + if (mode & (M6812_OP_REG | M6812_OP_D_IDX)) { - if (mode & M6812_OP_IDX_2) + if (mode & M6812_OP_D_IDX) { if (op->reg1 != REG_D) as_bad (_("Expecting register D for indexed indirect mode.")); @@ -1855,12 +2065,16 @@ build_insn (opcode, operands, nb_operands) { int i; char *f; - int insn_size = 1; long format; int move_insn = 0; /* Put the page code instruction if there is one. */ format = opcode->format; + + if (format & M6811_OP_BRANCH) + fix_new (frag_now, frag_now_fix (), 1, + &abs_symbol, 0, 1, BFD_RELOC_M68HC11_RL_JUMP); + if (format & OP_EXTENDED) { int page_code; @@ -1875,7 +2089,6 @@ build_insn (opcode, operands, nb_operands) number_to_chars_bigendian (f, page_code, 1); f++; - insn_size = 2; } else f = m68hc11_new_insn (1); @@ -1891,13 +2104,13 @@ build_insn (opcode, operands, nb_operands) move_insn = 1; if (format & M6812_OP_IDX) { - insn_size += build_indexed_byte (&operands[0], format, 1); + build_indexed_byte (&operands[0], format, 1); i = 1; format &= ~M6812_OP_IDX; } if (format & M6812_OP_IDX_P2) { - insn_size += build_indexed_byte (&operands[1], format, 1); + build_indexed_byte (&operands[1], format, 1); i = 0; format &= ~M6812_OP_IDX_P2; } @@ -1905,16 +2118,22 @@ build_insn (opcode, operands, nb_operands) if (format & (M6811_OP_DIRECT | M6811_OP_IMM8)) { - insn_size++; fixup8 (&operands[i].exp, format & (M6811_OP_DIRECT | M6811_OP_IMM8 | M6812_OP_TRAP_ID), operands[i].mode); i++; } + else if (IS_CALL_SYMBOL (format) && nb_operands == 1) + { + format &= ~M6812_OP_PAGE; + fixup24 (&operands[i].exp, format & M6811_OP_IND16, + operands[i].mode); + i++; + } else if (format & (M6811_OP_IMM16 | M6811_OP_IND16)) { - insn_size += 2; - fixup16 (&operands[i].exp, format & (M6811_OP_IMM16 | M6811_OP_IND16), + fixup16 (&operands[i].exp, + format & (M6811_OP_IMM16 | M6811_OP_IND16 | M6812_OP_PAGE), operands[i].mode); i++; } @@ -1925,38 +2144,38 @@ build_insn (opcode, operands, nb_operands) if ((format & M6811_OP_IY) && (operands[0].reg1 != REG_Y)) as_bad (_("Invalid indexed register, expecting register Y.")); - insn_size++; fixup8 (&operands[0].exp, M6811_OP_IX, operands[0].mode); i = 1; } else if (format & - (M6812_OP_IDX | M6812_OP_IDX_2 | M6812_OP_IDX_1 | M6812_OP_D_IDX)) + (M6812_OP_IDX | M6812_OP_IDX_2 | M6812_OP_IDX_1 + | M6812_OP_D_IDX | M6812_OP_D_IDX_2)) { - insn_size += build_indexed_byte (&operands[i], format, move_insn); + build_indexed_byte (&operands[i], format, move_insn); i++; } else if (format & M6812_OP_REG && current_architecture & cpu6812) { - insn_size += build_reg_mode (&operands[i], format); + build_reg_mode (&operands[i], format); i++; } if (format & M6811_OP_BITMASK) { - insn_size++; fixup8 (&operands[i].exp, M6811_OP_BITMASK, operands[i].mode); i++; } if (format & M6811_OP_JUMP_REL) { - insn_size++; fixup8 (&operands[i].exp, M6811_OP_JUMP_REL, operands[i].mode); - i++; } else if (format & M6812_OP_IND16_P2) { - insn_size += 2; fixup16 (&operands[1].exp, M6811_OP_IND16, operands[1].mode); } + if (format & M6812_OP_PAGE) + { + fixup8 (&operands[i].exp, M6812_OP_PAGE, operands[i].mode); + } } /* Opcode identification and operand analysis. */ @@ -1995,6 +2214,9 @@ find (opc, operands, nb_operands) expect++; if (opcode->format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2)) expect++; + if ((opcode->format & M6812_OP_PAGE) + && (!IS_CALL_SYMBOL (opcode->format) || nb_operands == 2)) + expect++; for (i = 0; expect == nb_operands && i < nb_operands; i++) { @@ -2027,6 +2249,8 @@ find (opc, operands, nb_operands) { if (i == 0 && (format & M6811_OP_IND16) != 0) continue; + if (i != 0 && (format & M6812_OP_PAGE) != 0) + continue; if (i != 0 && (format & M6812_OP_IND16_P2) != 0) continue; if (i == 0 && (format & M6811_OP_BITMASK)) @@ -2052,9 +2276,6 @@ find (opc, operands, nb_operands) && (format & M6812_OP_IDX) && (operands[i].reg2 != REG_NONE)) continue; - if (i == 0 - && (format & M6812_OP_D_IDX)) - continue; if (i == 0 && (format & M6812_OP_IDX) && (format & (M6812_OP_IND16_P2 | M6812_OP_IDX_P2))) @@ -2080,6 +2301,11 @@ find (opc, operands, nb_operands) if (i == 1 && format & M6812_OP_IDX_P2) continue; } + if (mode & format & (M6812_OP_D_IDX | M6812_OP_D_IDX_2)) + { + if (i == 0) + continue; + } if (mode & M6812_AUTO_INC_DEC) { if (i == 0 @@ -2167,7 +2393,10 @@ find_opcode (opc, operands, nb_operands) if (i >= opc->min_operands) { opcode = find (opc, operands, i); - if (opcode) + if (opcode && !(opcode->format & M6812_OP_PAGE)) + return opcode; + + if (opcode && *input_line_pointer != ',') return opcode; } @@ -2213,7 +2442,7 @@ md_assemble (str) *op_end && nlen < 20 && !is_end_of_line[*op_end] && *op_end != ' '; op_end++) { - name[nlen] = tolower (op_start[nlen]); + name[nlen] = TOLOWER (op_start[nlen]); nlen++; } name[nlen] = 0; @@ -2255,14 +2484,14 @@ md_assemble (str) && (*op_end && (is_end_of_line[op_end[1]] || op_end[1] == ' ' || op_end[1] == '\t' - || !isalnum (op_end[1]))) + || !ISALNUM (op_end[1]))) && (*op_end == 'a' || *op_end == 'b' || *op_end == 'A' || *op_end == 'B' || *op_end == 'd' || *op_end == 'D' || *op_end == 'x' || *op_end == 'X' || *op_end == 'y' || *op_end == 'Y')) { - name[nlen++] = tolower (*op_end++); + name[nlen++] = TOLOWER (*op_end++); name[nlen] = 0; opc = (struct m68hc11_opcode_def *) hash_find (m68hc11_hash, name); @@ -2271,7 +2500,7 @@ md_assemble (str) } /* Identify a possible instruction alias. There are some on the - 68HC12 to emulate a fiew 68HC11 instructions. */ + 68HC12 to emulate a few 68HC11 instructions. */ if (opc == NULL && (current_architecture & cpu6812)) { int i; @@ -2338,7 +2567,7 @@ md_assemble (str) relative and must be in the range -256..255 (9-bits). */ if ((opcode->format & M6812_XBCC_MARKER) && (opcode->format & M6811_OP_JUMP_REL)) - build_dbranch_insn (opcode, operands, nb_operands); + build_dbranch_insn (opcode, operands, nb_operands, branch_optimize); /* Relative jumps instructions are taken care of separately. We have to make sure that the relative branch is within the range -128..127. If it's out @@ -2350,21 +2579,125 @@ md_assemble (str) else build_insn (opcode, operands, nb_operands); } + + +/* Pseudo op to control the ELF flags. */ +static void +s_m68hc11_mode (x) + int x ATTRIBUTE_UNUSED; +{ + char *name = input_line_pointer, ch; + + while (!is_end_of_line[(unsigned char) *input_line_pointer]) + input_line_pointer++; + ch = *input_line_pointer; + *input_line_pointer = '\0'; + + if (strcmp (name, "mshort") == 0) + { + elf_flags &= ~E_M68HC11_I32; + } + else if (strcmp (name, "mlong") == 0) + { + elf_flags |= E_M68HC11_I32; + } + else if (strcmp (name, "mshort-double") == 0) + { + elf_flags &= ~E_M68HC11_F64; + } + else if (strcmp (name, "mlong-double") == 0) + { + elf_flags |= E_M68HC11_F64; + } + else + { + as_warn (_("Invalid mode: %s\n"), name); + } + *input_line_pointer = ch; + demand_empty_rest_of_line (); +} + +/* Mark the symbols with STO_M68HC12_FAR to indicate the functions + are using 'rtc' for returning. It is necessary to use 'call' + to invoke them. This is also used by the debugger to correctly + find the stack frame. */ +static void +s_m68hc11_mark_symbol (mark) + int mark; +{ + char *name; + int c; + symbolS *symbolP; + asymbol *bfdsym; + elf_symbol_type *elfsym; + + do + { + name = input_line_pointer; + c = get_symbol_end (); + symbolP = symbol_find_or_make (name); + *input_line_pointer = c; + + SKIP_WHITESPACE (); + + bfdsym = symbol_get_bfdsym (symbolP); + elfsym = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym); + + assert (elfsym); + + /* Mark the symbol far (using rtc for function return). */ + elfsym->internal_elf_sym.st_other |= mark; + + if (c == ',') + { + input_line_pointer ++; + + SKIP_WHITESPACE (); + + if (*input_line_pointer == '\n') + c = '\n'; + } + } + while (c == ','); + + demand_empty_rest_of_line (); +} + +static void +s_m68hc11_relax (ignore) + int ignore ATTRIBUTE_UNUSED; +{ + expressionS ex; + + expression (&ex); + + if (ex.X_op != O_symbol || ex.X_add_number != 0) + { + as_bad (_("bad .relax format")); + ignore_rest_of_line (); + return; + } + + fix_new_exp (frag_now, frag_now_fix (), 1, &ex, 1, + BFD_RELOC_M68HC11_RL_GROUP); + + demand_empty_rest_of_line (); +} + /* Relocation, relaxation and frag conversions. */ + +/* PC-relative offsets are relative to the start of the + next instruction. That is, the address of the offset, plus its + size, since the offset is always the last part of the insn. */ long -md_pcrel_from_section (fixp, sec) - fixS *fixp; - segT sec; +md_pcrel_from (fixP) + fixS *fixP; { - int adjust; - if (fixp->fx_addsy != (symbolS *) NULL - && (!S_IS_DEFINED (fixp->fx_addsy) - || (S_GET_SEGMENT (fixp->fx_addsy) != sec))) + if (fixP->fx_r_type == BFD_RELOC_M68HC11_RL_JUMP) return 0; - adjust = fixp->fx_pcrel_adjust; - return fixp->fx_frag->fr_address + fixp->fx_where + adjust; + return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; } /* If while processing a fixup, a reloc really needs to be created @@ -2392,17 +2725,106 @@ tc_gen_reloc (section, fixp) return NULL; } - if (!fixp->fx_pcrel) - reloc->addend = fixp->fx_addnumber; - else - reloc->addend = (section->vma - + (fixp->fx_pcrel_adjust == 64 - ? -1 : fixp->fx_pcrel_adjust) - + fixp->fx_addnumber - + md_pcrel_from_section (fixp, section)); + /* Since we use Rel instead of Rela, encode the vtable entry to be + used in the relocation's section offset. */ + if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) + reloc->address = fixp->fx_offset; + + reloc->addend = 0; return reloc; } +/* We need a port-specific relaxation function to cope with sym2 - sym1 + relative expressions with both symbols in the same segment (but not + necessarily in the same frag as this insn), for example: + ldab sym2-(sym1-2),pc + sym1: + The offset can be 5, 9 or 16 bits long. */ + +long +m68hc11_relax_frag (seg, fragP, stretch) + segT seg ATTRIBUTE_UNUSED; + fragS *fragP; + long stretch ATTRIBUTE_UNUSED; +{ + long growth; + offsetT aim = 0; + symbolS *symbolP; + const relax_typeS *this_type; + const relax_typeS *start_type; + relax_substateT next_state; + relax_substateT this_state; + const relax_typeS *table = TC_GENERIC_RELAX_TABLE; + + /* We only have to cope with frags as prepared by + md_estimate_size_before_relax. The STATE_BITS16 case may geet here + because of the different reasons that it's not relaxable. */ + switch (fragP->fr_subtype) + { + case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16): + /* When we get to this state, the frag won't grow any more. */ + return 0; + + case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS5): + case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9): + if (fragP->fr_symbol == NULL + || S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) + as_fatal (_("internal inconsistency problem in %s: fr_symbol %lx"), + __FUNCTION__, (long) fragP->fr_symbol); + symbolP = fragP->fr_symbol; + if (symbol_resolved_p (symbolP)) + as_fatal (_("internal inconsistency problem in %s: resolved symbol"), + __FUNCTION__); + aim = S_GET_VALUE (symbolP); + break; + + default: + as_fatal (_("internal inconsistency problem in %s: fr_subtype %d"), + __FUNCTION__, fragP->fr_subtype); + } + + /* The rest is stolen from relax_frag. There's no obvious way to + share the code, but fortunately no requirement to keep in sync as + long as fragP->fr_symbol does not have its segment changed. */ + + this_state = fragP->fr_subtype; + start_type = this_type = table + this_state; + + if (aim < 0) + { + /* Look backwards. */ + for (next_state = this_type->rlx_more; next_state;) + if (aim >= this_type->rlx_backward) + next_state = 0; + else + { + /* Grow to next state. */ + this_state = next_state; + this_type = table + this_state; + next_state = this_type->rlx_more; + } + } + else + { + /* Look forwards. */ + for (next_state = this_type->rlx_more; next_state;) + if (aim <= this_type->rlx_forward) + next_state = 0; + else + { + /* Grow to next state. */ + this_state = next_state; + this_type = table + this_state; + next_state = this_type->rlx_more; + } + } + + growth = this_type->rlx_length - start_type->rlx_length; + if (growth != 0) + fragP->fr_subtype = this_state; + return growth; +} + void md_convert_frag (abfd, sec, fragP) bfd *abfd ATTRIBUTE_UNUSED; @@ -2410,6 +2832,7 @@ md_convert_frag (abfd, sec, fragP) fragS *fragP; { fixS *fixp; + long value; long disp; char *buffer_address = fragP->fr_literal; @@ -2419,9 +2842,8 @@ md_convert_frag (abfd, sec, fragP) buffer_address += fragP->fr_fix; /* The displacement of the address, from current location. */ - disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; - disp = (disp + fragP->fr_offset) - object_address; - disp += symbol_get_frag (fragP->fr_symbol)->fr_address; + value = S_GET_VALUE (fragP->fr_symbol); + disp = (value + fragP->fr_offset) - object_address; switch (fragP->fr_subtype) { @@ -2470,24 +2892,44 @@ md_convert_frag (abfd, sec, fragP) break; case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS5): - fragP->fr_opcode[0] = fragP->fr_opcode[0] << 5; - fragP->fr_opcode[0] |= disp & 0x1f; + if (fragP->fr_opcode[0] == 3 + && fragP->fr_symbol != 0 + && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) + value = disp; + fragP->fr_opcode[0] = fragP->fr_opcode[0] << 6; + fragP->fr_opcode[0] |= value & 0x1f; break; case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS9): + if (fragP->fr_opcode[0] == 3 + && fragP->fr_symbol != 0 + && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) + value = disp; fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3); fragP->fr_opcode[0] |= 0xE0; - fix_new (fragP, fragP->fr_fix + 1, 1, - fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_8); + fragP->fr_opcode[0] |= (value >> 8) & 1; + fragP->fr_opcode[1] = value; fragP->fr_fix += 1; break; case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS16): fragP->fr_opcode[0] = (fragP->fr_opcode[0] << 3); - fragP->fr_opcode[0] |= 0xE2; - fix_new (fragP, fragP->fr_fix, 2, - fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); - fragP->fr_fix += 1; + fragP->fr_opcode[0] |= 0xe2; + if ((fragP->fr_opcode[0] & 0x0ff) == 0x0fa + && fragP->fr_symbol != 0 + && S_GET_SEGMENT (fragP->fr_symbol) != absolute_section) + { + fixp = fix_new (fragP, fragP->fr_fix, 2, + fragP->fr_symbol, fragP->fr_offset, + 1, BFD_RELOC_16_PCREL); + fixp->fx_pcrel_adjust = 2; + } + else + { + fix_new (fragP, fragP->fr_fix, 2, + fragP->fr_symbol, fragP->fr_offset, 0, BFD_RELOC_16); + } + fragP->fr_fix += 2; break; case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE): @@ -2512,6 +2954,17 @@ md_convert_frag (abfd, sec, fragP) } } +/* On an ELF system, we can't relax a weak symbol. The weak symbol + can be overridden at final link time by a non weak symbol. We can + relax externally visible symbol because there is no shared library + and such symbol can't be overridden (unless they are weak). */ +static int +relaxable_symbol (symbol) + symbolS *symbol; +{ + return ! S_IS_WEAK (symbol); +} + /* Force truly undefined symbols to their maximum size, and generally set up the frag list to be relaxed. */ int @@ -2519,180 +2972,229 @@ md_estimate_size_before_relax (fragP, segment) fragS *fragP; asection *segment; { - int old_fr_fix; - char *buffer_address = fragP->fr_fix + fragP->fr_literal; + if (RELAX_LENGTH (fragP->fr_subtype) == STATE_UNDF) + { + if (S_GET_SEGMENT (fragP->fr_symbol) != segment + || !relaxable_symbol (fragP->fr_symbol)) + { + /* Non-relaxable cases. */ + int old_fr_fix; + char *buffer_address; - old_fr_fix = fragP->fr_fix; + old_fr_fix = fragP->fr_fix; + buffer_address = fragP->fr_fix + fragP->fr_literal; - switch (fragP->fr_subtype) - { - case ENCODE_RELAX (STATE_PC_RELATIVE, STATE_UNDF): + switch (RELAX_STATE (fragP->fr_subtype)) + { + case STATE_PC_RELATIVE: + + /* This relax is only for bsr and bra. */ + assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR) + || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA) + || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR)); + + if (flag_fixed_branchs) + as_bad_where (fragP->fr_file, fragP->fr_line, + _("bra or bsr with undefined symbol.")); + + /* The symbol is undefined or in a separate section. + Turn bra into a jmp and bsr into a jsr. The insn + becomes 3 bytes long (instead of 2). A fixup is + necessary for the unresolved symbol address. */ + fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]); + + fix_new (fragP, fragP->fr_fix - 1, 2, fragP->fr_symbol, + fragP->fr_offset, 0, BFD_RELOC_16); + fragP->fr_fix++; + break; - /* This relax is only for bsr and bra. */ - assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR) - || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA) - || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR)); + case STATE_CONDITIONAL_BRANCH: + assert (current_architecture & cpu6811); - /* A relaxable case. */ - if (S_GET_SEGMENT (fragP->fr_symbol) == segment) - { - fragP->fr_subtype = ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE); - } - else - { - if (flag_fixed_branchs) - as_bad_where (fragP->fr_file, fragP->fr_line, - _("bra or bsr with undefined symbol.")); + fragP->fr_opcode[0] ^= 1; /* Reverse sense of branch. */ + fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */ - /* The symbol is undefined or in a separate section. Turn bra into a - jmp and bsr into a jsr. The insn becomes 3 bytes long (instead of - 2). A fixup is necessary for the unresolved symbol address. */ + /* Don't use fr_opcode[2] because this may be + in a different frag. */ + buffer_address[0] = M6811_JMP; - fragP->fr_opcode[0] = convert_branch (fragP->fr_opcode[0]); + fragP->fr_fix++; + fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, + fragP->fr_offset, 0, BFD_RELOC_16); + fragP->fr_fix += 2; + break; - fragP->fr_fix++; - fix_new (fragP, old_fr_fix - 1, 2, fragP->fr_symbol, - fragP->fr_offset, 0, BFD_RELOC_16); - frag_wane (fragP); - } - break; + case STATE_INDEXED_OFFSET: + assert (current_architecture & cpu6812); + + if (fragP->fr_symbol + && S_GET_SEGMENT (fragP->fr_symbol) == absolute_section) + { + fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_OFFSET, + STATE_BITS5); + /* Return the size of the variable part of the frag. */ + return md_relax_table[fragP->fr_subtype].rlx_length; + } + else + { + /* Switch the indexed operation to 16-bit mode. */ + fragP->fr_opcode[0] = fragP->fr_opcode[0] << 3; + fragP->fr_opcode[0] |= 0xe2; + fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, + fragP->fr_offset, 0, BFD_RELOC_16); + fragP->fr_fix += 2; + } + break; - case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, STATE_UNDF): - assert (current_architecture & cpu6811); + case STATE_XBCC_BRANCH: + assert (current_architecture & cpu6812); - if (S_GET_SEGMENT (fragP->fr_symbol) == segment) - { - fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, - STATE_BYTE); - } - else - { - fragP->fr_opcode[0] ^= 1; /* Reverse sense of branch. */ - fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */ + fragP->fr_opcode[0] ^= 0x20; /* Reverse sense of branch. */ + fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */ + + /* Don't use fr_opcode[2] because this may be + in a different frag. */ + buffer_address[0] = M6812_JMP; + + fragP->fr_fix++; + fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, + fragP->fr_offset, 0, BFD_RELOC_16); + fragP->fr_fix += 2; + break; + + case STATE_CONDITIONAL_BRANCH_6812: + assert (current_architecture & cpu6812); - /* Don't use fr_opcode[2] because this may be - in a different frag. */ - buffer_address[0] = M6811_JMP; + /* Translate into a lbcc branch. */ + fragP->fr_opcode[1] = fragP->fr_opcode[0]; + fragP->fr_opcode[0] = M6811_OPCODE_PAGE2; - fragP->fr_fix++; - fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, - fragP->fr_offset, 0, BFD_RELOC_16); - fragP->fr_fix += 2; + fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, + fragP->fr_offset, 1, BFD_RELOC_16_PCREL); + fragP->fr_fix += 2; + break; + + default: + as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype); + } frag_wane (fragP); - } - break; - case ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_UNDF): - assert (current_architecture & cpu6812); + /* Return the growth in the fixed part of the frag. */ + return fragP->fr_fix - old_fr_fix; + } - if (S_GET_SEGMENT (fragP->fr_symbol) == segment) + /* Relaxable cases. */ + switch (RELAX_STATE (fragP->fr_subtype)) { + case STATE_PC_RELATIVE: + /* This relax is only for bsr and bra. */ + assert (IS_OPCODE (fragP->fr_opcode[0], M6811_BSR) + || IS_OPCODE (fragP->fr_opcode[0], M6811_BRA) + || IS_OPCODE (fragP->fr_opcode[0], M6812_BSR)); + + fragP->fr_subtype = ENCODE_RELAX (STATE_PC_RELATIVE, STATE_BYTE); + break; + + case STATE_CONDITIONAL_BRANCH: + assert (current_architecture & cpu6811); + + fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH, + STATE_BYTE); + break; + + case STATE_INDEXED_OFFSET: + assert (current_architecture & cpu6812); + fragP->fr_subtype = ENCODE_RELAX (STATE_INDEXED_OFFSET, STATE_BITS5); - } - else - { - /* Switch the indexed operation to 16-bit mode. */ - if ((fragP->fr_opcode[1] & 0x21) == 0x20) - fragP->fr_opcode[1] = (fragP->fr_opcode[1] >> 3) | 0xc0 | 0x02; - - fragP->fr_fix++; - fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, - fragP->fr_offset, 0, BFD_RELOC_16); - fragP->fr_fix += 2; - frag_wane (fragP); - } - break; + break; - case ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_UNDF): - assert (current_architecture & cpu6812); + case STATE_XBCC_BRANCH: + assert (current_architecture & cpu6812); - if (S_GET_SEGMENT (fragP->fr_symbol) == segment) - { fragP->fr_subtype = ENCODE_RELAX (STATE_XBCC_BRANCH, STATE_BYTE); - } - else - { - fragP->fr_opcode[0] ^= 0x20; /* Reverse sense of branch. */ - fragP->fr_opcode[1] = 3; /* Skip next jmp insn (3 bytes). */ - - /* Don't use fr_opcode[2] because this may be - in a different frag. */ - buffer_address[0] = M6812_JMP; - - fragP->fr_fix++; - fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, - fragP->fr_offset, 0, BFD_RELOC_16); - fragP->fr_fix += 2; - frag_wane (fragP); - } - break; + break; - case ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_UNDF): - assert (current_architecture & cpu6812); + case STATE_CONDITIONAL_BRANCH_6812: + assert (current_architecture & cpu6812); - if (S_GET_SEGMENT (fragP->fr_symbol) == segment) - { fragP->fr_subtype = ENCODE_RELAX (STATE_CONDITIONAL_BRANCH_6812, STATE_BYTE); + break; } - else - { - /* Translate into a lbcc branch. */ - fragP->fr_opcode[1] = fragP->fr_opcode[0]; - fragP->fr_opcode[0] = M6811_OPCODE_PAGE2; + } - fix_new (fragP, fragP->fr_fix, 2, fragP->fr_symbol, - fragP->fr_offset, 0, BFD_RELOC_16_PCREL); - fragP->fr_fix += 2; - frag_wane (fragP); - } - break; + if (fragP->fr_subtype >= sizeof (md_relax_table) / sizeof (md_relax_table[0])) + as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype); + + /* Return the size of the variable part of the frag. */ + return md_relax_table[fragP->fr_subtype].rlx_length; +} + +/* See whether we need to force a relocation into the output file. */ +int +tc_m68hc11_force_relocation (fixP) + fixS * fixP; +{ + switch (fixP->fx_r_type) + { + case BFD_RELOC_VTABLE_INHERIT: + case BFD_RELOC_VTABLE_ENTRY: + case BFD_RELOC_M68HC11_RL_GROUP: + return 1; default: - as_fatal (_("Subtype %d is not recognized."), fragP->fr_subtype); + break; } - return (fragP->fr_fix - old_fr_fix); + return S_FORCE_RELOC (fixP->fx_addsy); } +/* Here we decide which fixups can be adjusted to make them relative + to the beginning of the section instead of the symbol. Basically + we need to make sure that the linker relaxation is done + correctly, so in some cases we force the original symbol to be + used. */ int -md_apply_fix (fixp, valuep) - fixS *fixp; - valueT *valuep; +tc_m68hc11_fix_adjustable (fixP) + fixS *fixP; +{ + switch (fixP->fx_r_type) + { + /* For the linker relaxation to work correctly, these relocs + need to be on the symbol itself. */ + case BFD_RELOC_16: + case BFD_RELOC_LO16: + case BFD_RELOC_M68HC11_RL_JUMP: + case BFD_RELOC_M68HC11_RL_GROUP: + case BFD_RELOC_VTABLE_INHERIT: + case BFD_RELOC_VTABLE_ENTRY: + return 0; + + case BFD_RELOC_32: + default: + return 1; + } +} + +void +md_apply_fix3 (fixP, valP, seg) + fixS *fixP; + valueT *valP; + segT seg ATTRIBUTE_UNUSED; { char *where; - long value; + long value = * valP; int op_type; - if (fixp->fx_addsy == (symbolS *) NULL) - { - value = *valuep; - fixp->fx_done = 1; - } - else if (fixp->fx_pcrel) - { - value = *valuep; - } - else - { - value = fixp->fx_offset; - if (fixp->fx_subsy != (symbolS *) NULL) - { - if (S_GET_SEGMENT (fixp->fx_subsy) == absolute_section) - { - value -= S_GET_VALUE (fixp->fx_subsy); - } - else - { - /* We don't actually support subtracting a symbol. */ - as_bad_where (fixp->fx_file, fixp->fx_line, - _("Expression too complex.")); - } - } - } + if (fixP->fx_addsy == (symbolS *) NULL) + fixP->fx_done = 1; - op_type = fixp->fx_r_type; + /* We don't actually support subtracting a symbol. */ + if (fixP->fx_subsy != (symbolS *) NULL) + as_bad_where (fixP->fx_file, fixP->fx_line, _("Expression too complex.")); + + op_type = fixP->fx_r_type; /* Patch the instruction with the resolved operand. Elf relocation info will also be generated to take care of linker/loader fixups. @@ -2703,19 +3205,26 @@ md_apply_fix (fixp, valuep) relax table, bcc, bra, bsr transformations) The BFD_RELOC_32 is necessary for the support of --gstabs. */ - where = fixp->fx_frag->fr_literal + fixp->fx_where; + where = fixP->fx_frag->fr_literal + fixP->fx_where; - switch (fixp->fx_r_type) + switch (fixP->fx_r_type) { case BFD_RELOC_32: bfd_putb32 ((bfd_vma) value, (unsigned char *) where); break; + case BFD_RELOC_24: + case BFD_RELOC_M68HC11_24: + bfd_putb16 ((bfd_vma) (value & 0x0ffff), (unsigned char *) where); + ((bfd_byte*) where)[2] = ((value >> 16) & 0x0ff); + break; + case BFD_RELOC_16: case BFD_RELOC_16_PCREL: + case BFD_RELOC_M68HC11_LO16: bfd_putb16 ((bfd_vma) value, (unsigned char *) where); if (value < -65537 || value > 65535) - as_bad_where (fixp->fx_file, fixp->fx_line, + as_bad_where (fixP->fx_file, fixP->fx_line, _("Value out of 16-bit range.")); break; @@ -2725,6 +3234,7 @@ md_apply_fix (fixp, valuep) case BFD_RELOC_M68HC11_LO8: case BFD_RELOC_8: + case BFD_RELOC_M68HC11_PAGE: #if 0 bfd_putb8 ((bfd_vma) value, (unsigned char *) where); #endif @@ -2738,14 +3248,14 @@ md_apply_fix (fixp, valuep) ((bfd_byte *) where)[0] = (bfd_byte) value; if (value < -128 || value > 127) - as_bad_where (fixp->fx_file, fixp->fx_line, + as_bad_where (fixP->fx_file, fixP->fx_line, _("Value %ld too large for 8-bit PC-relative branch."), value); break; case BFD_RELOC_M68HC11_3B: if (value <= 0 || value > 8) - as_bad_where (fixp->fx_file, fixp->fx_line, + as_bad_where (fixP->fx_file, fixP->fx_line, _("Auto increment/decrement offset '%ld' is out of range."), value); if (where[0] & 0x8) @@ -2756,51 +3266,23 @@ md_apply_fix (fixp, valuep) where[0] = where[0] | (value & 0x07); break; + case BFD_RELOC_M68HC11_RL_JUMP: + case BFD_RELOC_M68HC11_RL_GROUP: + case BFD_RELOC_VTABLE_INHERIT: + case BFD_RELOC_VTABLE_ENTRY: + fixP->fx_done = 0; + return; + default: as_fatal (_("Line %d: unknown relocation type: 0x%x."), - fixp->fx_line, fixp->fx_r_type); + fixP->fx_line, fixP->fx_r_type); } - - return 0; -} - -int -m68hc11_cleanup () -{ - return 1; } +/* Set the ELF specific flags. */ void -m68hc11_end_of_source () +m68hc11_elf_final_processing () { - segT saved_seg; - subsegT saved_subseg; - segT debug_info; - char *p; - long total_size = 0; - - if (debug_type != DEBUG_DWARF2) - return; - - dwarf2_finish (); - - saved_seg = now_seg; - saved_subseg = now_subseg; - - debug_info = subseg_new (".debug_info", 0); - bfd_set_section_flags (stdoutput, debug_info, SEC_READONLY); - subseg_set (debug_info, 0); - p = frag_more (10); - total_size = 12; - -# define STUFF(val,size) md_number_to_chars (p, val, size); p += size; - STUFF (total_size, 4); /* Length of compilation unit. */ - STUFF (2, 2); /* Dwarf version */ - STUFF (0, 4); - STUFF (2, 1); /* Pointer size */ - STUFF (1, 1); /* Compile unit */ - STUFF (0, 4); - - now_subseg = saved_subseg; - now_seg = saved_seg; + elf_elfheader (stdoutput)->e_flags &= ~EF_M68HC11_ABI; + elf_elfheader (stdoutput)->e_flags |= elf_flags; }