X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fconfig%2Ftc-m68k.c;h=89c2df9c29807e89ebe0af2ad5f93babc8fe67da;hb=6b6e92f432c86611c81a5da6880946bad25b59dc;hp=466a8d3e77bc34d94e0d4729cb239404542848f1;hpb=8a104df9d77a79d084454ccf9855c4fdd5225fa2;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c index 466a8d3e77..89c2df9c29 100644 --- a/gas/config/tc-m68k.c +++ b/gas/config/tc-m68k.c @@ -1,7 +1,6 @@ /* tc-m68k.c -- Assemble for the m68k family Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002 - Free Software Foundation, Inc. + 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. @@ -25,6 +24,7 @@ #include "obstack.h" #include "subsegs.h" #include "dwarf2dbg.h" +#include "dw2gencfi.h" #include "opcode/m68k.h" #include "m68k-parse.h" @@ -54,19 +54,19 @@ const char line_comment_chars[] = "#*"; const char line_separator_chars[] = ";"; -/* Chars that can be used to separate mant from exp in floating point nums */ -CONST char EXP_CHARS[] = "eE"; +/* Chars that can be used to separate mant from exp in floating point nums. */ +const char EXP_CHARS[] = "eE"; /* Chars that mean this number is a floating point constant, as in "0f12.456" or "0d1.2345e12". */ -CONST char FLT_CHARS[] = "rRsSfFdDxXeEpP"; +const char FLT_CHARS[] = "rRsSfFdDxXeEpP"; /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be changed in read.c . Ideally it shouldn't have to know about it at all, but nothing is ideal around here. */ -const int md_reloc_size = 8; /* Size of relocation record */ +const int md_reloc_size = 8; /* Size of relocation record. */ /* Are we trying to generate PIC code? If so, absolute references ought to be made into linkage table references or pc-relative @@ -74,8 +74,8 @@ const int md_reloc_size = 8; /* Size of relocation record */ to denote pic relocations. */ int flag_want_pic; -static int flag_short_refs; /* -l option */ -static int flag_long_jumps; /* -S option */ +static int flag_short_refs; /* -l option. */ +static int flag_long_jumps; /* -S option. */ static int flag_keep_pcrel; /* --pcrel option. */ #ifdef REGISTER_PREFIX_OPTIONAL @@ -113,7 +113,6 @@ static enum m68k_size m68k_index_width_default = SIZE_LONG; /* We want to warn if any text labels are misaligned. In order to get the right line number, we need to record the line number for each label. */ - struct label_line { struct label_line *next; @@ -131,8 +130,8 @@ static struct label_line *labels; static struct label_line *current_label; -/* Its an arbitrary name: This means I don't approve of it */ -/* See flames below */ +/* Its an arbitrary name: This means I don't approve of it. + See flames below. */ static struct obstack robyn; struct m68k_incant @@ -168,40 +167,51 @@ static const enum m68k_register m68060_control_regs[] = { 0 }; static const enum m68k_register mcf_control_regs[] = { - CACR, TC, ITT0, ITT1, DTT0, DTT1, VBR, ROMBAR, + CACR, TC, ACR0, ACR1, ACR2, ACR3, VBR, ROMBAR, RAMBAR0, RAMBAR1, MBAR, 0 }; +static const enum m68k_register mcf528x_control_regs[] = { + CACR, ACR0, ACR1, VBR, FLASHBAR, RAMBAR, + 0 +}; +static const enum m68k_register mcfv4e_control_regs[] = { + CACR, TC, ITT0, ITT1, DTT0, DTT1, BUSCR, VBR, PC, ROMBAR, + ROMBAR1, RAMBAR0, RAMBAR1, MPCR, EDRAMBAR, SECMBAR, MBAR, MBAR0, MBAR1, + PCR1U0, PCR1L0, PCR1U1, PCR1L1, PCR2U0, PCR2L0, PCR2U1, PCR2L1, + PCR3U0, PCR3L0, PCR3U1, PCR3L1, + 0 +}; #define cpu32_control_regs m68010_control_regs static const enum m68k_register *control_regs; -/* internal form of a 68020 instruction */ +/* Internal form of a 68020 instruction. */ struct m68k_it { const char *error; - const char *args; /* list of opcode info */ + const char *args; /* List of opcode info. */ int numargs; - int numo; /* Number of shorts in opcode */ + int numo; /* Number of shorts in opcode. */ short opcode[11]; struct m68k_op operands[6]; - int nexp; /* number of exprs in use */ + int nexp; /* Number of exprs in use. */ struct m68k_exp exprs[4]; - int nfrag; /* Number of frags we have to produce */ + int nfrag; /* Number of frags we have to produce. */ struct { - int fragoff; /* Where in the current opcode the frag ends */ + int fragoff; /* Where in the current opcode the frag ends. */ symbolS *fadd; offsetT foff; int fragty; } fragb[4]; - int nrel; /* Num of reloc strucs in use */ + int nrel; /* Num of reloc strucs in use. */ struct { int n; @@ -222,35 +232,35 @@ struct m68k_it enum pic_relocation pic_reloc; #endif } - reloc[5]; /* Five is enough??? */ + reloc[5]; /* Five is enough??? */ }; -#define cpu_of_arch(x) ((x) & (m68000up|mcf)) +#define cpu_of_arch(x) ((x) & (m68000up | mcfisa_a)) #define float_of_arch(x) ((x) & mfloat) #define mmu_of_arch(x) ((x) & mmmu) -#define arch_coldfire_p(x) (((x) & mcf) != 0) +#define arch_coldfire_p(x) ((x) & mcfisa_a) +#define arch_coldfire_fpu(x) ((x) & cfloat) -/* Macros for determining if cpu supports a specific addressing mode */ -#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcf5407)) +/* Macros for determining if cpu supports a specific addressing mode. */ +#define HAVE_LONG_BRANCH(x) ((x) & (m68020|m68030|m68040|m68060|cpu32|mcfisa_b)) -static struct m68k_it the_ins; /* the instruction being assembled */ +static struct m68k_it the_ins; /* The instruction being assembled. */ #define op(ex) ((ex)->exp.X_op) #define adds(ex) ((ex)->exp.X_add_symbol) #define subs(ex) ((ex)->exp.X_op_symbol) #define offs(ex) ((ex)->exp.X_add_number) -/* Macros for adding things to the m68k_it struct */ - +/* Macros for adding things to the m68k_it struct. */ #define addword(w) the_ins.opcode[the_ins.numo++]=(w) /* Static functions. */ - static void insop PARAMS ((int, const struct m68k_incant *)); static void add_fix PARAMS ((int, struct m68k_exp *, int, int)); static void add_frag PARAMS ((symbolS *, offsetT, int)); -/* Like addword, but goes BEFORE general operands */ +/* Like addword, but goes BEFORE general operands. */ + static void insop (w, opcode) int w; @@ -351,59 +361,85 @@ static void s_mri_endw PARAMS ((int)); static void md_convert_frag_1 PARAMS ((fragS *)); static int current_architecture; +static int current_chip; struct m68k_cpu { unsigned long arch; + unsigned long chip; const char *name; int alias; }; static const struct m68k_cpu archs[] = { - { m68000, "68000", 0 }, - { m68010, "68010", 0 }, - { m68020, "68020", 0 }, - { m68030, "68030", 0 }, - { m68040, "68040", 0 }, - { m68060, "68060", 0 }, - { cpu32, "cpu32", 0 }, - { m68881, "68881", 0 }, - { m68851, "68851", 0 }, - { mcf5200, "5200", 0 }, - { mcf5206e, "5206e", 0 }, - { mcf5307, "5307", 0}, - { mcf5407, "5407", 0}, + { m68000, m68000, "68000", 0 }, + { m68010, m68010, "68010", 0 }, + { m68020, m68020, "68020", 0 }, + { m68030, m68030, "68030", 0 }, + { m68040, m68040, "68040", 0 }, + { m68060, m68060, "68060", 0 }, + { cpu32, cpu32, "cpu32", 0 }, + { m68881, m68881, "68881", 0 }, + { m68851, m68851, "68851", 0 }, + { mcfisa_a, mcf5200, "5200", 0 }, + { mcfisa_a|mcfhwdiv|mcfmac, mcf5206e, "5206e", 0 }, + { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf521x, "521x", 0 }, + { mcfisa_a|mcfhwdiv|mcfemac, mcf5249, "5249", 0 }, + { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac|mcfusp, mcf528x, "528x", 0 }, + { mcfisa_a|mcfhwdiv|mcfmac, mcf5307, "5307", 0 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "5407", 0 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "547x", 0 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5480, "548x", 0 }, /* Aliases (effectively, so far as gas is concerned) for the above cpus. */ - { m68020, "68k", 1 }, - { m68000, "68008", 1 }, - { m68000, "68302", 1 }, - { m68000, "68306", 1 }, - { m68000, "68307", 1 }, - { m68000, "68322", 1 }, - { m68000, "68356", 1 }, - { m68000, "68ec000", 1 }, - { m68000, "68hc000", 1 }, - { m68000, "68hc001", 1 }, - { m68020, "68ec020", 1 }, - { m68030, "68ec030", 1 }, - { m68040, "68ec040", 1 }, - { m68060, "68ec060", 1 }, - { cpu32, "68330", 1 }, - { cpu32, "68331", 1 }, - { cpu32, "68332", 1 }, - { cpu32, "68333", 1 }, - { cpu32, "68334", 1 }, - { cpu32, "68336", 1 }, - { cpu32, "68340", 1 }, - { cpu32, "68341", 1 }, - { cpu32, "68349", 1 }, - { cpu32, "68360", 1 }, - { m68881, "68882", 1 }, - { mcf5200, "5202", 1 }, - { mcf5200, "5204", 1 }, - { mcf5200, "5206", 1 }, + { m68020, m68020, "68k", 1 }, + { m68000, m68000, "68008", 1 }, + { m68000, m68000, "68302", 1 }, + { m68000, m68000, "68306", 1 }, + { m68000, m68000, "68307", 1 }, + { m68000, m68000, "68322", 1 }, + { m68000, m68000, "68356", 1 }, + { m68000, m68000, "68ec000", 1 }, + { m68000, m68000, "68hc000", 1 }, + { m68000, m68000, "68hc001", 1 }, + { m68020, m68020, "68ec020", 1 }, + { m68030, m68030, "68ec030", 1 }, + { m68040, m68040, "68ec040", 1 }, + { m68060, m68060, "68ec060", 1 }, + { cpu32, cpu32, "68330", 1 }, + { cpu32, cpu32, "68331", 1 }, + { cpu32, cpu32, "68332", 1 }, + { cpu32, cpu32, "68333", 1 }, + { cpu32, cpu32, "68334", 1 }, + { cpu32, cpu32, "68336", 1 }, + { cpu32, cpu32, "68340", 1 }, + { cpu32, cpu32, "68341", 1 }, + { cpu32, cpu32, "68349", 1 }, + { cpu32, cpu32, "68360", 1 }, + { m68881, m68881, "68882", 1 }, + { mcfisa_a, mcf5200, "5202", 1 }, + { mcfisa_a, mcf5200, "5204", 1 }, + { mcfisa_a, mcf5200, "5206", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5214", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_aa|mcfemac, mcf521x, "5216", 1 }, + { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5280", 1 }, + { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5281", 1 }, + { mcfisa_a|mcfisa_aa|mcfhwdiv|mcfemac, mcf528x, "5282", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfmac, mcf5407, "cfv4", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5470", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5471", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5472", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5473", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5474", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5475", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5480", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5481", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5482", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5483", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5484", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "5485", 1 }, + { mcfisa_a|mcfhwdiv|mcfisa_b|mcfemac|mcfusp|cfloat, mcf5470, "cfv4e", 1 }, }; static const int n_archs = sizeof (archs) / sizeof (archs[0]); @@ -431,10 +467,10 @@ static const int n_archs = sizeof (archs) / sizeof (archs[0]); BYTE and SHORT forms, punting if that isn't enough. This gives us four different relaxation modes for branches: */ -#define BRANCHBWL 0 /* branch byte, word, or long */ -#define BRABSJUNC 1 /* absolute jump for LONG, unconditional */ -#define BRABSJCOND 2 /* absolute jump for LONG, conditional */ -#define BRANCHBW 3 /* branch byte or word */ +#define BRANCHBWL 0 /* Branch byte, word, or long. */ +#define BRABSJUNC 1 /* Absolute jump for LONG, unconditional. */ +#define BRABSJCOND 2 /* Absolute jump for LONG, conditional. */ +#define BRANCHBW 3 /* Branch byte or word. */ /* We also relax coprocessor branches and DBcc's. All CPUs that support coprocessor branches support them in word and long forms, so we have only @@ -444,9 +480,9 @@ static const int n_archs = sizeof (archs) / sizeof (archs[0]); This gives us two relaxation modes. If long branches are not available and absolute jumps are not acceptable, we don't relax DBcc's. */ -#define FBRANCH 4 /* coprocessor branch */ -#define DBCCLBR 5 /* DBcc relaxable with a long branch */ -#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump */ +#define FBRANCH 4 /* Coprocessor branch. */ +#define DBCCLBR 5 /* DBcc relaxable with a long branch. */ +#define DBCCABSJ 6 /* DBcc relaxable with an absolute jump. */ /* That's all for instruction relaxation. However, we also relax PC-relative operands. Specifically, we have three operand relaxation modes. On the @@ -459,9 +495,9 @@ static const int n_archs = sizeof (archs) / sizeof (archs[0]); form of the PC+displacement+index operand. Finally, some absolute operands can be relaxed down to 16-bit PC-relative. */ -#define PCREL1632 7 /* 16-bit or 32-bit PC-relative */ -#define PCINDEX 8 /* PC+displacement+index */ -#define ABSTOPCREL 9 /* absolute relax down to 16-bit PC-relative */ +#define PCREL1632 7 /* 16-bit or 32-bit PC-relative. */ +#define PCINDEX 8 /* PC + displacement + index. */ +#define ABSTOPCREL 9 /* Absolute relax down to 16-bit PC-relative. */ /* Note that calls to frag_var need to specify the maximum expansion needed; this is currently 10 bytes for DBCC. */ @@ -495,22 +531,22 @@ relax_typeS md_relax_table[] = { 1, 1, 0, 0 }, { 1, 1, 0, 0 }, - { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE */ + { 1, 1, 0, 0 }, /* FBRANCH doesn't come BYTE. */ { 32767, -32768, 2, TAB (FBRANCH, LONG) }, { 0, 0, 4, 0 }, { 1, 1, 0, 0 }, - { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */ + { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ { 32767, -32768, 2, TAB (DBCCLBR, LONG) }, { 0, 0, 10, 0 }, { 1, 1, 0, 0 }, - { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE */ + { 1, 1, 0, 0 }, /* DBCC doesn't come BYTE. */ { 32767, -32768, 2, TAB (DBCCABSJ, LONG) }, { 0, 0, 10, 0 }, { 1, 1, 0, 0 }, - { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE */ + { 1, 1, 0, 0 }, /* PCREL1632 doesn't come BYTE. */ { 32767, -32768, 2, TAB (PCREL1632, LONG) }, { 0, 0, 6, 0 }, { 1, 1, 0, 0 }, @@ -520,7 +556,7 @@ relax_typeS md_relax_table[] = { 0, 0, 4, 0 }, { 1, 1, 0, 0 }, - { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE */ + { 1, 1, 0, 0 }, /* ABSTOPCREL doesn't come BYTE. */ { 32767, -32768, 2, TAB (ABSTOPCREL, LONG) }, { 0, 0, 4, 0 }, { 1, 1, 0, 0 }, @@ -528,15 +564,13 @@ relax_typeS md_relax_table[] = /* These are the machine dependent pseudo-ops. These are included so the assembler can work on the output from the SUN C compiler, which - generates these. - */ + generates these. */ /* This table describes all the machine specific pseudo-ops the assembler has to support. The fields are: pseudo-op name without dot function to call to execute this pseudo-op - Integer arg to pass to the function - */ + Integer arg to pass to the function. */ const pseudo_typeS md_pseudo_table[] = { {"data1", s_data1, 0}, @@ -554,12 +588,6 @@ const pseudo_typeS md_pseudo_table[] = {"extend", float_cons, 'x'}, {"ldouble", float_cons, 'x'}, -#ifdef OBJ_ELF - /* Dwarf2 support for Gcc. */ - {"file", dwarf2_directive_file, 0}, - {"loc", dwarf2_directive_loc, 0}, -#endif - /* The following pseudo-ops are supported for MRI compatibility. */ {"chip", s_chip, 0}, {"comline", s_space, 1}, @@ -611,7 +639,7 @@ const pseudo_typeS md_pseudo_table[] = extern void obj_coff_section PARAMS ((int)); #endif -CONST pseudo_typeS mote_pseudo_table[] = +const pseudo_typeS mote_pseudo_table[] = { {"dcl", cons, 4}, @@ -655,28 +683,99 @@ static char alt_notend_table[256]; || (*s == ':' \ && alt_notend_table[(unsigned char) s[1]]))) +/* Return a human readable string holding the list of chips that are + valid for a particular architecture, suppressing aliases (unless + there is only one of them). */ + +static char * +find_cf_chip (int architecture) +{ + static char buf[1024]; + int i, j, n_chips, n_alias; + char *cp; + + strcpy (buf, " ("); + cp = buf + strlen (buf); + + for (i = 0, n_chips = 0, n_alias = 0; i < n_archs; ++i) + if (archs[i].arch & architecture) + { + n_chips++; + if (archs[i].alias) + n_alias++; + } + + if (n_chips == 0) + as_fatal (_("no matching ColdFire architectures found")); + + if (n_alias > 1) + n_chips -= n_alias; + + for (i = 0, j = 0; i < n_archs && j < n_chips; ++i) + if (archs[i].arch & architecture) + { + if (j) + { + if (((j == n_chips - 1) && !(n_alias > 1))|| ! n_alias) + { + if (n_chips == 2) + { + strncpy (cp, _(" or "), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + } + else + { + strncpy (cp, _(", or "), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + } + } + else + { + strncpy (cp, ", ", (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + } + } + strncpy (cp, archs[i].name, (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + j++; + } + + if (n_alias > 1) + { + strncpy (cp, _(", or aliases"), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + } + + strncpy (cp, ")", (sizeof (buf) - (cp - buf))); + + return buf; +} + #if defined (M68KCOFF) && !defined (BFD_ASSEMBLER) #ifdef NO_PCREL_RELOCS int -make_pcrel_absolute(fixP, add_number) +make_pcrel_absolute (fixP, add_number) fixS *fixP; long *add_number; { register unsigned char *opcode = fixP->fx_frag->fr_opcode; - /* rewrite the PC relative instructions to absolute address ones. - * these are rumoured to be faster, and the apollo linker refuses - * to deal with the PC relative relocations. - */ - if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP */ + /* Rewrite the PC relative instructions to absolute address ones. + these are rumored to be faster, and the apollo linker refuses + to deal with the PC relative relocations. */ + if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */ { + if (flag_keep_pcrel) + as_fatal (_("Tried to convert PC relative branch to absolute jump")); opcode[0] = 0x4e; opcode[1] = 0xf9; } - else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR */ + else if (opcode[0] == 0x61 && opcode[1] == 0xff) /* BSR -> JSR. */ { + if (flag_keep_pcrel) + as_fatal (_("Tried to convert PC relative BSR to absolute JSR")); opcode[0] = 0x4e; opcode[1] = 0xb9; } @@ -724,7 +823,7 @@ tc_coff_fix2rtype (fixP) libraries, and we can relax any external sym. */ #define relaxable_symbol(symbol) \ - (!((S_IS_EXTERNAL (symbol) && strcmp (TARGET_OS, "elf") != 0) \ + (!((S_IS_EXTERNAL (symbol) && EXTERN_FORCE_RELOC) \ || S_IS_WEAK (symbol))) /* Compute the relocation code for a fixup of SIZE bytes, using pc @@ -844,11 +943,7 @@ int tc_m68k_fix_adjustable (fixP) fixS *fixP; { - /* Prevent all adjustments to global symbols. */ - if (! relaxable_symbol (fixP->fx_addsy)) - return 0; - - /* adjust_reloc_syms doesn't know about the GOT */ + /* Adjust_reloc_syms doesn't know about the GOT. */ switch (fixP->fx_r_type) { case BFD_RELOC_8_GOT_PCREL: @@ -886,7 +981,7 @@ tc_m68k_fix_adjustable (fixP) arelent * tc_gen_reloc (section, fixp) - asection *section; + asection *section ATTRIBUTE_UNUSED; fixS *fixp; { arelent *reloc; @@ -1023,7 +1118,7 @@ m68k_ip (instring) unsigned long ok_arch = 0; if (*instring == ' ') - instring++; /* skip leading whitespace */ + instring++; /* Skip leading whitespace. */ /* Scan up to end of operation-code, which MUST end in end-of-string or exactly 1 space. */ @@ -1072,7 +1167,7 @@ m68k_ip (instring) return; } - /* found a legitimate opcode, start matching operands */ + /* Found a legitimate opcode, start matching operands. */ while (*p == ' ') ++p; @@ -1081,7 +1176,7 @@ m68k_ip (instring) char *old = input_line_pointer; *old = '\n'; input_line_pointer = p; - /* Ahh - it's a motorola style psuedo op */ + /* Ahh - it's a motorola style psuedo op. */ mote_pseudo_table[opcode->m_opnum].poc_handler (mote_pseudo_table[opcode->m_opnum].poc_val); input_line_pointer = old; @@ -1131,7 +1226,7 @@ m68k_ip (instring) opsfound++; } - /* We've got the operands. Find an opcode that'll accept them */ + /* We've got the operands. Find an opcode that'll accept them. */ for (losing = 0;;) { /* If we didn't get the right number of ops, or we have no @@ -1501,6 +1596,14 @@ m68k_ip (instring) ++losing; break; + case '4': + if (opP->mode != AINDR && opP->mode != AINC && opP->mode != ADEC + && (opP->mode != DISP + || opP->reg < ADDR0 + || opP->reg > ADDR7)) + ++losing; + break; + case 'B': /* FOO */ if (opP->mode != ABSL || (flag_long_jumps @@ -1508,6 +1611,24 @@ m68k_ip (instring) losing++; break; + case 'b': + switch (opP->mode) + { + case IMMED: + case ABSL: + case AREG: + case FPREG: + case CONTROL: + case POST: + case PRE: + case REGLST: + losing++; + break; + default: + break; + } + break; + case 'C': if (opP->mode != CONTROL || opP->reg != CCR) losing++; @@ -1530,6 +1651,12 @@ m68k_ip (instring) losing++; break; + case 'e': + if (opP->reg != ACC && opP->reg != ACC1 + && opP->reg != ACC2 && opP->reg != ACC3) + losing++; + break; + case 'F': if (opP->mode != FPREG) losing++; @@ -1540,6 +1667,11 @@ m68k_ip (instring) losing++; break; + case 'g': + if (opP->reg != ACCEXT01 && opP->reg != ACCEXT23) + losing++; + break; + case 'H': if (opP->reg != MASK) losing++; @@ -1552,6 +1684,11 @@ m68k_ip (instring) losing++; break; + case 'i': + if (opP->mode != LSH && opP->mode != RSH) + losing++; + break; + case 'J': if (opP->mode != CONTROL || opP->reg < USP @@ -1712,6 +1849,16 @@ m68k_ip (instring) losing++; break; + case 'x': + if (opP->mode != IMMED) + losing++; + else if (opP->disp.exp.X_op != O_constant + || opP->disp.exp.X_add_number < -1 + || opP->disp.exp.X_add_number > 7 + || opP->disp.exp.X_add_number == 0) + losing++; + break; + /* JF these are out of order. We could put them in order if we were willing to put up with bunches of #ifdef m68851s in the code. @@ -1719,7 +1866,7 @@ m68k_ip (instring) Don't forget that you need these operands to use 68030 MMU instructions. */ #ifndef NO_68851 - /* Memory addressing mode used by pflushr */ + /* Memory addressing mode used by pflushr. */ case '|': if (opP->mode == CONTROL || opP->mode == FPREG @@ -1773,6 +1920,25 @@ m68k_ip (instring) losing++; break; + case 'w': + switch (opP->mode) + { + case IMMED: + case ABSL: + case AREG: + case DREG: + case FPREG: + case CONTROL: + case POST: + case PRE: + case REGLST: + losing++; + break; + default: + break; + } + break; + case 'X': if (opP->mode != CONTROL || (!(opP->reg >= BAD && opP->reg <= BAD + 7) @@ -1796,9 +1962,7 @@ m68k_ip (instring) && opP->reg != IC && opP->reg != DC && opP->reg != BC)) - { - losing++; - } /* not a cache specifier. */ + losing++; break; case '_': @@ -1819,19 +1983,29 @@ m68k_ip (instring) opP->mode = AREG; break; + case 'y': + if (!(opP->mode == AINDR + || (opP->mode == DISP && !(opP->reg == PC || + opP->reg == ZPC)))) + losing++; + break; + + case 'z': + if (!(opP->mode == AINDR || opP->mode == DISP)) + losing++; + break; + default: abort (); - } /* switch on type of operand */ + } if (losing) break; - } /* for each operand */ - } /* if immediately wrong */ + } + } if (!losing) - { - break; - } /* got it. */ + break; opcode = opcode->m_next; @@ -1842,11 +2016,41 @@ m68k_ip (instring) { char buf[200], *cp; - strcpy (buf, - _("invalid instruction for this architecture; needs ")); + strncpy (buf, + _("invalid instruction for this architecture; needs "), sizeof (buf)); cp = buf + strlen (buf); switch (ok_arch) { + case mcfisa_a: + strncpy (cp, _("ColdFire ISA_A"), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + break; + case mcfhwdiv: + strncpy (cp, _("ColdFire hardware divide"), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + break; + case mcfisa_aa: + strncpy (cp, _("ColdFire ISA_A+"), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + break; + case mcfisa_b: + strncpy (cp, _("ColdFire ISA_B"), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + break; + case cfloat: + strncpy (cp, _("ColdFire fpu"), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + strncpy (cp, find_cf_chip (ok_arch), (sizeof (buf) - (cp - buf))); + cp += strlen (cp); + break; case mfloat: strcpy (cp, _("fpu (68040, 68060 or 68881/68882)")); break; @@ -1865,9 +2069,8 @@ m68k_ip (instring) default: { int got_one = 0, idx; - for (idx = 0; - idx < (int) (sizeof (archs) / sizeof (archs[0])); - idx++) + + for (idx = 0; idx < n_archs; idx++) { if ((archs[idx].arch & ok_arch) && ! archs[idx].alias) @@ -1891,13 +2094,12 @@ m68k_ip (instring) else the_ins.error = _("operands mismatch"); return; - } /* Fell off the end */ + } losing = 0; } - /* now assemble it */ - + /* Now assemble it. */ the_ins.args = opcode->m_operands; the_ins.numargs = opcode->m_opnum; the_ins.numo = opcode->m_codenum; @@ -1923,12 +2125,17 @@ m68k_ip (instring) case '/': case '<': case '>': + case 'b': case 'm': case 'n': case 'o': case 'p': case 'q': case 'v': + case 'w': + case 'y': + case 'z': + case '4': #ifndef NO_68851 case '|': #endif @@ -1937,7 +2144,7 @@ m68k_ip (instring) case IMMED: tmpreg = 0x3c; /* 7.4 */ if (strchr ("bwl", s[1])) - nextword = get_num (&opP->disp, 80); + nextword = get_num (&opP->disp, 90); else nextword = get_num (&opP->disp, 0); if (isvar (&opP->disp)) @@ -1990,7 +2197,7 @@ m68k_ip (instring) if (!baseo) break; - /* We gotta put out some float */ + /* We gotta put out some float. */ if (op (&opP->disp) != O_big) { valueT val; @@ -2049,7 +2256,7 @@ m68k_ip (instring) break; case DISP: - nextword = get_num (&opP->disp, 80); + nextword = get_num (&opP->disp, 90); if (opP->reg == PC && ! isvar (&opP->disp) @@ -2064,7 +2271,7 @@ m68k_ip (instring) #endif } - /* Force into index mode. Hope this works */ + /* Force into index mode. Hope this works. */ /* We do the first bit for 32-bit displacements, and the second bit for 16 bit ones. It is possible that we @@ -2145,9 +2352,9 @@ m68k_ip (instring) case PRE: case BASE: nextword = 0; - baseo = get_num (&opP->disp, 80); + baseo = get_num (&opP->disp, 90); if (opP->mode == POST || opP->mode == PRE) - outro = get_num (&opP->odisp, 80); + outro = get_num (&opP->odisp, 90); /* Figure out the `addressing mode'. Also turn on the BASE_DISABLE bit, if needed. */ if (opP->reg == PC || opP->reg == ZPC) @@ -2175,7 +2382,7 @@ m68k_ip (instring) else siz2 = SIZE_UNSPEC; - /* Index register stuff */ + /* Index register stuff. */ if (opP->index.reg != 0 && opP->index.reg >= DATA && opP->index.reg <= ADDR7) @@ -2190,7 +2397,8 @@ m68k_ip (instring) if ((opP->index.scale != 1 && cpu_of_arch (current_architecture) < m68020) || (opP->index.scale == 8 - && arch_coldfire_p (current_architecture))) + && (arch_coldfire_p (current_architecture) + && !arch_coldfire_fpu (current_architecture)))) { opP->error = _("scale factor invalid on this architecture; needs cpu32 or 68020 or higher"); @@ -2286,7 +2494,7 @@ m68k_ip (instring) } else { - nextword |= 0x40; /* No index reg */ + nextword |= 0x40; /* No index reg. */ if (opP->index.reg >= ZDATA0 && opP->index.reg <= ZDATA7) nextword |= (opP->index.reg - ZDATA0) << 12; @@ -2334,7 +2542,7 @@ m68k_ip (instring) break; } - /* Figure out innner displacement stuff */ + /* Figure out inner displacement stuff. */ if (opP->mode == POST || opP->mode == PRE) { if (cpu_of_arch (current_architecture) & cpu32) @@ -2395,7 +2603,7 @@ m68k_ip (instring) break; case ABSL: - nextword = get_num (&opP->disp, 80); + nextword = get_num (&opP->disp, 90); switch (opP->disp.size) { default: @@ -2424,7 +2632,7 @@ m68k_ip (instring) TAB (ABSTOPCREL, SZ_UNDEF)); break; } - /* Fall through into long */ + /* Fall through into long. */ case SIZE_LONG: if (isvar (&opP->disp)) add_fix ('l', &opP->disp, 0, 0); @@ -2437,7 +2645,8 @@ m68k_ip (instring) case SIZE_BYTE: as_bad (_("unsupported byte value; use a different suffix")); /* Fall through. */ - case SIZE_WORD: /* Word */ + + case SIZE_WORD: if (isvar (&opP->disp)) add_fix ('w', &opP->disp, 0, 0); @@ -2452,6 +2661,16 @@ m68k_ip (instring) as_bad (_("unknown/incorrect operand")); /* abort (); */ } + + /* If s[0] is '4', then this is for the mac instructions + that can have a trailing_ampersand set. If so, set 0x100 + bit on tmpreg so install_gen_operand can check for it and + set the appropriate bit (word2, bit 5). */ + if (s[0] == '4') + { + if (opP->trailing_ampersand) + tmpreg |= 0x100; + } install_gen_operand (s[1], tmpreg); break; @@ -2470,7 +2689,7 @@ m68k_ip (instring) break; case '3': default: - tmpreg = 80; + tmpreg = 90; break; } tmpreg = get_num (&opP->disp, tmpreg); @@ -2537,7 +2756,7 @@ m68k_ip (instring) break; case 'B': - tmpreg = get_num (&opP->disp, 80); + tmpreg = get_num (&opP->disp, 90); switch (s[1]) { case 'B': @@ -2557,7 +2776,7 @@ m68k_ip (instring) addword (0); break; case 'g': - if (subs (&opP->disp)) /* We can't relax it */ + if (subs (&opP->disp)) /* We can't relax it. */ goto long_branch; #ifdef OBJ_ELF @@ -2630,12 +2849,12 @@ m68k_ip (instring) } addword (0); break; - case 'C': /* Fixed size LONG coproc branches */ + case 'C': /* Fixed size LONG coproc branches. */ add_fix ('l', &opP->disp, 1, 0); addword (0); addword (0); break; - case 'c': /* Var size Coprocesssor branches */ + case 'c': /* Var size Coprocesssor branches. */ if (subs (&opP->disp) || (adds (&opP->disp) == 0)) { the_ins.opcode[the_ins.numo - 1] |= 0x40; @@ -2652,12 +2871,12 @@ m68k_ip (instring) } break; - case 'C': /* Ignore it */ + case 'C': /* Ignore it. */ break; - case 'd': /* JF this is a kludge */ + case 'd': /* JF this is a kludge. */ install_operand ('s', opP->reg - ADDR); - tmpreg = get_num (&opP->disp, 80); + tmpreg = get_num (&opP->disp, 90); if (!issword (tmpreg)) { as_warn (_("Expression out of range, using 0")); @@ -2670,14 +2889,22 @@ m68k_ip (instring) install_operand (s[1], opP->reg - DATA); break; - case 'E': /* Ignore it */ + case 'e': /* EMAC ACCx, reg/reg. */ + install_operand (s[1], opP->reg - ACC); + break; + + case 'E': /* Ignore it. */ break; case 'F': install_operand (s[1], opP->reg - FP0); break; - case 'G': /* Ignore it */ + case 'g': /* EMAC ACCEXTx. */ + install_operand (s[1], opP->reg - ACCEXT01); + break; + + case 'G': /* Ignore it. */ case 'H': break; @@ -2686,7 +2913,11 @@ m68k_ip (instring) install_operand (s[1], tmpreg); break; - case 'J': /* JF foo */ + case 'i': /* MAC/EMAC scale factor. */ + install_operand (s[1], opP->mode == LSH ? 0x1 : 0x3); + break; + + case 'J': /* JF foo. */ switch (opP->reg) { case SFC: @@ -2701,15 +2932,19 @@ m68k_ip (instring) case TC: tmpreg = 0x003; break; + case ACR0: case ITT0: tmpreg = 0x004; break; + case ACR1: case ITT1: tmpreg = 0x005; break; + case ACR2: case DTT0: tmpreg = 0x006; break; + case ACR3: case DTT1: tmpreg = 0x007; break; @@ -2747,15 +2982,67 @@ m68k_ip (instring) case ROMBAR: tmpreg = 0xC00; break; + case ROMBAR1: + tmpreg = 0xC01; + break; + case FLASHBAR: case RAMBAR0: tmpreg = 0xC04; break; + case RAMBAR: case RAMBAR1: tmpreg = 0xC05; break; + case MPCR: + tmpreg = 0xC0C; + break; + case EDRAMBAR: + tmpreg = 0xC0D; + break; + case MBAR0: + case SECMBAR: + tmpreg = 0xC0E; + break; + case MBAR1: case MBAR: tmpreg = 0xC0F; break; + case PCR1U0: + tmpreg = 0xD02; + break; + case PCR1L0: + tmpreg = 0xD03; + break; + case PCR2U0: + tmpreg = 0xD04; + break; + case PCR2L0: + tmpreg = 0xD05; + break; + case PCR3U0: + tmpreg = 0xD06; + break; + case PCR3L0: + tmpreg = 0xD07; + break; + case PCR1L1: + tmpreg = 0xD0A; + break; + case PCR1U1: + tmpreg = 0xD0B; + break; + case PCR2L1: + tmpreg = 0xD0C; + break; + case PCR2U1: + tmpreg = 0xD0D; + break; + case PCR3L1: + tmpreg = 0xD0E; + break; + case PCR3U1: + tmpreg = 0xD0F; + break; default: abort (); } @@ -2827,7 +3114,7 @@ m68k_ip (instring) case 'R': /* This depends on the fact that ADDR registers are eight more than their corresponding DATA regs, so the result - will have the ADDR_REG bit set */ + will have the ADDR_REG bit set. */ install_operand (s[1], opP->reg - DATA); break; @@ -2850,14 +3137,14 @@ m68k_ip (instring) install_operand (s[1], tmpreg); break; - case 'S': /* Ignore it */ + case 'S': /* Ignore it. */ break; case 'T': install_operand (s[1], get_num (&opP->disp, 30)); break; - case 'U': /* Ignore it */ + case 'U': /* Ignore it. */ break; case 'c': @@ -2877,7 +3164,7 @@ m68k_ip (instring) break; default: as_fatal (_("failed sanity check")); - } /* switch on cache token */ + } /* switch on cache token. */ install_operand (s[1], tmpreg); break; #ifndef NO_68851 @@ -3001,17 +3288,23 @@ m68k_ip (instring) tmpreg = get_num (&opP->disp, 20); install_operand (s[1], tmpreg); break; - case '_': /* used only for move16 absolute 32-bit address */ + case '_': /* used only for move16 absolute 32-bit address. */ if (isvar (&opP->disp)) add_fix ('l', &opP->disp, 0, 0); - tmpreg = get_num (&opP->disp, 80); + tmpreg = get_num (&opP->disp, 90); addword (tmpreg >> 16); addword (tmpreg & 0xFFFF); break; case 'u': install_operand (s[1], opP->reg - DATA0L); opP->reg -= (DATA0L); - opP->reg &= 0x0F; /* remove upper/lower bit */ + opP->reg &= 0x0F; /* remove upper/lower bit. */ + break; + case 'x': + tmpreg = get_num (&opP->disp, 80); + if (tmpreg == -1) + tmpreg = 0; + install_operand (s[1], tmpreg); break; default: abort (); @@ -3080,7 +3373,7 @@ install_operand (mode, val) switch (mode) { case 's': - the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge */ + the_ins.opcode[0] |= val & 0xFF; /* JF FF is for M kludge. */ break; case 'd': the_ins.opcode[0] |= val << 9; @@ -3135,7 +3428,7 @@ install_operand (mode, val) break; case 'j': the_ins.opcode[1] |= val; - the_ins.numo++; /* What a hack */ + the_ins.numo++; /* What a hack. */ break; case 'k': the_ins.opcode[1] |= val << 4; @@ -3157,30 +3450,51 @@ install_operand (mode, val) the_ins.opcode[0] |= ((val & 0x7) << 9); the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); break; - case 'n': + case 'n': /* MAC/EMAC Rx on !load. */ the_ins.opcode[0] |= ((val & 0x8) << (6 - 3)); the_ins.opcode[0] |= ((val & 0x7) << 9); + the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); break; - case 'o': + case 'o': /* MAC/EMAC Rx on load. */ the_ins.opcode[1] |= val << 12; the_ins.opcode[1] |= ((val & 0x10) << (7 - 4)); break; - case 'M': + case 'M': /* MAC/EMAC Ry on !load. */ the_ins.opcode[0] |= (val & 0xF); the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); break; - case 'N': + case 'N': /* MAC/EMAC Ry on load. */ the_ins.opcode[1] |= (val & 0xF); the_ins.opcode[1] |= ((val & 0x10) << (6 - 4)); break; case 'h': the_ins.opcode[1] |= ((val != 1) << 10); break; + case 'F': + the_ins.opcode[0] |= ((val & 0x3) << 9); + break; + case 'f': + the_ins.opcode[0] |= ((val & 0x3) << 0); + break; + case 'G': + the_ins.opcode[0] |= ((~val & 0x1) << 7); + the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); + break; + case 'H': + the_ins.opcode[0] |= ((val & 0x1) << 7); + the_ins.opcode[1] |= ((val & 0x2) << (4 - 1)); + break; + case 'I': + the_ins.opcode[1] |= ((val & 0x3) << 9); + break; + case ']': + the_ins.opcode[0] |= (val & 0x1) <<10; + break; case 'c': default: as_fatal (_("failed sanity check.")); } -} /* install_operand() */ +} static void install_gen_operand (mode, val) @@ -3189,6 +3503,11 @@ install_gen_operand (mode, val) { switch (mode) { + case '/': /* Special for mask loads for mac/msac insns with + possible mask; trailing_ampersend set in bit 8. */ + the_ins.opcode[0] |= (val & 0x3f); + the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5); + break; case 's': the_ins.opcode[0] |= val; break; @@ -3205,16 +3524,14 @@ install_gen_operand (mode, val) case 'p': the_ins.opcode[0] |= val; break; - /* more stuff goes here */ + /* more stuff goes here. */ default: as_fatal (_("failed sanity check.")); } -} /* install_gen_operand() */ +} -/* - * verify that we have some number of paren pairs, do m68k_ip_op(), and - * then deal with the bitfield hack. - */ +/* Verify that we have some number of paren pairs, do m68k_ip_op(), and + then deal with the bitfield hack. */ static char * crack_operand (str, opP) @@ -3240,7 +3557,7 @@ crack_operand (str, opP) else if (*str == ')') { if (!parens) - { /* ERROR */ + { /* ERROR. */ opP->error = _("Extra )"); return str; } @@ -3251,7 +3568,7 @@ crack_operand (str, opP) inquote = ! inquote; } if (!*str && parens) - { /* ERROR */ + { /* ERROR. */ opP->error = _("Missing )"); return str; } @@ -3264,7 +3581,7 @@ crack_operand (str, opP) } *str = c; if (c == '}') - c = *++str; /* JF bitfield hack */ + c = *++str; /* JF bitfield hack. */ if (c) { c = *++str; @@ -3378,56 +3695,87 @@ static const struct init_entry init_table[] = { "cc", CCR }, { "acc", ACC }, + { "acc0", ACC }, + { "acc1", ACC1 }, + { "acc2", ACC2 }, + { "acc3", ACC3 }, + { "accext01", ACCEXT01 }, + { "accext23", ACCEXT23 }, { "macsr", MACSR }, { "mask", MASK }, - /* control registers */ - { "sfc", SFC }, /* Source Function Code */ + /* Control registers. */ + { "sfc", SFC }, /* Source Function Code. */ { "sfcr", SFC }, - { "dfc", DFC }, /* Destination Function Code */ + { "dfc", DFC }, /* Destination Function Code. */ { "dfcr", DFC }, - { "cacr", CACR }, /* Cache Control Register */ - { "caar", CAAR }, /* Cache Address Register */ + { "cacr", CACR }, /* Cache Control Register. */ + { "caar", CAAR }, /* Cache Address Register. */ - { "usp", USP }, /* User Stack Pointer */ - { "vbr", VBR }, /* Vector Base Register */ - { "msp", MSP }, /* Master Stack Pointer */ - { "isp", ISP }, /* Interrupt Stack Pointer */ + { "usp", USP }, /* User Stack Pointer. */ + { "vbr", VBR }, /* Vector Base Register. */ + { "msp", MSP }, /* Master Stack Pointer. */ + { "isp", ISP }, /* Interrupt Stack Pointer. */ - { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0 */ - { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1 */ - { "dtt0", DTT0 }, /* Data Transparent Translation Register 0 */ - { "dtt1", DTT1 }, /* Data Transparent Translation Register 1 */ + { "itt0", ITT0 }, /* Instruction Transparent Translation Reg 0. */ + { "itt1", ITT1 }, /* Instruction Transparent Translation Reg 1. */ + { "dtt0", DTT0 }, /* Data Transparent Translation Register 0. */ + { "dtt1", DTT1 }, /* Data Transparent Translation Register 1. */ /* 68ec040 versions of same */ - { "iacr0", ITT0 }, /* Instruction Access Control Register 0 */ - { "iacr1", ITT1 }, /* Instruction Access Control Register 0 */ - { "dacr0", DTT0 }, /* Data Access Control Register 0 */ - { "dacr1", DTT1 }, /* Data Access Control Register 0 */ + { "iacr0", ITT0 }, /* Instruction Access Control Register 0. */ + { "iacr1", ITT1 }, /* Instruction Access Control Register 0. */ + { "dacr0", DTT0 }, /* Data Access Control Register 0. */ + { "dacr1", DTT1 }, /* Data Access Control Register 0. */ /* mcf5200 versions of same. The ColdFire programmer's reference manual indicated that the order is 2,3,0,1, but Ken Rose says that 0,1,2,3 is the correct order. */ - { "acr0", ITT0 }, /* Access Control Unit 0 */ - { "acr1", ITT1 }, /* Access Control Unit 1 */ - { "acr2", DTT0 }, /* Access Control Unit 2 */ - { "acr3", DTT1 }, /* Access Control Unit 3 */ + { "acr0", ACR0 }, /* Access Control Unit 0. */ + { "acr1", ACR1 }, /* Access Control Unit 1. */ + { "acr2", ACR2 }, /* Access Control Unit 2. */ + { "acr3", ACR3 }, /* Access Control Unit 3. */ - { "tc", TC }, /* MMU Translation Control Register */ + { "tc", TC }, /* MMU Translation Control Register. */ { "tcr", TC }, - { "mmusr", MMUSR }, /* MMU Status Register */ - { "srp", SRP }, /* User Root Pointer */ - { "urp", URP }, /* Supervisor Root Pointer */ + { "mmusr", MMUSR }, /* MMU Status Register. */ + { "srp", SRP }, /* User Root Pointer. */ + { "urp", URP }, /* Supervisor Root Pointer. */ { "buscr", BUSCR }, { "pcr", PCR }, - { "rombar", ROMBAR }, /* ROM Base Address Register */ - { "rambar0", RAMBAR0 }, /* ROM Base Address Register */ - { "rambar1", RAMBAR1 }, /* ROM Base Address Register */ - { "mbar", MBAR }, /* Module Base Address Register */ - /* end of control registers */ + { "rombar", ROMBAR }, /* ROM Base Address Register. */ + { "rambar0", RAMBAR0 }, /* ROM Base Address Register. */ + { "rambar1", RAMBAR1 }, /* ROM Base Address Register. */ + { "mbar", MBAR }, /* Module Base Address Register. */ + + { "mbar0", MBAR0 }, /* mcfv4e registers. */ + { "mbar1", MBAR1 }, /* mcfv4e registers. */ + { "rombar0", ROMBAR }, /* mcfv4e registers. */ + { "rombar1", ROMBAR1 }, /* mcfv4e registers. */ + { "mpcr", MPCR }, /* mcfv4e registers. */ + { "edrambar", EDRAMBAR }, /* mcfv4e registers. */ + { "secmbar", SECMBAR }, /* mcfv4e registers. */ + { "asid", TC }, /* mcfv4e registers. */ + { "mmubar", BUSCR }, /* mcfv4e registers. */ + { "pcr1u0", PCR1U0 }, /* mcfv4e registers. */ + { "pcr1l0", PCR1L0 }, /* mcfv4e registers. */ + { "pcr2u0", PCR2U0 }, /* mcfv4e registers. */ + { "pcr2l0", PCR2L0 }, /* mcfv4e registers. */ + { "pcr3u0", PCR3U0 }, /* mcfv4e registers. */ + { "pcr3l0", PCR3L0 }, /* mcfv4e registers. */ + { "pcr1u1", PCR1U1 }, /* mcfv4e registers. */ + { "pcr1l1", PCR1L1 }, /* mcfv4e registers. */ + { "pcr2u1", PCR2U1 }, /* mcfv4e registers. */ + { "pcr2l1", PCR2L1 }, /* mcfv4e registers. */ + { "pcr3u1", PCR3U1 }, /* mcfv4e registers. */ + { "pcr3l1", PCR3L1 }, /* mcfv4e registers. */ + + { "flashbar", FLASHBAR }, /* mcf528x registers. */ + { "rambar", RAMBAR }, /* mcf528x registers. */ + /* End of control registers. */ { "ac", AC }, { "bc", BC }, @@ -3461,10 +3809,10 @@ static const struct init_entry init_table[] = { "tt0", TT0 }, { "tt1", TT1 }, - /* 68ec030 versions of same */ + /* 68ec030 versions of same. */ { "ac0", TT0 }, { "ac1", TT1 }, - /* 68ec030 access control unit, identical to 030 MMU status reg */ + /* 68ec030 access control unit, identical to 030 MMU status reg. */ { "acusr", PSR }, /* Suppressed data and address registers. */ @@ -3619,7 +3967,7 @@ md_assemble (str) if (the_ins.nfrag == 0) { - /* No frag hacking involved; just put it out */ + /* No frag hacking involved; just put it out. */ toP = frag_more (2 * the_ins.numo); fromP = &the_ins.opcode[0]; for (m = the_ins.numo; m; --m) @@ -3628,7 +3976,7 @@ md_assemble (str) toP += 2; fromP++; } - /* put out symbol-dependent info */ + /* Put out symbol-dependent info. */ for (m = 0; m < the_ins.nrel; m++) { switch (the_ins.reloc[m].wid) @@ -3669,7 +4017,7 @@ md_assemble (str) return; } - /* There's some frag hacking */ + /* There's some frag hacking. */ { /* Calculate the max frag size. */ int wid; @@ -3781,7 +4129,7 @@ md_begin () const struct m68k_opcode *ins; struct m68k_incant *hack, *slak; - const char *retval = 0; /* empty string, or error msg text */ + const char *retval = 0; /* Empty string, or error msg text. */ int i; if (flag_mri) @@ -3807,7 +4155,7 @@ md_begin () slak->m_opnum = strlen (slak->m_operands) / 2; slak->m_arch = ins->arch; slak->m_opcode = ins->opcode; - /* This is kludgey */ + /* This is kludgey. */ slak->m_codenum = ((ins->match) & 0xffffL) ? 2 : 1; if (i + 1 != m68k_numopcodes && !strcmp (ins->name, m68k_opcodes[i + 1].name)) @@ -3923,7 +4271,7 @@ md_begin () #ifndef MIT_SYNTAX_ONLY /* Insert pseudo ops, these have to go into the opcode table since - gas expects pseudo ops to start with a dot */ + gas expects pseudo ops to start with a dot. */ { int n = 0; while (mote_pseudo_table[n].poc_name) @@ -3952,8 +4300,14 @@ static void select_control_regs () { /* Note which set of "movec" control registers is available. */ - switch (cpu_of_arch (current_architecture)) + switch (current_chip) { + case 0: + if (verbose) + as_warn (_("architecture not yet selected: defaulting to 68020")); + control_regs = m68020_control_regs; + break; + case m68000: control_regs = m68000_control_regs; break; @@ -3979,6 +4333,14 @@ select_control_regs () case mcf5407: control_regs = mcf_control_regs; break; + case mcf528x: + case mcf521x: + control_regs = mcf528x_control_regs; + break; + case mcf5470: + case mcf5480: + control_regs = mcfv4e_control_regs; + break; default: abort (); } @@ -4151,7 +4513,7 @@ m68k_mri_mode_change (on) } } -/* Equal to MAX_PRECISION in atof-ieee.c */ +/* Equal to MAX_PRECISION in atof-ieee.c. */ #define MAX_LITTLENUMS 6 /* Turn a string in input_line_pointer into a floating point constant @@ -4236,7 +4598,7 @@ md_apply_fix3 (fixP, valP, seg) to generate the code we want. */ char *buf = fixP->fx_frag->fr_literal; buf += fixP->fx_where; - /* end ibm compiler workaround */ + /* End ibm compiler workaround. */ val = ((val & 0xffffffff) ^ 0x80000000) - 0x80000000; @@ -4247,7 +4609,7 @@ md_apply_fix3 (fixP, valP, seg) if (fixP->fx_addsy) { memset (buf, 0, fixP->fx_size); - fixP->fx_addnumber = val; /* Remember value for emit_reloc */ + fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT && !S_IS_DEFINED (fixP->fx_addsy) @@ -4284,7 +4646,7 @@ md_apply_fix3 (fixP, valP, seg) *buf++ = (val >> 8); *buf++ = val; upper_limit = 0x7fffffff; - lower_limit = - (offsetT) 0x7fffffff - 1; /* avoid constant overflow */ + lower_limit = - (offsetT) 0x7fffffff - 1; /* Avoid constant overflow. */ break; default: BAD_CASE (fixP->fx_size); @@ -4345,7 +4707,7 @@ md_convert_frag_1 (fragP) want. */ register char *buffer_address = fragP->fr_literal; buffer_address += fragP->fr_fix; - /* end ibm compiler workaround */ + /* End ibm compiler workaround. */ /* The displacement of the address, from current location. */ disp = fragP->fr_symbol ? S_GET_VALUE (fragP->fr_symbol) : 0; @@ -4383,16 +4745,20 @@ md_convert_frag_1 (fragP) case TAB (BRABSJUNC, LONG): if (fragP->fr_opcode[0] == 0x61) /* jbsr */ { + if (flag_keep_pcrel) + as_fatal (_("Tried to convert PC relative BSR to absolute JSR")); fragP->fr_opcode[0] = 0x4E; - fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand */ + fragP->fr_opcode[1] = (char) 0xB9; /* JSR with ABSL LONG operand. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0, RELAX_RELOC_ABS32); fragP->fr_fix += 4; } else if (fragP->fr_opcode[0] == 0x60) /* jbra */ { + if (flag_keep_pcrel) + as_fatal (_("Tried to convert PC relative branch to absolute jump")); fragP->fr_opcode[0] = 0x4E; - fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand */ + fragP->fr_opcode[1] = (char) 0xF9; /* JMP with ABSL LONG operand. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0, RELAX_RELOC_ABS32); fragP->fr_fix += 4; @@ -4405,18 +4771,20 @@ md_convert_frag_1 (fragP) } break; case TAB (BRABSJCOND, LONG): - /* Only Bcc 68000 instructions can come here. */ - /* Change bcc into b!cc/jmp absl long. */ + if (flag_keep_pcrel) + as_fatal (_("Tried to convert PC relative conditional branch to absolute jump")); - fragP->fr_opcode[0] ^= 0x01; /* invert bcc */ - fragP->fr_opcode[1] = 0x6;/* branch offset = 6 */ + /* Only Bcc 68000 instructions can come here + Change bcc into b!cc/jmp absl long. */ + fragP->fr_opcode[0] ^= 0x01; /* Invert bcc. */ + fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */ /* JF: these used to be fr_opcode[2,3], but they may be in a - different frag, in which case refering to them is a no-no. + different frag, in which case referring to them is a no-no. Only fr_opcode[0,1] are guaranteed to work. */ *buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */ *buffer_address++ = (char) 0xf9; - fragP->fr_fix += 2; /* account for jmp instruction */ + fragP->fr_fix += 2; /* Account for jmp instruction. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0, RELAX_RELOC_ABS32); fragP->fr_fix += 4; @@ -4428,7 +4796,7 @@ md_convert_frag_1 (fragP) fragP->fr_fix += 2; break; case TAB (FBRANCH, LONG): - fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit */ + fragP->fr_opcode[1] |= 0x40; /* Turn on LONG bit. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1, RELAX_RELOC_PC32); fragP->fr_fix += 4; @@ -4440,35 +4808,39 @@ md_convert_frag_1 (fragP) fragP->fr_fix += 2; break; case TAB (DBCCLBR, LONG): - /* only DBcc instructions can come here */ - /* Change dbcc into dbcc/bral. */ + /* Only DBcc instructions can come here. + Change dbcc into dbcc/bral. + JF: these used to be fr_opcode[2-7], but that's wrong. */ + if (flag_keep_pcrel) + as_fatal (_("Tried to convert DBcc to absolute jump")); - /* JF: these used to be fr_opcode[2-7], but that's wrong */ - *buffer_address++ = 0x00; /* branch offset = 4 */ + *buffer_address++ = 0x00; /* Branch offset = 4. */ *buffer_address++ = 0x04; - *buffer_address++ = 0x60; /* put in bra pc+6 */ + *buffer_address++ = 0x60; /* Put in bra pc+6. */ *buffer_address++ = 0x06; *buffer_address++ = 0x60; /* Put in bral (0x60ff). */ *buffer_address++ = (char) 0xff; - fragP->fr_fix += 6; /* account for bra/jmp instructions */ + fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 1, RELAX_RELOC_PC32); fragP->fr_fix += 4; break; case TAB (DBCCABSJ, LONG): - /* only DBcc instructions can come here */ - /* Change dbcc into dbcc/jmp. */ + /* Only DBcc instructions can come here. + Change dbcc into dbcc/jmp. + JF: these used to be fr_opcode[2-7], but that's wrong. */ + if (flag_keep_pcrel) + as_fatal (_("Tried to convert PC relative conditional branch to absolute jump")); - /* JF: these used to be fr_opcode[2-7], but that's wrong */ - *buffer_address++ = 0x00; /* branch offset = 4 */ + *buffer_address++ = 0x00; /* Branch offset = 4. */ *buffer_address++ = 0x04; - *buffer_address++ = 0x60; /* put in bra pc+6 */ + *buffer_address++ = 0x60; /* Put in bra pc + 6. */ *buffer_address++ = 0x06; - *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ + *buffer_address++ = 0x4e; /* Put in jmp long (0x4ef9). */ *buffer_address++ = (char) 0xf9; - fragP->fr_fix += 6; /* account for bra/jmp instructions */ + fragP->fr_fix += 6; /* Account for bra/jmp instructions. */ fix_new (fragP, fragP->fr_fix, 4, fragP->fr_symbol, fragP->fr_offset, 0, RELAX_RELOC_ABS32); fragP->fr_fix += 4; @@ -4522,8 +4894,10 @@ md_convert_frag_1 (fragP) fragP->fr_fix += 2; break; case TAB (ABSTOPCREL, LONG): + if (flag_keep_pcrel) + as_fatal (_("Tried to convert PC relative conditional branch to absolute jump")); /* The thing to do here is force it to ABSOLUTE LONG, since - ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway */ + ABSTOPCREL is really trying to shorten an ABSOLUTE address anyway. */ if ((fragP->fr_opcode[1] & 0x3F) != 0x3A) abort (); fragP->fr_opcode[1] &= ~0x3F; @@ -4693,7 +5067,7 @@ md_estimate_size_before_relax (fragP, segment) /* the bit-field entries in the relocation_info struct plays hell with the byte-order problems of cross-assembly. So as a hack, I added this mach. dependent ri twiddler. Ugly, but it gets - you there. -KWK */ + you there. -KWK */ /* on m68k: first 4 bytes are normal unsigned long, next three bytes are symbolnum, most sig. byte first. Last byte is broken up with bit 7 as pcrel, bits 6 & 5 as length, bit 4 as pcrel, and the lower @@ -4706,17 +5080,17 @@ md_ri_to_chars (the_bytes, ri) char *the_bytes; struct reloc_info_generic *ri; { - /* this is easy */ + /* This is easy. */ md_number_to_chars (the_bytes, ri->r_address, 4); - /* now the fun stuff */ + /* Now the fun stuff. */ the_bytes[4] = (ri->r_symbolnum >> 16) & 0x0ff; - the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; - the_bytes[6] = ri->r_symbolnum & 0x0ff; + the_bytes[5] = (ri->r_symbolnum >> 8) & 0x0ff; + the_bytes[6] = ri->r_symbolnum & 0x0ff; the_bytes[7] = (((ri->r_pcrel << 7) & 0x80) | ((ri->r_length << 5) & 0x60) | ((ri->r_extern << 4) & 0x10)); } -#endif /* comment */ +#endif #ifndef BFD_ASSEMBLER void @@ -4730,7 +5104,7 @@ tc_aout_fix_to_chars (where, fixP, segment_address_in_file) * Out: GNU LD relocation length code: 0, 1, or 2. */ - static CONST unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; + static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2}; long r_symbolnum; know (fixP->fx_addsy != NULL); @@ -4754,8 +5128,8 @@ tc_aout_fix_to_chars (where, fixP, segment_address_in_file) #endif /* OBJ_AOUT or OBJ_BOUT */ #ifndef WORKING_DOT_WORD -CONST int md_short_jump_size = 4; -CONST int md_long_jump_size = 6; +const int md_short_jump_size = 4; +const int md_long_jump_size = 6; void md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) @@ -4781,8 +5155,10 @@ md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) { valueT offset; - if (!HAVE_LONG_BRANCH(current_architecture)) + if (!HAVE_LONG_BRANCH (current_architecture)) { + if (flag_keep_pcrel) + as_fatal (_("Tried to convert PC relative branch to absolute jump")); offset = to_addr - S_GET_VALUE (to_symbol); md_number_to_chars (ptr, (valueT) 0x4EF9, 2); md_number_to_chars (ptr + 2, (valueT) offset, 4); @@ -4803,17 +5179,16 @@ md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) aren't OK are an error (what a shock, no?) 0: Everything is OK - 10: Absolute 1:8 only - 20: Absolute 0:7 only - 30: absolute 0:15 only - 40: Absolute 0:31 only - 50: absolute 0:127 only + 10: Absolute 1:8 only + 20: Absolute 0:7 only + 30: absolute 0:15 only + 40: Absolute 0:31 only + 50: absolute 0:127 only 55: absolute -64:63 only - 60: absolute -128:127 only - 70: absolute 0:4095 only - 80: No bignums - - */ + 60: absolute -128:127 only + 70: absolute 0:4095 only + 80: absolute -1, 1:7 only + 90: No bignums. */ static int get_num (exp, ok) @@ -4822,7 +5197,7 @@ get_num (exp, ok) { if (exp->exp.X_op == O_absent) { - /* Do the same thing the VAX asm does */ + /* Do the same thing the VAX asm does. */ op (exp) = O_constant; adds (exp) = 0; subs (exp) = 0; @@ -4876,24 +5251,33 @@ get_num (exp, ok) offs (exp) = 0; } break; + case 80: + if (offs (exp) < -1 + || offs (exp) > 7 + || offs (exp) == 0) + { + as_warn (_("expression out of range: defaulting to 1")); + offs (exp) = 1; + } + break; default: break; } } else if (exp->exp.X_op == O_big) { - if (offs (exp) <= 0 /* flonum */ - && (ok == 80 /* no bignums */ - || (ok > 10 /* small-int ranges including 0 ok */ + if (offs (exp) <= 0 /* flonum. */ + && (ok == 90 /* no bignums */ + || (ok > 10 /* Small-int ranges including 0 ok. */ /* If we have a flonum zero, a zero integer should do as well (e.g., in moveq). */ && generic_floating_point_number.exponent == 0 && generic_floating_point_number.low[0] == 0))) { - /* HACK! Turn it into a long */ + /* HACK! Turn it into a long. */ LITTLENUM_TYPE words[6]; - gen_to_words (words, 2, 8L); /* These numbers are magic! */ + gen_to_words (words, 2, 8L); /* These numbers are magic! */ op (exp) = O_constant; adds (exp) = 0; subs (exp) = 0; @@ -4911,7 +5295,7 @@ get_num (exp, ok) } else { - if (ok >= 10 && ok <= 70) + if (ok >= 10 && ok <= 80) { op (exp) = O_constant; adds (exp) = 0; @@ -5040,6 +5424,7 @@ mri_chip () else current_architecture &= m68881 | m68851; current_architecture |= archs[i].arch; + current_chip |= archs[i].chip; while (*input_line_pointer == '/') { @@ -5256,7 +5641,7 @@ s_opt (ignore) } /* Skip ahead to a comma. This is used for OPT options which we do - not suppor tand which take arguments. */ + not support and which take arguments. */ static void skip_to_comma (arg, on) @@ -5418,6 +5803,7 @@ struct save_opts int keep_locals; int short_refs; int architecture; + int chip; int quick; int rel32; int listing; @@ -5443,6 +5829,7 @@ s_save (ignore) s->keep_locals = flag_keep_locals; s->short_refs = flag_short_refs; s->architecture = current_architecture; + s->chip = current_chip; s->quick = m68k_quick; s->rel32 = m68k_rel32; s->listing = listing; @@ -5477,6 +5864,7 @@ s_restore (ignore) flag_keep_locals = s->keep_locals; flag_short_refs = s->short_refs; current_architecture = s->architecture; + current_chip = s->chip; m68k_quick = s->quick; m68k_rel32 = s->rel32; listing = s->listing; @@ -5741,10 +6129,10 @@ swap_mri_condition (cc) { case MCC ('h', 'i'): return MCC ('c', 's'); case MCC ('l', 's'): return MCC ('c', 'c'); - /* is an alias for */ + /* is an alias for . */ case MCC ('h', 's'): case MCC ('c', 'c'): return MCC ('l', 's'); - /* is an alias for */ + /* is an alias for . */ case MCC ('l', 'o'): case MCC ('c', 's'): return MCC ('h', 'i'); case MCC ('p', 'l'): return MCC ('m', 'i'); @@ -5753,7 +6141,7 @@ swap_mri_condition (cc) case MCC ('l', 't'): return MCC ('g', 't'); case MCC ('g', 't'): return MCC ('l', 't'); case MCC ('l', 'e'): return MCC ('g', 'e'); - /* issue a warning for conditions we can not swap */ + /* Issue a warning for conditions we can not swap. */ case MCC ('n', 'e'): return MCC ('n', 'e'); // no problem here case MCC ('e', 'q'): return MCC ('e', 'q'); // also no problem case MCC ('v', 'c'): @@ -6047,7 +6435,7 @@ s_mri_if (qual) or at first column of a line (I think this can't actually happen here?) This is important when assembling: if d0 12(a0,d0*2) then - if d0 #CONST*20 then */ + if d0 #CONST*20 then. */ while ( ! ( is_end_of_line[(unsigned char) *s] || ( flag_mri && *s == '*' @@ -6442,12 +6830,11 @@ s_mri_for (qual) } /* We have fully parsed the FOR operands. Now build the loop. */ - n = push_mri_control (mri_for); buf = (char *) xmalloc (50 + (input_line_pointer - varstart)); - /* move init,var */ + /* Move init,var. */ s = buf; *s++ = 'm'; *s++ = 'o'; @@ -6466,7 +6853,7 @@ s_mri_for (qual) colon (n->top); - /* cmp end,var */ + /* cmp end,var. */ s = buf; *s++ = 'c'; *s++ = 'm'; @@ -6482,7 +6869,7 @@ s_mri_for (qual) *s = '\0'; mri_assemble (buf); - /* bcc bottom */ + /* bcc bottom. */ ex[0] = TOLOWER (extent); ex[1] = '\0'; if (up) @@ -6626,7 +7013,7 @@ s_mri_while (qual) or at first column of a line (I think this can't actually happen here?) This is important when assembling: while d0 12(a0,d0*2) do - while d0 #CONST*20 do */ + while d0 #CONST*20 do. */ while (! (is_end_of_line[(unsigned char) *s] || (flag_mri && *s == '*' @@ -6729,9 +7116,9 @@ s_mri_endw (ignore) */ #ifdef OBJ_ELF -CONST char *md_shortopts = "lSA:m:kQ:V"; +const char *md_shortopts = "lSA:m:kQ:V"; #else -CONST char *md_shortopts = "lSA:m:k"; +const char *md_shortopts = "lSA:m:k"; #endif struct option md_longopts[] = { @@ -6764,7 +7151,7 @@ md_parse_option (c, arg) switch (c) { case 'l': /* -l means keep external to 2 bit offset - rather than 16 bit one */ + rather than 16 bit one. */ flag_short_refs = 1; break; @@ -6781,7 +7168,7 @@ md_parse_option (c, arg) case 'A': if (*arg == 'm') arg++; - /* intentional fall-through */ + /* Intentional fall-through. */ case 'm': if (arg[0] == 'n' && arg[1] == 'o' && arg[2] == '-') @@ -6830,6 +7217,7 @@ md_parse_option (c, arg) { current_architecture &= ~m68000up; current_architecture |= arch; + current_chip |= archs[i].chip; } else if (arch == m68881) { @@ -6857,7 +7245,7 @@ md_parse_option (c, arg) case OPTION_PIC: case 'k': flag_want_pic = 1; - break; /* -pic, Position Independent Code */ + break; /* -pic, Position Independent Code. */ case OPTION_REGISTER_PREFIX_OPTIONAL: flag_reg_prefix_optional = 1; @@ -6919,7 +7307,8 @@ md_show_usage (stream) FILE *stream; { const char *default_cpu = TARGET_CPU; - int default_arch, i; + int i; + unsigned int default_arch; /* Get the canonical name for the default target CPU. */ if (*default_cpu == 'm') @@ -6946,7 +7335,8 @@ md_show_usage (stream) -l use 1 word for refs to undefined symbols [default 2]\n\ -m68000 | -m68008 | -m68010 | -m68020 | -m68030 | -m68040 | -m68060 |\n\ -m68302 | -m68331 | -m68332 | -m68333 | -m68340 | -m68360 | -mcpu32 |\n\ --m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m5307 | -m5407\n\ +-m5200 | -m5202 | -m5204 | -m5206 | -m5206e | -m521x | -m5249 |\n\ +-m528x | -m5307 | -m5407 | -m547x | -m548x | -mcfv4 | -mcfv4e\n\ specify variant of 680X0 architecture [default %s]\n\ -m68881 | -m68882 | -mno-68881 | -mno-68882\n\ target has/lacks floating-point coprocessor\n\ @@ -6972,8 +7362,8 @@ md_show_usage (stream) #ifdef TEST2 /* TEST2: Test md_assemble() */ -/* Warning, this routine probably doesn't work anymore */ - +/* Warning, this routine probably doesn't work anymore. */ +int main () { struct m68k_it the_ins; @@ -7142,7 +7532,7 @@ tc_coff_sizemachdep (frag) void m68k_elf_final_processing () { - /* Set file-specific flags if this is a cpu32 processor */ + /* Set file-specific flags if this is a cpu32 processor. */ if (cpu_of_arch (current_architecture) & cpu32) elf_elfheader (stdoutput)->e_flags |= EF_CPU32; else if ((cpu_of_arch (current_architecture) & m68000up) @@ -7150,3 +7540,34 @@ m68k_elf_final_processing () elf_elfheader (stdoutput)->e_flags |= EF_M68000; } #endif + +int +tc_m68k_regname_to_dw2regnum (const char *regname) +{ + unsigned int regnum; + static const char *const regnames[] = + { + "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", + "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", + "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", + "pc" + }; + + for (regnum = 0; regnum < ARRAY_SIZE (regnames); regnum++) + if (strcmp (regname, regnames[regnum]) == 0) + return regnum; + + return -1; +} + +void +tc_m68k_frame_initial_instructions (void) +{ + static int sp_regno = -1; + + if (sp_regno < 0) + sp_regno = tc_m68k_regname_to_dw2regnum ("sp"); + + cfi_add_CFA_def_cfa (sp_regno, -DWARF2_CIE_DATA_ALIGNMENT); + cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, DWARF2_CIE_DATA_ALIGNMENT); +}