X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fconfig%2Ftc-mep.c;h=4a03c5bf21ce7a29d4c7a37f7e35307ad41fa7ee;hb=f42f1a1d6ca0cc84e43d7f2b85044a2565ca00f2;hp=4e3c874c095c9b3e21e17bbac997e4c1a865097d;hpb=20203fb9399bed63f555d79dcd8ad95a5bb0aed6;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/config/tc-mep.c b/gas/config/tc-mep.c index 4e3c874c09..4a03c5bf21 100644 --- a/gas/config/tc-mep.c +++ b/gas/config/tc-mep.c @@ -1,6 +1,5 @@ /* tc-mep.c -- Assembler for the Toshiba Media Processor. - Copyright (C) 2001, 2002, 2003, 2004, 2005, 2007 - Free Software Foundation. Inc. + Copyright (C) 2001-2017 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. @@ -19,8 +18,8 @@ the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ -#include #include "as.h" +#include #include "dwarf2dbg.h" #include "subsegs.h" #include "symcat.h" @@ -29,7 +28,6 @@ #include "cgen.h" #include "elf/common.h" #include "elf/mep.h" -#include "libbfd.h" #include "xregex.h" /* Structure to hold all of the different components describing @@ -80,8 +78,6 @@ static void mep_noregerr (int); const pseudo_typeS md_pseudo_table[] = { { "word", cons, 4 }, - { "file", (void (*) (int)) dwarf2_directive_file, 0 }, - { "loc", dwarf2_directive_loc, 0 }, { "vliw", mep_switch_to_vliw_mode, 0 }, { "core", mep_switch_to_core_mode, 0 }, { "vtext", mep_s_vtext, 0 }, @@ -198,7 +194,7 @@ static int optbits = 0; static int optbitset = 0; int -md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) +md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) { int i, idx; switch (c) @@ -446,7 +442,7 @@ mep_machine (void) /* The MeP version of the cgen parse_operand function. The only difference from the standard version is that we want to avoid treating '$foo' and '($foo...)' as references to a symbol called '$foo'. The chances are - that '$foo' is really a misspelt register. */ + that '$foo' is really a misspelled register. */ static const char * mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want, @@ -468,7 +464,7 @@ mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want, } void -md_begin () +md_begin (void) { /* Initialize the `cgen' interface. */ @@ -489,12 +485,12 @@ md_begin () mep_cop = mep_config_map[mep_config_index].cpu_flag & EF_MEP_COP_MASK; /* Set the machine number and endian. */ - gas_cgen_cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, + gas_cgen_cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0U, CGEN_CPU_OPEN_ENDIAN, target_big_endian ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE, - CGEN_CPU_OPEN_ISAS, 0, + CGEN_CPU_OPEN_ISAS, (CGEN_BITSET *) 0, CGEN_CPU_OPEN_END); mep_cgen_init_asm (gas_cgen_cpu_desc); @@ -511,7 +507,7 @@ md_begin () gas_cgen_initialize_saved_fixups_array(); } -/* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a +/* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a coprocessor instruction, if possible, into FIELDS, BUF, and INSN. */ static const CGEN_INSN * @@ -526,14 +522,14 @@ mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd, const char *errmsg = NULL; /* The instructions are stored in hashed lists. */ - ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc, + ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc, CGEN_INSN_MNEMONIC (pinsn)); start = str; for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) { const CGEN_INSN *insn = ilist->insn; - if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn), + if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn), CGEN_INSN_MNEMONIC (pinsn)) == 0 && MEP_INSN_COP_P (ilist->insn) && mep_cgen_insn_supported (cd, insn)) @@ -551,7 +547,7 @@ mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd, errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); if (errmsg != NULL) continue; - + errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, (bfd_vma) 0); if (errmsg != NULL) @@ -586,7 +582,7 @@ mep_check_parallel32_scheduling (void) an internally parallel core or an internally parallel coprocessor, neither of which are supported at this time. */ if ( num_insns_saved > 2 ) - as_fatal("Internally paralled cores and coprocessors not supported."); + as_fatal("Internally paralleled cores and coprocessors not supported."); /* If there are no insns saved, that's ok. Just return. This will happen when mep_process_saved_insns is called when the end of the @@ -615,7 +611,7 @@ mep_check_parallel32_scheduling (void) as_bad (_("core and copro insn lengths must total 32 bits.")); } else - as_bad (_("vliw group must consist of 1 core and 1 copro insn.")); + as_bad (_("vliw group must consist of 1 core and 1 copro insn.")); } else { @@ -625,7 +621,7 @@ mep_check_parallel32_scheduling (void) 1. The instruction is a 32 bit core or coprocessor insn and can be executed by itself. Valid. - 2. The instrucion is a core instruction for which a cop nop + 2. The instruction is a core instruction for which a cop nop exists. In this case, insert the cop nop into the saved insn array after the core insn and return. Valid. @@ -651,17 +647,17 @@ mep_check_parallel32_scheduling (void) CGEN_INSN_VLIW32_NO_MATCHING_NOP)) as_fatal ("No valid nop."); - /* At this point we know that we have a single 16-bit insn that has - a matching nop. We have to assemble it and put it into the saved + /* At this point we know that we have a single 16-bit insn that has + a matching nop. We have to assemble it and put it into the saved insn and fixup chain arrays. */ if (insn0iscopro) { char *errmsg; mep_insn insn; - + /* Move the insn and it's fixups to the second element of the - saved insns arrary and insert a 16 bit core nope into the + saved insns array and insert a 16 bit core nope into the first element. */ insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop", &insn.fields, insn.buffer, @@ -674,7 +670,7 @@ mep_check_parallel32_scheduling (void) /* Move the insn in element 0 to element 1 and insert the nop into element 0. Move the fixups in element 0 to - element 1 and save the current fixups to element 0. + element 1 and save the current fixups to element 0. Really there aren't any fixups at this point because we're inserting a nop but we might as well be general so that if there's ever a need to insert a general insn, we'll @@ -762,7 +758,7 @@ mep_check_parallel64_scheduling (void) 1. The instruction is a 64 bit coprocessor insn and can be executed by itself. Valid. - 2. The instrucion is a core instruction for which a cop nop + 2. The instruction is a core instruction for which a cop nop exists. In this case, insert the cop nop into the saved insn array after the core insn and return. Valid. @@ -777,7 +773,7 @@ mep_check_parallel64_scheduling (void) we have to abort. */ /* If the insn is 64 bits long, it can run alone. The size check - is done indepependantly of whether the insn is core or copro + is done independently of whether the insn is core or copro in case 64 bit coprocessor insns are added later. */ if (insn0length == 64) return; @@ -821,7 +817,7 @@ mep_check_parallel64_scheduling (void) nop has been added, then make the necessary changes and handle its assembly and insertion here. Otherwise, go figure out why either: - + 1. The assembler thinks that there is a 32-bit core nop to match a 32-bit coprocessor insn, or 2. The assembler thinks that there is a 48-bit core nop @@ -838,7 +834,7 @@ mep_check_parallel64_scheduling (void) /* Move the insn in element 0 to element 1 and insert the nop into element 0. Move the fixups in element 0 to - element 1 and save the current fixups to element 0. + element 1 and save the current fixups to element 0. Really there aren't any fixups at this point because we're inserting a nop but we might as well be general so that if there's ever a need to insert a general insn, we'll @@ -1149,15 +1145,15 @@ mep_check_ivc2_scheduling (void) #endif /* MEP_IVC2_SUPPORTED */ /* The scheduling functions are just filters for invalid combinations. - If there is a violation, they terminate assembly. Otherise they - just fall through. Succesful combinations cause no side effects + If there is a violation, they terminate assembly. Otherwise they + just fall through. Successful combinations cause no side effects other than valid nop insertion. */ static void mep_check_parallel_scheduling (void) { /* This is where we will eventually read the config information - and choose which scheduling checking function to call. */ + and choose which scheduling checking function to call. */ #ifdef MEP_IVC2_SUPPORTED if (mep_cop == EF_MEP_COP_IVC2) mep_check_ivc2_scheduling (); @@ -1223,7 +1219,7 @@ md_assemble (char * str) + copro insn We want to handle the general case where more than - one instruction can be preceeded by a +. This will + one instruction can be preceded by a +. This will happen later if we add support for internally parallel coprocessors. We'll make the parsing nice and general so that it can handle an arbitrary number of insns @@ -1247,9 +1243,9 @@ md_assemble (char * str) int thisInsnIsCopro = 0; mep_insn insn; int i; - + /* Initialize the insn buffer */ - + if (! CGEN_INT_INSN_P) for (i=0; i < CGEN_MAX_INSN_SIZE; i++) insn.buffer[i]='\0'; @@ -1303,7 +1299,7 @@ md_assemble (char * str) /* Check for a + with a core insn and abort if found. */ if (!thisInsnIsCopro) { - as_fatal("A core insn cannot be preceeded by a +.\n"); + as_fatal("A core insn cannot be preceded by a +.\n"); return; } @@ -1385,7 +1381,7 @@ valueT md_section_align (segT segment, valueT size) { int align = bfd_get_section_alignment (stdoutput, segment); - return ((size + (1 << align) - 1) & (-1 << align)); + return ((size + (1 << align) - 1) & -(1 << align)); } @@ -1529,6 +1525,7 @@ md_estimate_size_before_relax (fragS * fragP, segT segment) fragP->fr_subtype = insn_to_subtype (fragP->fr_cgen.insn->base->num); if (S_GET_SEGMENT (fragP->fr_symbol) != segment + || S_IS_WEAK (fragP->fr_symbol) #ifdef MEP_IVC2_SUPPORTED || (mep_cop == EF_MEP_COP_IVC2 && bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW) @@ -1548,7 +1545,7 @@ md_estimate_size_before_relax (fragS * fragP, segT segment) switch (fragP->fr_cgen.insn->base->num) { case MEP_INSN_BSR12: - fragP->fr_subtype = insn_to_subtype + fragP->fr_subtype = insn_to_subtype (subtype_mappings[fragP->fr_subtype].insn_for_extern); break; case MEP_INSN_BEQZ: @@ -1616,7 +1613,7 @@ target_address_for (fragS *frag) } void -md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, +md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT seg ATTRIBUTE_UNUSED, fragS *fragP) { @@ -1711,7 +1708,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, operand = MEP_OPERAND_PCREL17A2; break; } - /* ...FALLTHROUGH... */ + /* Fall through. */ case MEP_INSN_JMP: addend = target_address_for (fragP); @@ -1726,6 +1723,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, case MEP_INSN_BNEZ: bit = 1; + /* Fall through. */ case MEP_INSN_BEQZ: fragP->fr_opcode[1^e] = bit | (addend & 0xfe); operand = MEP_OPERAND_PCREL8A2; @@ -1733,6 +1731,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, case MEP_INSN_BNEI: bit = 4; + /* Fall through. */ case MEP_INSN_BEQI: if (subtype_mappings[fragP->fr_subtype].growth) { @@ -1764,6 +1763,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, } if (S_GET_SEGMENT (fragP->fr_symbol) != seg + || S_IS_WEAK (fragP->fr_symbol) || operand == MEP_OPERAND_PCABS24A2) { gas_assert (fragP->fr_cgen.insn != 0); @@ -1800,7 +1800,7 @@ mep_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) break; } - /* Now call cgen's md_aply_fix. */ + /* Now call cgen's md_apply_fix. */ gas_cgen_md_apply_fix (fixP, valP, seg); } @@ -1809,11 +1809,17 @@ md_pcrel_from_section (fixS *fixP, segT sec) { if (fixP->fx_addsy != (symbolS *) NULL && (! S_IS_DEFINED (fixP->fx_addsy) + || S_IS_WEAK (fixP->fx_addsy) || S_GET_SEGMENT (fixP->fx_addsy) != sec)) /* The symbol is undefined (or is defined but not in this section). Let the linker figure it out. */ return 0; + /* If we've got other reasons for emitting this relocation, let the + linker handle pc-rel also. */ + if (mep_force_relocation (fixP)) + return 0; + /* Return the address of the opcode - cgen adjusts for opcode size itself, to be consistent with the disassembler, which must do so. */ @@ -1861,7 +1867,7 @@ md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED, #ifdef OBJ_COMPLEX_RELC /* coalescing this into RELOC_MEP_16 is actually a bug, since it's a signed operand. let the relc code handle it. */ - return BFD_RELOC_RELC; + return BFD_RELOC_RELC; #endif case MEP_OPERAND_UIMM16: @@ -1874,7 +1880,7 @@ md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED, default: #ifdef OBJ_COMPLEX_RELC - /* this is not an error, yet. + /* this is not an error, yet. pass it to the linker. */ return BFD_RELOC_RELC; #endif @@ -1929,7 +1935,7 @@ mep_cgen_record_fixup_exp (fragS *frag, tc_gen_reloc. */ void -mep_frob_file () +mep_frob_file (void) { struct mep_hi_fixup * l; @@ -2013,6 +2019,9 @@ mep_force_relocation (fixS *fixp) || fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) return 1; + if (generic_force_reloc (fixp)) + return 1; + /* Allow branches to global symbols to be resolved at assembly time. This is consistent with way relaxable branches are handled, since branches to both global and local symbols are relaxed. It also @@ -2031,7 +2040,7 @@ md_number_to_chars (char *buf, valueT val, int n) number_to_chars_littleendian (buf, val, n); } -char * +const char * md_atof (int type, char *litP, int *sizeP) { return ieee_md_atof (type, litP, sizeP, TRUE); @@ -2072,13 +2081,13 @@ mep_fix_adjustable (fixS *fixP) } bfd_vma -mep_elf_section_letter (int letter, char **ptrmsg) +mep_elf_section_letter (int letter, const char **ptrmsg) { if (letter == 'v') return SHF_MEP_VLIW; - *ptrmsg = _("Bad .section directive: want a,v,w,x,M,S in string"); - return 0; + *ptrmsg = _("bad .section directive: want a,v,w,x,M,S in string"); + return -1; } flagword @@ -2176,7 +2185,7 @@ mep_cleanup (void) { /* Take care of any insns left to be parallelized when the file ends. This is mainly here to handle the case where the file ends with an - insn preceeded by a + or the file ends unexpectedly. */ + insn preceded by a + or the file ends unexpectedly. */ if (mode == VLIW) mep_process_saved_insns (); } @@ -2190,5 +2199,5 @@ mep_flush_pending_output (void) pluspresent = 0; } - return 1; + return 1; }