X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fconfig%2Ftc-mep.c;h=6128b6e66901db6111c1eb84dceeaf633d7c9a13;hb=97f50151221de0a023a8317559b1992a90f9cb8f;hp=511d9686599b7a9a4e83292070701a60c5e1a833;hpb=85143216ca14d79b3e384a1bcb871890a8ac7659;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/config/tc-mep.c b/gas/config/tc-mep.c index 511d968659..6128b6e669 100644 --- a/gas/config/tc-mep.c +++ b/gas/config/tc-mep.c @@ -1,6 +1,5 @@ /* tc-mep.c -- Assembler for the Toshiba Media Processor. - Copyright (C) 2001, 2002, 2003, 2004, 2005, 2007 - Free Software Foundation. Inc. + Copyright (C) 2001-2016 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. @@ -19,8 +18,8 @@ the Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ -#include #include "as.h" +#include #include "dwarf2dbg.h" #include "subsegs.h" #include "symcat.h" @@ -80,8 +79,6 @@ static void mep_noregerr (int); const pseudo_typeS md_pseudo_table[] = { { "word", cons, 4 }, - { "file", (void (*) (int)) dwarf2_directive_file, 0 }, - { "loc", dwarf2_directive_loc, 0 }, { "vliw", mep_switch_to_vliw_mode, 0 }, { "core", mep_switch_to_core_mode, 0 }, { "vtext", mep_s_vtext, 0 }, @@ -198,7 +195,7 @@ static int optbits = 0; static int optbitset = 0; int -md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) +md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) { int i, idx; switch (c) @@ -468,7 +465,7 @@ mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want, } void -md_begin () +md_begin (void) { /* Initialize the `cgen' interface. */ @@ -489,12 +486,12 @@ md_begin () mep_cop = mep_config_map[mep_config_index].cpu_flag & EF_MEP_COP_MASK; /* Set the machine number and endian. */ - gas_cgen_cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, + gas_cgen_cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0U, CGEN_CPU_OPEN_ENDIAN, target_big_endian ? CGEN_ENDIAN_BIG : CGEN_ENDIAN_LITTLE, - CGEN_CPU_OPEN_ISAS, 0, + CGEN_CPU_OPEN_ISAS, (CGEN_BITSET *) 0, CGEN_CPU_OPEN_END); mep_cgen_init_asm (gas_cgen_cpu_desc); @@ -511,7 +508,7 @@ md_begin () gas_cgen_initialize_saved_fixups_array(); } -/* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a +/* Variant of mep_cgen_assemble_insn. Assemble insn STR of cpu CD as a coprocessor instruction, if possible, into FIELDS, BUF, and INSN. */ static const CGEN_INSN * @@ -526,14 +523,14 @@ mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd, const char *errmsg = NULL; /* The instructions are stored in hashed lists. */ - ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc, + ilist = CGEN_ASM_LOOKUP_INSN (gas_cgen_cpu_desc, CGEN_INSN_MNEMONIC (pinsn)); start = str; for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) { const CGEN_INSN *insn = ilist->insn; - if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn), + if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn), CGEN_INSN_MNEMONIC (pinsn)) == 0 && MEP_INSN_COP_P (ilist->insn) && mep_cgen_insn_supported (cd, insn)) @@ -551,7 +548,7 @@ mep_cgen_assemble_cop_insn (CGEN_CPU_DESC cd, errmsg = CGEN_PARSE_FN (cd, insn) (cd, insn, & str, fields); if (errmsg != NULL) continue; - + errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, (bfd_vma) 0); if (errmsg != NULL) @@ -615,7 +612,7 @@ mep_check_parallel32_scheduling (void) as_bad (_("core and copro insn lengths must total 32 bits.")); } else - as_bad (_("vliw group must consist of 1 core and 1 copro insn.")); + as_bad (_("vliw group must consist of 1 core and 1 copro insn.")); } else { @@ -651,15 +648,15 @@ mep_check_parallel32_scheduling (void) CGEN_INSN_VLIW32_NO_MATCHING_NOP)) as_fatal ("No valid nop."); - /* At this point we know that we have a single 16-bit insn that has - a matching nop. We have to assemble it and put it into the saved + /* At this point we know that we have a single 16-bit insn that has + a matching nop. We have to assemble it and put it into the saved insn and fixup chain arrays. */ if (insn0iscopro) { char *errmsg; mep_insn insn; - + /* Move the insn and it's fixups to the second element of the saved insns arrary and insert a 16 bit core nope into the first element. */ @@ -674,7 +671,7 @@ mep_check_parallel32_scheduling (void) /* Move the insn in element 0 to element 1 and insert the nop into element 0. Move the fixups in element 0 to - element 1 and save the current fixups to element 0. + element 1 and save the current fixups to element 0. Really there aren't any fixups at this point because we're inserting a nop but we might as well be general so that if there's ever a need to insert a general insn, we'll @@ -821,7 +818,7 @@ mep_check_parallel64_scheduling (void) nop has been added, then make the necessary changes and handle its assembly and insertion here. Otherwise, go figure out why either: - + 1. The assembler thinks that there is a 32-bit core nop to match a 32-bit coprocessor insn, or 2. The assembler thinks that there is a 48-bit core nop @@ -838,7 +835,7 @@ mep_check_parallel64_scheduling (void) /* Move the insn in element 0 to element 1 and insert the nop into element 0. Move the fixups in element 0 to - element 1 and save the current fixups to element 0. + element 1 and save the current fixups to element 0. Really there aren't any fixups at this point because we're inserting a nop but we might as well be general so that if there's ever a need to insert a general insn, we'll @@ -1157,7 +1154,7 @@ static void mep_check_parallel_scheduling (void) { /* This is where we will eventually read the config information - and choose which scheduling checking function to call. */ + and choose which scheduling checking function to call. */ #ifdef MEP_IVC2_SUPPORTED if (mep_cop == EF_MEP_COP_IVC2) mep_check_ivc2_scheduling (); @@ -1247,9 +1244,9 @@ md_assemble (char * str) int thisInsnIsCopro = 0; mep_insn insn; int i; - + /* Initialize the insn buffer */ - + if (! CGEN_INT_INSN_P) for (i=0; i < CGEN_MAX_INSN_SIZE; i++) insn.buffer[i]='\0'; @@ -1385,7 +1382,7 @@ valueT md_section_align (segT segment, valueT size) { int align = bfd_get_section_alignment (stdoutput, segment); - return ((size + (1 << align) - 1) & (-1 << align)); + return ((size + (1 << align) - 1) & -(1 << align)); } @@ -1549,7 +1546,7 @@ md_estimate_size_before_relax (fragS * fragP, segT segment) switch (fragP->fr_cgen.insn->base->num) { case MEP_INSN_BSR12: - fragP->fr_subtype = insn_to_subtype + fragP->fr_subtype = insn_to_subtype (subtype_mappings[fragP->fr_subtype].insn_for_extern); break; case MEP_INSN_BEQZ: @@ -1617,7 +1614,7 @@ target_address_for (fragS *frag) } void -md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, +md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT seg ATTRIBUTE_UNUSED, fragS *fragP) { @@ -1817,6 +1814,11 @@ md_pcrel_from_section (fixS *fixP, segT sec) Let the linker figure it out. */ return 0; + /* If we've got other reasons for emitting this relocation, let the + linker handle pc-rel also. */ + if (mep_force_relocation (fixP)) + return 0; + /* Return the address of the opcode - cgen adjusts for opcode size itself, to be consistent with the disassembler, which must do so. */ @@ -1864,7 +1866,7 @@ md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED, #ifdef OBJ_COMPLEX_RELC /* coalescing this into RELOC_MEP_16 is actually a bug, since it's a signed operand. let the relc code handle it. */ - return BFD_RELOC_RELC; + return BFD_RELOC_RELC; #endif case MEP_OPERAND_UIMM16: @@ -1877,7 +1879,7 @@ md_cgen_lookup_reloc (const CGEN_INSN *insn ATTRIBUTE_UNUSED, default: #ifdef OBJ_COMPLEX_RELC - /* this is not an error, yet. + /* this is not an error, yet. pass it to the linker. */ return BFD_RELOC_RELC; #endif @@ -1932,7 +1934,7 @@ mep_cgen_record_fixup_exp (fragS *frag, tc_gen_reloc. */ void -mep_frob_file () +mep_frob_file (void) { struct mep_hi_fixup * l; @@ -2037,7 +2039,7 @@ md_number_to_chars (char *buf, valueT val, int n) number_to_chars_littleendian (buf, val, n); } -char * +const char * md_atof (int type, char *litP, int *sizeP) { return ieee_md_atof (type, litP, sizeP, TRUE); @@ -2078,13 +2080,13 @@ mep_fix_adjustable (fixS *fixP) } bfd_vma -mep_elf_section_letter (int letter, char **ptrmsg) +mep_elf_section_letter (int letter, const char **ptrmsg) { if (letter == 'v') return SHF_MEP_VLIW; - *ptrmsg = _("Bad .section directive: want a,v,w,x,M,S in string"); - return 0; + *ptrmsg = _("bad .section directive: want a,v,w,x,M,S in string"); + return -1; } flagword @@ -2196,5 +2198,5 @@ mep_flush_pending_output (void) pluspresent = 0; } - return 1; + return 1; }