X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fconfig%2Ftc-mep.c;h=6b52841fa9dacd799cb174a9fe021258007a95af;hb=53fc67f8b2663261810353ae8e4f9920ae7a1c56;hp=780356f07ff0f8959b64705cb603322e3bc05f14;hpb=3739860c11a9cfcdaa4d5d204ea3536784de7bb3;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/config/tc-mep.c b/gas/config/tc-mep.c index 780356f07f..6b52841fa9 100644 --- a/gas/config/tc-mep.c +++ b/gas/config/tc-mep.c @@ -1,5 +1,5 @@ /* tc-mep.c -- Assembler for the Toshiba Media Processor. - Copyright (C) 2001-2015 Free Software Foundation, Inc. + Copyright (C) 2001-2020 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler. @@ -28,7 +28,6 @@ #include "cgen.h" #include "elf/common.h" #include "elf/mep.h" -#include "libbfd.h" #include "xregex.h" /* Structure to hold all of the different components describing @@ -195,7 +194,7 @@ static int optbits = 0; static int optbitset = 0; int -md_parse_option (int c, char *arg ATTRIBUTE_UNUSED) +md_parse_option (int c, const char *arg ATTRIBUTE_UNUSED) { int i, idx; switch (c) @@ -443,7 +442,7 @@ mep_machine (void) /* The MeP version of the cgen parse_operand function. The only difference from the standard version is that we want to avoid treating '$foo' and '($foo...)' as references to a symbol called '$foo'. The chances are - that '$foo' is really a misspelt register. */ + that '$foo' is really a misspelled register. */ static const char * mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want, @@ -465,7 +464,7 @@ mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want, } void -md_begin () +md_begin (void) { /* Initialize the `cgen' interface. */ @@ -583,7 +582,7 @@ mep_check_parallel32_scheduling (void) an internally parallel core or an internally parallel coprocessor, neither of which are supported at this time. */ if ( num_insns_saved > 2 ) - as_fatal("Internally paralled cores and coprocessors not supported."); + as_fatal("Internally paralleled cores and coprocessors not supported."); /* If there are no insns saved, that's ok. Just return. This will happen when mep_process_saved_insns is called when the end of the @@ -622,7 +621,7 @@ mep_check_parallel32_scheduling (void) 1. The instruction is a 32 bit core or coprocessor insn and can be executed by itself. Valid. - 2. The instrucion is a core instruction for which a cop nop + 2. The instruction is a core instruction for which a cop nop exists. In this case, insert the cop nop into the saved insn array after the core insn and return. Valid. @@ -658,7 +657,7 @@ mep_check_parallel32_scheduling (void) mep_insn insn; /* Move the insn and it's fixups to the second element of the - saved insns arrary and insert a 16 bit core nope into the + saved insns array and insert a 16 bit core nope into the first element. */ insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop", &insn.fields, insn.buffer, @@ -759,7 +758,7 @@ mep_check_parallel64_scheduling (void) 1. The instruction is a 64 bit coprocessor insn and can be executed by itself. Valid. - 2. The instrucion is a core instruction for which a cop nop + 2. The instruction is a core instruction for which a cop nop exists. In this case, insert the cop nop into the saved insn array after the core insn and return. Valid. @@ -774,7 +773,7 @@ mep_check_parallel64_scheduling (void) we have to abort. */ /* If the insn is 64 bits long, it can run alone. The size check - is done indepependantly of whether the insn is core or copro + is done independently of whether the insn is core or copro in case 64 bit coprocessor insns are added later. */ if (insn0length == 64) return; @@ -1112,7 +1111,7 @@ mep_check_ivc2_scheduling (void) #if CGEN_INT_INSN_P cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) temp, 32, - m->buffer[0]); + m->buffer[0], gas_cgen_cpu_desc->insn_endian); #else memcpy (temp, m->buffer, byte_len); #endif @@ -1146,8 +1145,8 @@ mep_check_ivc2_scheduling (void) #endif /* MEP_IVC2_SUPPORTED */ /* The scheduling functions are just filters for invalid combinations. - If there is a violation, they terminate assembly. Otherise they - just fall through. Succesful combinations cause no side effects + If there is a violation, they terminate assembly. Otherwise they + just fall through. Successful combinations cause no side effects other than valid nop insertion. */ static void @@ -1220,7 +1219,7 @@ md_assemble (char * str) + copro insn We want to handle the general case where more than - one instruction can be preceeded by a +. This will + one instruction can be preceded by a +. This will happen later if we add support for internally parallel coprocessors. We'll make the parsing nice and general so that it can handle an arbitrary number of insns @@ -1300,7 +1299,7 @@ md_assemble (char * str) /* Check for a + with a core insn and abort if found. */ if (!thisInsnIsCopro) { - as_fatal("A core insn cannot be preceeded by a +.\n"); + as_fatal("A core insn cannot be preceded by a +.\n"); return; } @@ -1381,8 +1380,8 @@ md_assemble (char * str) valueT md_section_align (segT segment, valueT size) { - int align = bfd_get_section_alignment (stdoutput, segment); - return ((size + (1 << align) - 1) & (-1 << align)); + int align = bfd_section_alignment (segment); + return ((size + (1 << align) - 1) & -(1 << align)); } @@ -1529,7 +1528,7 @@ md_estimate_size_before_relax (fragS * fragP, segT segment) || S_IS_WEAK (fragP->fr_symbol) #ifdef MEP_IVC2_SUPPORTED || (mep_cop == EF_MEP_COP_IVC2 - && bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW) + && bfd_section_flags (segment) & SEC_MEP_VLIW) #endif /* MEP_IVC2_SUPPORTED */ ) { @@ -1540,7 +1539,7 @@ md_estimate_size_before_relax (fragS * fragP, segT segment) } if (MEP_VLIW && ! MEP_VLIW64 - && (bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW)) + && (bfd_section_flags (segment) & SEC_MEP_VLIW)) { /* Use 32 bit branches for vliw32 so the vliw word is not split. */ switch (fragP->fr_cgen.insn->base->num) @@ -1573,7 +1572,7 @@ md_estimate_size_before_relax (fragS * fragP, segT segment) #ifdef MEP_IVC2_SUPPORTED if (mep_cop == EF_MEP_COP_IVC2 - && bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW) + && bfd_section_flags (segment) & SEC_MEP_VLIW) return 0; #endif /* MEP_IVC2_SUPPORTED */ @@ -1588,7 +1587,7 @@ mep_relax_frag (segT segment, fragS *fragP, long stretch) long rv = relax_frag (segment, fragP, stretch); #ifdef MEP_IVC2_SUPPORTED if (mep_cop == EF_MEP_COP_IVC2 - && bfd_get_section_flags (stdoutput, segment) & SEC_MEP_VLIW) + && bfd_section_flags (segment) & SEC_MEP_VLIW) return 0; #endif return rv; @@ -1625,7 +1624,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, int core_mode; #ifdef MEP_IVC2_SUPPORTED - if (bfd_get_section_flags (stdoutput, seg) & SEC_MEP_VLIW + if (bfd_section_flags (seg) & SEC_MEP_VLIW && mep_cop == EF_MEP_COP_IVC2) core_mode = 0; else @@ -1709,7 +1708,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, operand = MEP_OPERAND_PCREL17A2; break; } - /* ...FALLTHROUGH... */ + /* Fall through. */ case MEP_INSN_JMP: addend = target_address_for (fragP); @@ -1724,6 +1723,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, case MEP_INSN_BNEZ: bit = 1; + /* Fall through. */ case MEP_INSN_BEQZ: fragP->fr_opcode[1^e] = bit | (addend & 0xfe); operand = MEP_OPERAND_PCREL8A2; @@ -1731,6 +1731,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, case MEP_INSN_BNEI: bit = 4; + /* Fall through. */ case MEP_INSN_BEQI: if (subtype_mappings[fragP->fr_subtype].growth) { @@ -1789,7 +1790,7 @@ mep_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) switch (fixP->fx_cgen.opinfo) { case BFD_RELOC_MEP_LOW16: - *valP = ((long)(*valP & 0xffff)) << 16 >> 16; + *valP = ((*valP & 0xffff) ^ 0x8000) - 0x8000; break; case BFD_RELOC_MEP_HI16U: *valP >>= 16; @@ -1799,7 +1800,7 @@ mep_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) break; } - /* Now call cgen's md_aply_fix. */ + /* Now call cgen's md_apply_fix. */ gas_cgen_md_apply_fix (fixP, valP, seg); } @@ -1934,7 +1935,7 @@ mep_cgen_record_fixup_exp (fragS *frag, tc_gen_reloc. */ void -mep_frob_file () +mep_frob_file (void) { struct mep_hi_fixup * l; @@ -2039,7 +2040,7 @@ md_number_to_chars (char *buf, valueT val, int n) number_to_chars_littleendian (buf, val, n); } -char * +const char * md_atof (int type, char *litP, int *sizeP) { return ieee_md_atof (type, litP, sizeP, TRUE); @@ -2080,7 +2081,7 @@ mep_fix_adjustable (fixS *fixP) } bfd_vma -mep_elf_section_letter (int letter, char **ptrmsg) +mep_elf_section_letter (int letter, const char **ptrmsg) { if (letter == 'v') return SHF_MEP_VLIW; @@ -2109,7 +2110,7 @@ mep_vtext_section (void) { flagword applicable = bfd_applicable_section_flags (stdoutput); vtext_section = subseg_new (VTEXT_SECTION_NAME, 0); - bfd_set_section_flags (stdoutput, vtext_section, + bfd_set_section_flags (vtext_section, applicable & (SEC_ALLOC | SEC_LOAD | SEC_RELOC | SEC_CODE | SEC_READONLY | SEC_MEP_VLIW)); @@ -2184,7 +2185,7 @@ mep_cleanup (void) { /* Take care of any insns left to be parallelized when the file ends. This is mainly here to handle the case where the file ends with an - insn preceeded by a + or the file ends unexpectedly. */ + insn preceded by a + or the file ends unexpectedly. */ if (mode == VLIW) mep_process_saved_insns (); }