X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fconfig%2Ftc-ppc.c;h=c4c32d1aeab00689d296b4954e3c0431d1517ae3;hb=ba0b21743576bcc16dcc7f0cd8f17b55519e5913;hp=7436fbdd379fa0c09b5504da9088cd5292a929c9;hpb=a7fc733f393cf349a03757bdf1c66c2576b387ca;p=deliverable%2Fbinutils-gdb.git

diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c
index 7436fbdd37..c4c32d1aea 100644
--- a/gas/config/tc-ppc.c
+++ b/gas/config/tc-ppc.c
@@ -182,6 +182,10 @@ const char EXP_CHARS[] = "eE";
 /* Characters which mean that a number is a floating point constant,
    as in 0d1.0.  */
 const char FLT_CHARS[] = "dD";
+
+/* '+' and '-' can be used as postfix predicate predictors for conditional 
+   branches.  So they need to be accepted as symbol characters.  */
+const char ppc_symbol_chars[] = "+-";
 
 /* The target specific pseudo-ops which we support.  */
 
@@ -233,8 +237,6 @@ const pseudo_typeS md_pseudo_table[] =
   { "rdata",	ppc_elf_rdata,	0 },
   { "rodata",	ppc_elf_rdata,	0 },
   { "lcomm",	ppc_elf_lcomm,	0 },
-  { "file",	(void (*) PARAMS ((int))) dwarf2_directive_file, 0 },
-  { "loc",	dwarf2_directive_loc, 0 },
 #endif
 
 #ifdef TE_PE
@@ -1060,36 +1062,40 @@ md_show_usage (stream)
 {
   fprintf (stream, _("\
 PowerPC options:\n\
+-a32			generate ELF32/XCOFF32\n\
+-a64			generate ELF64/XCOFF64\n\
 -u			ignored\n\
 -mpwrx, -mpwr2		generate code for POWER/2 (RIOS2)\n\
 -mpwr			generate code for POWER (RIOS1)\n\
 -m601			generate code for PowerPC 601\n\
 -mppc, -mppc32, -m603, -m604\n\
 			generate code for PowerPC 603/604\n\
--m403, -m405            generate code for PowerPC 403/405\n\
+-m403, -m405		generate code for PowerPC 403/405\n\
 -m7400, -m7410, -m7450, -m7455\n\
-			generate code For PowerPC 7400/7410/7450/7455\n\
+			generate code For PowerPC 7400/7410/7450/7455\n"));
+  fprintf (stream, _("\
 -mppc64, -m620		generate code for PowerPC 620/625/630\n\
 -mppc64bridge		generate code for PowerPC 64, including bridge insns\n\
 -mbooke64		generate code for 64-bit PowerPC BookE\n\
 -mbooke, mbooke32	generate code for 32-bit PowerPC BookE\n\
 -mpower4		generate code for Power4 architecture\n\
--maltivec		generate code for AltiVec\n\
 -mcom			generate code Power/PowerPC common instructions\n\
--many			generate code for any architecture (PWR/PWRX/PPC)\n\
--mregnames		Allow symbolic names for registers\n\
--mno-regnames		Do not allow symbolic names for registers\n"));
+-many			generate code for any architecture (PWR/PWRX/PPC)\n"));
   fprintf (stream, _("\
+-maltivec		generate code for AltiVec\n\
 -me500, -me500x2	generate code for Motorola e500 core complex\n\
--mspe			generate code for Motorola SPE instructions\n"));
+-mspe			generate code for Motorola SPE instructions\n\
+-mregnames		Allow symbolic names for registers\n\
+-mno-regnames		Do not allow symbolic names for registers\n"));
 #ifdef OBJ_ELF
   fprintf (stream, _("\
 -mrelocatable		support for GCC's -mrelocatble option\n\
 -mrelocatable-lib	support for GCC's -mrelocatble-lib option\n\
 -memb			set PPC_EMB bit in ELF flags\n\
--mlittle, -mlittle-endian\n\
+-mlittle, -mlittle-endian, -l, -le\n\
 			generate code for a little endian machine\n\
--mbig, -mbig-endian	generate code for a big endian machine\n\
+-mbig, -mbig-endian, -b, -be\n\
+			generate code for a big endian machine\n\
 -msolaris		generate code for Solaris\n\
 -mno-solaris		do not generate code for Solaris\n\
 -V			print assembler version number\n\
@@ -2441,7 +2447,7 @@ md_assemble (str)
 	    }
 
 	  if (ppc_obj64
-	      && (operand->flags & PPC_OPERAND_DS) != 0)
+	      && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0)
 	    {
 	      switch (reloc)
 		{
@@ -2746,7 +2752,7 @@ ppc_section_letter (letter, ptr_msg)
     return SHF_EXCLUDE;
 
   *ptr_msg = _("Bad .section directive: want a,e,w,x,M,S,G,T in string");
-  return 0;
+  return -1;
 }
 
 int
@@ -5708,13 +5714,18 @@ md_apply_fix3 (fixP, valP, seg)
 	    abort ();
 	  {
 	    unsigned char *where = fixP->fx_frag->fr_literal + fixP->fx_where;
-	    unsigned long val;
+	    long val, mask;
 
 	    if (target_big_endian)
-	      val = bfd_getb16 (where);
+	      val = bfd_getb32 (where - 2);
 	    else
-	      val = bfd_getl16 (where);
-	    val |= (value & 0xfffc);
+	      val = bfd_getl32 (where);
+	    mask = 0xfffc;
+	    /* lq insns reserve the four lsbs.  */
+	    if ((ppc_cpu & PPC_OPCODE_POWER4) != 0
+		&& (val & (0x3f << 26)) == (56 << 26))
+	      mask = 0xfff0;
+	    val |= value & mask;
 	    if (target_big_endian)
 	      bfd_putb16 ((bfd_vma) val, where);
 	    else
@@ -5722,6 +5733,12 @@ md_apply_fix3 (fixP, valP, seg)
 	  }
 	  break;
 
+	case BFD_RELOC_PPC_B16_BRTAKEN:
+	case BFD_RELOC_PPC_B16_BRNTAKEN:
+	case BFD_RELOC_PPC_BA16_BRTAKEN:
+	case BFD_RELOC_PPC_BA16_BRNTAKEN:
+	  break;
+
 	case BFD_RELOC_PPC_TLS:
 	case BFD_RELOC_PPC_DTPMOD:
 	case BFD_RELOC_PPC_TPREL16: