X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fdoc%2Fc-arm.texi;h=7e4863ea992387ace7a785f759e93379430cd336;hb=42e58860e260edf7d92734c01b95fccf9ddb2431;hp=983434f166cfc7084a5a8449a6be9520ec1a4a40;hpb=34bca50861dd6a0d59b8f8b215865e3a52895191;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi index 983434f166..7e4863ea99 100644 --- a/gas/doc/c-arm.texi +++ b/gas/doc/c-arm.texi @@ -1,5 +1,4 @@ -@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, -@c 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. +@c Copyright (C) 1996-2016 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @@ -120,13 +119,29 @@ recognized: @code{cortex-a8}, @code{cortex-a9}, @code{cortex-a15}, +@code{cortex-a17}, +@code{cortex-a32}, +@code{cortex-a35}, +@code{cortex-a53}, +@code{cortex-a57}, +@code{cortex-a72}, @code{cortex-r4}, @code{cortex-r4f}, +@code{cortex-r5}, +@code{cortex-r7}, +@code{cortex-r8}, +@code{cortex-m7}, @code{cortex-m4}, @code{cortex-m3}, @code{cortex-m1}, @code{cortex-m0}, @code{cortex-m0plus}, +@code{exynos-m1}, +@code{marvell-pj4}, +@code{marvell-whitney}, +@code{qdf24xx}, +@code{xgene1}, +@code{xgene2}, @code{ep9312} (ARM920 with Cirrus Maverick coprocessor), @code{i80200} (Intel XScale processor) @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) @@ -154,18 +169,24 @@ been added, again in ascending alphabetical order. For example, The following extensions are currently supported: +@code{crc} @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}), @code{fp} (Floating Point Extensions for v8-A architecture), @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures), @code{iwmmxt}, @code{iwmmxt2}, +@code{xscale}, @code{maverick}, -@code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures), +@code{mp} (Multiprocessing Extensions for v7-A and v7-R +architectures), @code{os} (Operating System for v6M architecture), @code{sec} (Security Extensions for v6K and v7-A architectures), @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}), @code{virt} (Virtualization Extensions for v7-A architecture, implies @code{idiv}), +@code{pan} (Priviliged Access Never Extensions for v8-A architecture), +@code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies +@code{simd}) and @code{xscale}. @@ -194,16 +215,20 @@ names are recognized: @code{armv6j}, @code{armv6k}, @code{armv6z}, -@code{armv6zk}, +@code{armv6kz}, @code{armv6-m}, @code{armv6s-m}, @code{armv7}, @code{armv7-a}, +@code{armv7ve}, @code{armv7-r}, @code{armv7-m}, @code{armv7e-m}, @code{armv8-a}, +@code{armv8.1-a}, +@code{armv8.2-a}, @code{iwmmxt} +@code{iwmmxt2} and @code{xscale}. If both @code{-mcpu} and @@ -245,6 +270,8 @@ The following format options are recognized: @code{vfpv4}, @code{vfpv4-d16}, @code{fpv4-sp-d16}, +@code{fpv5-sp-d16}, +@code{fpv5-d16}, @code{fp-armv8}, @code{arm1020t}, @code{arm1020e}, @@ -253,8 +280,10 @@ The following format options are recognized: @code{neon}, @code{neon-vfpv4}, @code{neon-fp-armv8}, +@code{crypto-neon-fp-armv8}, +@code{neon-fp-armv8.1} and -@code{crypto-neon-fp-armv8}. +@code{crypto-neon-fp-armv8.1}. In addition to determining which instructions are assembled, this option also affects the way in which the @code{.double} assembler directive behaves @@ -345,6 +374,12 @@ and This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. +Note: If a program is being built for a system with big-endian data +and little-endian instructions then it should be assembled with the +@option{-EB} option, (all of it, code and data) and then linked with +the @option{--be8} option. This will reverse the endianness of the +instructions back to little-endian, but leave the data as big-endian. + @cindex @code{-EL} command line option, ARM @item -EL This option specifies that the output generated by the assembler should @@ -367,6 +402,16 @@ the linker option of the same name. Enable or disable warnings about using deprecated options or features. The default is to warn. +@cindex @code{-mccs} command line option, ARM +@item -mccs +Turns on CodeComposer Studio assembly syntax compatibility mode. + +@cindex @code{-mwarn-syms} command line option, ARM +@item -mwarn-syms +@itemx -mno-warn-syms +Enable or disable warnings about symbols that match the names of ARM +instructions. The default is to warn. + @end table @@ -388,7 +433,7 @@ ARM and THUMB instructions had their own, separate syntaxes. The new, @code{unified} syntax, which can be selected via the @code{.syntax} directive, and has the following main features: -@table @bullet +@itemize @bullet @item Immediate operands do not require a @code{#} prefix. @@ -413,7 +458,7 @@ The @code{.N} and @code{.W} suffixes are recognized and honored. @item All instructions set the flags if and only if they have an @code{s} affix. -@end table +@end itemize @node ARM-Chars @subsection Special Characters @@ -449,28 +494,6 @@ Either @samp{#} or @samp{$} can be used to indicate immediate operands. @cindex register names, ARM *TODO* Explain about ARM register naming, and the predefined names. -@node ARM-Neon-Alignment -@subsection NEON Alignment Specifiers - -@cindex alignment for NEON instructions -Some NEON load/store instructions allow an optional address -alignment qualifier. -The ARM documentation specifies that this is indicated by -@samp{@@ @var{align}}. However GAS already interprets -the @samp{@@} character as a "line comment" start, -so @samp{: @var{align}} is used instead. For example: - -@smallexample - vld1.8 @{q0@}, [r0, :128] -@end smallexample - -@node ARM Floating Point -@section Floating Point - -@cindex floating point, ARM (@sc{ieee}) -@cindex ARM floating point (@sc{ieee}) -The ARM family uses @sc{ieee} floating-point numbers. - @node ARM-Relocations @subsection ARM relocation generation @@ -517,6 +540,44 @@ respectively. For example to load the 32-bit address of foo into r0: MOVT r0, #:upper16:foo @end smallexample +Relocations @samp{R_ARM_THM_ALU_ABS_G0_NC}, @samp{R_ARM_THM_ALU_ABS_G1_NC}, +@samp{R_ARM_THM_ALU_ABS_G2_NC} and @samp{R_ARM_THM_ALU_ABS_G3_NC} can be +generated by prefixing the value with @samp{#:lower0_7:#}, +@samp{#:lower8_15:#}, @samp{#:upper0_7:#} and @samp{#:upper8_15:#} +respectively. For example to load the 32-bit address of foo into r0: + +@smallexample + MOVS r0, #:upper8_15:#foo + LSLS r0, r0, #8 + ADDS r0, #:upper0_7:#foo + LSLS r0, r0, #8 + ADDS r0, #:lower8_15:#foo + LSLS r0, r0, #8 + ADDS r0, #:lower0_7:#foo +@end smallexample + +@node ARM-Neon-Alignment +@subsection NEON Alignment Specifiers + +@cindex alignment for NEON instructions +Some NEON load/store instructions allow an optional address +alignment qualifier. +The ARM documentation specifies that this is indicated by +@samp{@@ @var{align}}. However GAS already interprets +the @samp{@@} character as a "line comment" start, +so @samp{: @var{align}} is used instead. For example: + +@smallexample + vld1.8 @{q0@}, [r0, :128] +@end smallexample + +@node ARM Floating Point +@section Floating Point + +@cindex floating point, ARM (@sc{ieee}) +@cindex ARM floating point (@sc{ieee}) +The ARM family uses @sc{ieee} floating-point numbers. + @node ARM Directives @section ARM Machine Directives @@ -562,13 +623,6 @@ incrementally to the architecture being compiled for. @item .arm This performs the same action as @var{.code 32}. -@anchor{arm_pad} -@cindex @code{.pad} directive, ARM -@item .pad #@var{count} -Generate unwinder annotations for a stack adjustment of @var{count} bytes. -A positive value indicates the function prologue allocated stack space by -decrementing the stack pointer. - @c BBBBBBBBBBBBBBBBBBBBBBBBBB @cindex @code{.bss} directive, ARM @@ -768,6 +822,7 @@ This directive writes 12-byte packed floating-point values to the output section. These are not compatible with current ARM processors or ABIs. +@anchor{arm_pad} @cindex @code{.pad} directive, ARM @item .pad #@var{count} Generate unwinder annotations for a stack adjustment of @var{count} bytes. @@ -1185,3 +1240,4 @@ code that calls functions which may throw exceptions. If you need to know more about the object-file format used to represent unwind information, you may consult the @cite{Exception Handling ABI for the ARM Architecture} available from @uref{http://infocenter.arm.com}. +