X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fdoc%2Fc-arm.texi;h=91803605775418bcc795e163f42b0beaec880967;hb=efb763a5ea351f9d865cbe491909f03472ebf2d6;hp=a316c267e22c603ed529451a488d9b3d1baf5c56;hpb=54691107334ee13f3237e0f754d458c52d5b145e;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi index a316c267e2..9180360577 100644 --- a/gas/doc/c-arm.texi +++ b/gas/doc/c-arm.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1996-2018 Free Software Foundation, Inc. +@c Copyright (C) 1996-2020 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @@ -129,12 +129,16 @@ recognized: @code{cortex-a73}, @code{cortex-a75}, @code{cortex-a76}, +@code{cortex-a76ae}, +@code{cortex-a77}, +@code{ares}, @code{cortex-r4}, @code{cortex-r4f}, @code{cortex-r5}, @code{cortex-r7}, @code{cortex-r8}, @code{cortex-r52}, +@code{cortex-m35p}, @code{cortex-m33}, @code{cortex-m23}, @code{cortex-m7}, @@ -146,11 +150,12 @@ recognized: @code{exynos-m1}, @code{marvell-pj4}, @code{marvell-whitney}, +@code{neoverse-n1}, @code{xgene1}, @code{xgene2}, @code{ep9312} (ARM920 with Cirrus Maverick coprocessor), @code{i80200} (Intel XScale processor) -@code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) +@code{iwmmxt} (Intel XScale processor with Wireless MMX technology coprocessor) and @code{xscale}. The special name @code{all} may be used to allow the @@ -175,6 +180,8 @@ been added, again in ascending alphabetical order. For example, The following extensions are currently supported: +@code{bf16} (BFloat16 extensions for v8.6-A architecture), +@code{i8mm} (Int8 Matrix Multiply extensions for v8.6-A architecture), @code{crc} @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}), @code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}), @@ -189,6 +196,10 @@ The following extensions are currently supported: @code{mp} (Multiprocessing Extensions for v7-A and v7-R architectures), @code{os} (Operating System for v6M architecture), +@code{predres} (Execution and Data Prediction Restriction Instruction for +v8-A architectures, added by default from v8.5-A), +@code{sb} (Speculation Barrier Instruction for v8-A architectures, added by +default from v8.5-A), @code{sec} (Security Extensions for v6K and v7-A architectures), @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}), @code{virt} (Virtualization Extensions for v7-A architecture, implies @@ -241,7 +252,12 @@ names are recognized: @code{armv8.3-a}, @code{armv8-r}, @code{armv8.4-a}, -@code{iwmmxt} +@code{armv8.5-a}, +@code{armv8-m.base}, +@code{armv8-m.main}, +@code{armv8.1-m.main}, +@code{armv8.6-a}, +@code{iwmmxt}, @code{iwmmxt2} and @code{xscale}. @@ -249,8 +265,190 @@ If both @code{-mcpu} and @code{-march} are specified, the assembler will use the setting for @code{-mcpu}. -The architecture option can be extended with the same instruction set -extension options as the @code{-mcpu} option. +The architecture option can be extended with a set extension options. These +extensions are context sensitive, i.e. the same extension may mean different +things when used with different architectures. When used together with a +@code{-mfpu} option, the union of both feature enablement is taken. +See their availability and meaning below: + +For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}: + +@code{+fp}: Enables VFPv2 instructions. +@code{+nofp}: Disables all FPU instrunctions. + +For @code{armv7}: + +@code{+fp}: Enables VFPv3 instructions with 16 double-word registers. +@code{+nofp}: Disables all FPU instructions. + +For @code{armv7-a}: + +@code{+fp}: Enables VFPv3 instructions with 16 double-word registers. +@code{+vfpv3-d16}: Alias for @code{+fp}. +@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers. +@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point +conversion instructions and 16 double-word registers. +@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion +instructions and 32 double-word registers. +@code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers. +@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers. +@code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word +registers. +@code{+neon}: Alias for @code{+simd}. +@code{+neon-vfpv3}: Alias for @code{+simd}. +@code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and +NEONv1 instructions with 32 double-word registers. +@code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 +double-word registers. +@code{+mp}: Enables Multiprocessing Extensions. +@code{+sec}: Enables Security Extensions. +@code{+nofp}: Disables all FPU and NEON instructions. +@code{+nosimd}: Disables all NEON instructions. + +For @code{armv7ve}: + +@code{+fp}: Enables VFPv4 instructions with 16 double-word registers. +@code{+vfpv4-d16}: Alias for @code{+fp}. +@code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers. +@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers. +@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point +conversion instructions and 16 double-word registers. +@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion +instructions and 32 double-word registers. +@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers. +@code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 +double-word registers. +@code{+neon-vfpv4}: Alias for @code{+simd}. +@code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word +registers. +@code{+neon-vfpv3}: Alias for @code{+neon}. +@code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and +NEONv1 instructions with 32 double-word registers. +double-word registers. +@code{+nofp}: Disables all FPU and NEON instructions. +@code{+nosimd}: Disables all NEON instructions. + +For @code{armv7-r}: + +@code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16 +double-word registers. +@code{+vfpv3xd}: Alias for @code{+fp.sp}. +@code{+fp}: Enables VFPv3 instructions with 16 double-word registers. +@code{+vfpv3-d16}: Alias for @code{+fp}. +@code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half +floating-point conversion instructions with 16 double-word registers. +@code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point +conversion instructions with 16 double-word registers. +@code{+idiv}: Enables integer division instructions in ARM mode. +@code{+nofp}: Disables all FPU instructions. + +For @code{armv7e-m}: + +@code{+fp}: Enables single-precision only VFPv4 instructions with 16 +double-word registers. +@code{+vfpvf4-sp-d16}: Alias for @code{+fp}. +@code{+fpv5}: Enables single-precision only VFPv5 instructions with 16 +double-word registers. +@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers. +@code{+fpv5-d16"}: Alias for @code{+fp.dp}. +@code{+nofp}: Disables all FPU instructions. + +For @code{armv8-m.main}: + +@code{+dsp}: Enables DSP Extension. +@code{+fp}: Enables single-precision only VFPv5 instructions with 16 +double-word registers. +@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers. +@code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0), +@code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1), +@code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2), +@code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3), +@code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4), +@code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5), +@code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6), +@code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7), +@code{+nofp}: Disables all FPU instructions. +@code{+nodsp}: Disables DSP Extension. + +For @code{armv8.1-m.main}: + +@code{+dsp}: Enables DSP Extension. +@code{+fp}: Enables single and half precision scalar Floating Point Extensions +for Armv8.1-M Mainline with 16 double-word registers. +@code{+fp.dp}: Enables double precision scalar Floating Point Extensions for +Armv8.1-M Mainline, implies @code{+fp}. +@code{+mve}: Enables integer only M-profile Vector Extension for +Armv8.1-M Mainline, implies @code{+dsp}. +@code{+mve.fp}: Enables Floating Point M-profile Vector Extension for +Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}. +@code{+nofp}: Disables all FPU instructions. +@code{+nodsp}: Disables DSP Extension. +@code{+nomve}: Disables all M-profile Vector Extensions. + +For @code{armv8-a}: + +@code{+crc}: Enables CRC32 Extension. +@code{+simd}: Enables VFP and NEON for Armv8-A. +@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies +@code{+simd}. +@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. +@code{+predres}: Enables Execution and Data Prediction Restriction Instruction +for Armv8-A. +@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. +@code{+nocrypto}: Disables Cryptography Extensions. + +For @code{armv8.1-a}: + +@code{+simd}: Enables VFP and NEON for Armv8.1-A. +@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies +@code{+simd}. +@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. +@code{+predres}: Enables Execution and Data Prediction Restriction Instruction +for Armv8-A. +@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. +@code{+nocrypto}: Disables Cryptography Extensions. + +For @code{armv8.2-a} and @code{armv8.3-a}: + +@code{+simd}: Enables VFP and NEON for Armv8.1-A. +@code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}. +@code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions +for Armv8.2-A, implies @code{+fp16}. +@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies +@code{+simd}. +@code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies +@code{+simd}. +@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. +@code{+predres}: Enables Execution and Data Prediction Restriction Instruction +for Armv8-A. +@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. +@code{+nocrypto}: Disables Cryptography Extensions. + +For @code{armv8.4-a}: + +@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for +Armv8.2-A. +@code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication +Variant Extensions for Armv8.2-A, implies @code{+simd}. +@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies +@code{+simd}. +@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. +@code{+predres}: Enables Execution and Data Prediction Restriction Instruction +for Armv8-A. +@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. +@code{+nocryptp}: Disables Cryptography Extensions. + +For @code{armv8.5-a}: + +@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for +Armv8.2-A. +@code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication +Variant Extensions for Armv8.2-A, implies @code{+simd}. +@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies +@code{+simd}. +@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. +@code{+nocryptp}: Disables Cryptography Extensions. + @cindex @code{-mfpu=} command-line option, ARM @item -mfpu=@var{floating-point-format} @@ -309,6 +507,22 @@ The default is dependent on the processor selected. For Architecture 5 or later, the default is to assemble for VFP instructions; for earlier architectures the default is to assemble for FPA instructions. +@cindex @code{-mfp16-format=} command-line option +@item -mfp16-format=@var{format} +This option specifies the half-precision floating point format to use +when assembling floating point numbers emitted by the @code{.float16} +directive. +The following format options are recognized: +@code{ieee}, +@code{alternative}. +If @code{ieee} is specified then the IEEE 754-2008 half-precision floating +point format is used, if @code{alternative} is specified then the Arm +alternative half-precision format is used. If this option is set on the +command line then the format is fixed and cannot be changed with +the @code{float16_format} directive. If this value is not set then +the IEEE 754-2008 format is used until the format is explicitly set with +the @code{float16_format} directive. + @cindex @code{-mthumb} command-line option, ARM @item -mthumb This option specifies that the assembler should start assembling Thumb @@ -712,7 +926,7 @@ The @var{tag} is either an attribute number, or one of the following: @code{Tag_CPU_raw_name}, @code{Tag_CPU_name}, @code{Tag_CPU_arch}, @code{Tag_CPU_arch_profile}, @code{Tag_ARM_ISA_use}, @code{Tag_THUMB_ISA_use}, @code{Tag_FP_arch}, @code{Tag_WMMX_arch}, -@code{Tag_Advanced_SIMD_arch}, @code{Tag_PCS_config}, +@code{Tag_Advanced_SIMD_arch}, @code{Tag_MVE_arch}, @code{Tag_PCS_config}, @code{Tag_ABI_PCS_R9_use}, @code{Tag_ABI_PCS_RW_data}, @code{Tag_ABI_PCS_RO_data}, @code{Tag_ABI_PCS_GOT_use}, @code{Tag_ABI_PCS_wchar_t}, @code{Tag_ABI_FP_rounding}, @@ -750,6 +964,23 @@ or ABIs. @c FFFFFFFFFFFFFFFFFFFFFFFFFF +@cindex @code{.float16} directive, ARM +@item .float16 @var{value [,...,value_n]} +Place the half precision floating point representation of one or more +floating-point values into the current section. The exact format of the +encoding is specified by @code{.float16_format}. If the format has not +been explicitly set yet (either via the @code{.float16_format} directive or +the command line option) then the IEEE 754-2008 format is used. + +@cindex @code{.float16_format} directive, ARM +@item .float16_format @var{format} +Set the format to use when encoding float16 values emitted by +the @code{.float16} directive. +Once the format has been set it cannot be changed. +@code{format} should be one of the following: @code{ieee} (encode in +the IEEE 754-2008 half precision format) or @code{alternative} (encode in +the Arm alternative half precision format). + @anchor{arm_fnend} @cindex @code{.fnend} directive, ARM @item .fnend