X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fdoc%2Fc-i386.texi;h=4a9f6615e4d416977db2d7ef51a3c960d956b602;hb=69dd98654ad9b6a1fb1ea1cdfa3f9fa1f57fce8c;hp=23c869e6f53e4b8252a147790cd1cd5c5aca3eec;hpb=ef05d49568cbf26e5a16185901444e1db929c817;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 23c869e6f5..4a9f6615e4 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -1,5 +1,5 @@ @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000, -@c 2001, 2003, 2004 +@c 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009 @c Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @@ -14,7 +14,7 @@ @end ifclear @cindex i386 support -@cindex i80306 support +@cindex i80386 support @cindex x86-64 support The i386 version @code{@value{AS}} supports both the original Intel 386 @@ -23,6 +23,7 @@ extending the Intel architecture to 64-bits. @menu * i386-Options:: Options +* i386-Directives:: X86 specific directives * i386-Syntax:: AT&T Syntax versus Intel Syntax * i386-Mnemonics:: Instruction Naming * i386-Regs:: Register Naming @@ -31,6 +32,7 @@ extending the Intel architecture to 64-bits. * i386-Jumps:: Handling of Jump Instructions * i386-Float:: Floating Point * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations +* i386-LWP:: AMD's Lightweight Profiling Instructions * i386-16bit:: Writing 16-bit Code * i386-Arch:: Specifying an x86 CPU architecture * i386-Bugs:: AT&T Syntax bugs @@ -78,9 +80,11 @@ affect using @samp{#} for starting a comment. @cindex @samp{-march=} option, i386 @cindex @samp{-march=} option, x86-64 -@item -march=@var{CPU} -This option specifies an instruction set architecture for generating -instructions. The following architectures are recognized: +@item -march=@var{CPU}[+@var{EXTENSION}@dots{}] +This option specifies the target processor. The assembler will +issue an error message if an attempt is made to assemble an instruction +which will not execute on the target processor. The following +processor names are recognized: @code{i8086}, @code{i186}, @code{i286}, @@ -97,16 +101,63 @@ instructions. The following architectures are recognized: @code{nocona}, @code{core}, @code{core2}, +@code{corei7}, +@code{l1om}, @code{k6}, @code{k6_2}, @code{athlon}, -@code{sledgehammer}, @code{opteron}, @code{k8}, +@code{amdfam10}, +@code{amdfam15}, @code{generic32} and @code{generic64}. -This option only affects instructions generated by the assembler. The +In addition to the basic instruction set, the assembler can be told to +accept various extension mnemonics. For example, +@code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and +@var{vmx}. The following extensions are currently supported: +@code{8087}, +@code{287}, +@code{387}, +@code{no87}, +@code{mmx}, +@code{nommx}, +@code{sse}, +@code{sse2}, +@code{sse3}, +@code{ssse3}, +@code{sse4.1}, +@code{sse4.2}, +@code{sse4}, +@code{nosse}, +@code{avx}, +@code{noavx}, +@code{vmx}, +@code{smx}, +@code{xsave}, +@code{aes}, +@code{pclmul}, +@code{fma}, +@code{movbe}, +@code{ept}, +@code{clflush}, +@code{lwp}, +@code{fma4}, +@code{xop}, +@code{syscall}, +@code{rdtscp}, +@code{3dnow}, +@code{3dnowa}, +@code{sse4a}, +@code{sse5}, +@code{svme}, +@code{abm} and +@code{padlock}. +Note that rather than extending a basic instruction set, the extension +mnemonics starting with @code{no} revoke the respective functionality. + +When the @code{.arch} directive is used with @option{-march}, the @code{.arch} directive will take precedent. @cindex @samp{-mtune=} option, i386 @@ -117,7 +168,72 @@ conjunction with the @option{-march} option, only instructions of the processor specified by the @option{-march} option will be generated. -Valid @var{CPU} values are identical to @option{-march=@var{CPU}}. +Valid @var{CPU} values are identical to the processor list of +@option{-march=@var{CPU}}. + +@cindex @samp{-msse2avx} option, i386 +@cindex @samp{-msse2avx} option, x86-64 +@item -msse2avx +This option specifies that the assembler should encode SSE instructions +with VEX prefix. + +@cindex @samp{-msse-check=} option, i386 +@cindex @samp{-msse-check=} option, x86-64 +@item -msse-check=@var{none} +@item -msse-check=@var{warning} +@item -msse-check=@var{error} +These options control if the assembler should check SSE intructions. +@option{-msse-check=@var{none}} will make the assembler not to check SSE +instructions, which is the default. @option{-msse-check=@var{warning}} +will make the assembler issue a warning for any SSE intruction. +@option{-msse-check=@var{error}} will make the assembler issue an error +for any SSE intruction. + +@cindex @samp{-mmnemonic=} option, i386 +@cindex @samp{-mmnemonic=} option, x86-64 +@item -mmnemonic=@var{att} +@item -mmnemonic=@var{intel} +This option specifies instruction mnemonic for matching instructions. +The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will +take precedent. + +@cindex @samp{-msyntax=} option, i386 +@cindex @samp{-msyntax=} option, x86-64 +@item -msyntax=@var{att} +@item -msyntax=@var{intel} +This option specifies instruction syntax when processing instructions. +The @code{.att_syntax} and @code{.intel_syntax} directives will +take precedent. + +@cindex @samp{-mnaked-reg} option, i386 +@cindex @samp{-mnaked-reg} option, x86-64 +@item -mnaked-reg +This opetion specifies that registers don't require a @samp{%} prefix. +The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. + +@end table + +@node i386-Directives +@section x86 specific Directives + +@cindex machine directives, x86 +@cindex x86 machine directives +@table @code + +@cindex @code{lcomm} directive, COFF +@item .lcomm @var{symbol} , @var{length}[, @var{alignment}] +Reserve @var{length} (an absolute expression) bytes for a local common +denoted by @var{symbol}. The section and value of @var{symbol} are +those of the new local common. The addresses are allocated in the bss +section, so that at run-time the bytes start off zeroed. Since +@var{symbol} is not declared global, it is normally not visible to +@code{@value{LD}}. The optional third parameter, @var{alignment}, +specifies the desired alignment of the symbol in the bss section. + +This directive is only available for COFF based x86 targets. + +@c FIXME: Document other x86 specific directives ? Eg: .code16gcc, +@c .largecomm @end table @@ -178,9 +294,9 @@ operands are prefixed by @samp{*}; they are undelimited in Intel syntax. AT&T and Intel syntax use the opposite order for source and destination operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The @samp{source, dest} convention is maintained for compatibility with -previous Unix assemblers. Note that instructions with more than one -source operand, such as the @samp{enter} instruction, do @emph{not} have -reversed order. @ref{i386-Bugs}. +previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and +instructions with 2 immediate operands, such as the @samp{enter} +instruction, do @emph{not} have reversed order. @ref{i386-Bugs}. @cindex mnemonic suffixes, i386 @cindex sizes operands, i386 @@ -198,6 +314,9 @@ this by prefixing memory operands (@emph{not} the instruction mnemonics) with Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T syntax. +In 64-bit code, @samp{movabs} can be used to encode the @samp{mov} +instruction with the 64-bit displacement or immediate operand. + @cindex return instructions, i386 @cindex i386 jump, call, return @cindex return instructions, x86-64 @@ -256,6 +375,13 @@ thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), @samp{wq} (from word to quadruple word), and @samp{lq} (from long to quadruple word). +@cindex encoding options, i386 +@cindex encoding options, x86-64 + +Different encoding options can be specified via optional mnemonic +suffix. @samp{.s} suffix swaps 2 register operands in encoding when +moving from one register to another. + @cindex conversion instructions, i386 @cindex i386 conversion instructions @cindex conversion instructions, x86-64 @@ -297,6 +423,21 @@ Far call/jump instructions are @samp{lcall} and @samp{ljmp} in AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel convention. +@section AT&T Mnemonic versus Intel Mnemonic + +@cindex i386 mnemonic compatibility +@cindex mnemonic compatibility, i386 + +@code{@value{AS}} supports assembly using Intel mnemonic. +@code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and +@code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T +syntax for compatibility with the output of @code{@value{GCC}}. +Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp}, +@samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp}, +@samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386 +assembler with different mnemonics from those in Intel IA32 specification. +@code{@value{GCC}} generates those instructions with AT&T mnemonic. + @node i386-Regs @section Register Naming @@ -663,6 +804,25 @@ as the floating point stack. See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed from the Intel syntax. +@node i386-LWP +@section AMD's Lightweight Profiling Instructions + +@cindex LWP, i386 +@cindex LWP, x86-64 + +@code{@value{AS}} supports AMD's Lightweight Profiling (LWP) +instruction set, available on AMD's Family 15h (Orochi) processors. + +LWP enables applications to collect and manage performance data, and +react to performance events. The collection of performance data +requires no context switches. LWP runs in the context of a thread and +so several counters can be used independently across multiple threads. +LWP can be used in both 64-bit and legacy 32-bit modes. + +For detailed information on the LWP instruction set, see the +@cite{AMD Lightweight Profiling Specification} available at +@uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}. + @node i386-16bit @section Writing 16-bit Code @@ -679,8 +839,9 @@ or 64-bit x86-64 code depending on the default configuration, it also supports writing code to run in real mode or in 16-bit protected mode code segments. To do this, put a @samp{.code16} or @samp{.code16gcc} directive before the assembly language instructions to -be run in 16-bit mode. You can switch @code{@value{AS}} back to writing -normal 32-bit code with the @samp{.code32} directive. +be run in 16-bit mode. You can switch @code{@value{AS}} to writing +32-bit code with the @samp{.code32} directive or 64-bit code with the +@samp{.code64} directive. @samp{.code16gcc} provides experimental support for generating 16-bit code from gcc, and differs from @samp{.code16} in that @samp{call}, @@ -753,10 +914,19 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} -@item @samp{k6} @tab @samp{athlon} @tab @samp{sledgehammer} @tab @samp{k8} +@item @samp{corei7} @tab @samp{l1om} +@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} +@item @samp{amdfam10} @tab @samp{amdfam15} +@item @samp{generic32} @tab @samp{generic64} @item @samp{.mmx} @tab @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} -@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.padlock} @tab @samp{.pacifica} -@item @samp{.svme} +@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} +@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave} +@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.movbe} +@item @samp{.ept} @tab @samp{.clflush} +@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} +@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} +@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} +@item @samp{.padlock} @end multitable Apart from the warning, there are only two other effects on