X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fdoc%2Fc-i386.texi;h=9f4d742623af5264f8ef53c89f6ae534a679dd22;hb=a0a1771e895e6606a2a795c407e20aed73f69bd9;hp=81039c4dbe72a0295670b24d2858feb5e0e6cd9d;hpb=01f0fe5e0450edf168c1f612feb93cf588e4e7ea;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 81039c4dbe..ba20067438 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -1,8 +1,8 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000, -@c 2001, 2003, 2004 -@c Free Software Foundation, Inc. +@c Copyright (C) 1991-2019 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. +@c man end + @ifset GENERIC @page @node i386-Dependent @@ -14,7 +14,7 @@ @end ifclear @cindex i386 support -@cindex i80306 support +@cindex i80386 support @cindex x86-64 support The i386 version @code{@value{AS}} supports both the original Intel 386 @@ -23,7 +23,8 @@ extending the Intel architecture to 64-bits. @menu * i386-Options:: Options -* i386-Syntax:: AT&T Syntax versus Intel Syntax +* i386-Directives:: X86 specific directives +* i386-Syntax:: Syntactical considerations * i386-Mnemonics:: Instruction Naming * i386-Regs:: Register Naming * i386-Prefixes:: Instruction Prefixes @@ -31,6 +32,9 @@ extending the Intel architecture to 64-bits. * i386-Jumps:: Handling of Jump Instructions * i386-Float:: Floating Point * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations +* i386-LWP:: AMD's Lightweight Profiling Instructions +* i386-BMI:: Bit Manipulation Instruction +* i386-TBM:: AMD's Trailing Bit Manipulation Instructions * i386-16bit:: Writing 16-bit Code * i386-Arch:: Specifying an x86 CPU architecture * i386-Bugs:: AT&T Syntax bugs @@ -43,20 +47,24 @@ extending the Intel architecture to 64-bits. @cindex options for i386 @cindex options for x86-64 @cindex i386 options -@cindex x86-64 options +@cindex x86-64 options The i386 version of @code{@value{AS}} has a few machine dependent options: -@table @code +@c man begin OPTIONS +@table @gcctabopt @cindex @samp{--32} option, i386 @cindex @samp{--32} option, x86-64 +@cindex @samp{--x32} option, i386 +@cindex @samp{--x32} option, x86-64 @cindex @samp{--64} option, i386 @cindex @samp{--64} option, x86-64 -@item --32 | --64 -Select the word size, either 32 bits or 64 bits. Selecting 32-bit -implies Intel i386 architecture, while 64-bit implies AMD x86-64 -architecture. +@item --32 | --x32 | --64 +Select the word size, either 32 bits or 64 bits. @samp{--32} +implies Intel i386 architecture, while @samp{--x32} and @samp{--64} +imply AMD x86-64 architecture with 32-bit or 64-bit word-size +respectively. These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit @@ -66,7 +74,8 @@ usage and use x86-64 as target platform). @item -n By default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such -as leal 0(%esi,1),%esi. This switch disables the optimization. +as leal 0(%esi,1),%esi. This switch disables the optimization if a single +byte nop (0x90) is explicitly specified as the fill byte for alignment. @cindex @samp{--divide} option, i386 @item --divide @@ -76,10 +85,446 @@ character, which means that it cannot be used in expressions. The not disable @samp{/} at the beginning of a line starting a comment, or affect using @samp{#} for starting a comment. +@cindex @samp{-march=} option, i386 +@cindex @samp{-march=} option, x86-64 +@item -march=@var{CPU}[+@var{EXTENSION}@dots{}] +This option specifies the target processor. The assembler will +issue an error message if an attempt is made to assemble an instruction +which will not execute on the target processor. The following +processor names are recognized: +@code{i8086}, +@code{i186}, +@code{i286}, +@code{i386}, +@code{i486}, +@code{i586}, +@code{i686}, +@code{pentium}, +@code{pentiumpro}, +@code{pentiumii}, +@code{pentiumiii}, +@code{pentium4}, +@code{prescott}, +@code{nocona}, +@code{core}, +@code{core2}, +@code{corei7}, +@code{l1om}, +@code{k1om}, +@code{iamcu}, +@code{k6}, +@code{k6_2}, +@code{athlon}, +@code{opteron}, +@code{k8}, +@code{amdfam10}, +@code{bdver1}, +@code{bdver2}, +@code{bdver3}, +@code{bdver4}, +@code{znver1}, +@code{znver2}, +@code{btver1}, +@code{btver2}, +@code{generic32} and +@code{generic64}. + +In addition to the basic instruction set, the assembler can be told to +accept various extension mnemonics. For example, +@code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and +@var{vmx}. The following extensions are currently supported: +@code{8087}, +@code{287}, +@code{387}, +@code{687}, +@code{no87}, +@code{no287}, +@code{no387}, +@code{no687}, +@code{cmov}, +@code{nocmov}, +@code{fxsr}, +@code{nofxsr}, +@code{mmx}, +@code{nommx}, +@code{sse}, +@code{sse2}, +@code{sse3}, +@code{ssse3}, +@code{sse4.1}, +@code{sse4.2}, +@code{sse4}, +@code{nosse}, +@code{nosse2}, +@code{nosse3}, +@code{nossse3}, +@code{nosse4.1}, +@code{nosse4.2}, +@code{nosse4}, +@code{avx}, +@code{avx2}, +@code{noavx}, +@code{noavx2}, +@code{adx}, +@code{rdseed}, +@code{prfchw}, +@code{smap}, +@code{mpx}, +@code{sha}, +@code{rdpid}, +@code{ptwrite}, +@code{cet}, +@code{gfni}, +@code{vaes}, +@code{vpclmulqdq}, +@code{prefetchwt1}, +@code{clflushopt}, +@code{se1}, +@code{clwb}, +@code{movdiri}, +@code{movdir64b}, +@code{enqcmd}, +@code{avx512f}, +@code{avx512cd}, +@code{avx512er}, +@code{avx512pf}, +@code{avx512vl}, +@code{avx512bw}, +@code{avx512dq}, +@code{avx512ifma}, +@code{avx512vbmi}, +@code{avx512_4fmaps}, +@code{avx512_4vnniw}, +@code{avx512_vpopcntdq}, +@code{avx512_vbmi2}, +@code{avx512_vnni}, +@code{avx512_bitalg}, +@code{avx512_bf16}, +@code{noavx512f}, +@code{noavx512cd}, +@code{noavx512er}, +@code{noavx512pf}, +@code{noavx512vl}, +@code{noavx512bw}, +@code{noavx512dq}, +@code{noavx512ifma}, +@code{noavx512vbmi}, +@code{noavx512_4fmaps}, +@code{noavx512_4vnniw}, +@code{noavx512_vpopcntdq}, +@code{noavx512_vbmi2}, +@code{noavx512_vnni}, +@code{noavx512_bitalg}, +@code{noavx512_vp2intersect}, +@code{noavx512_bf16}, +@code{noenqcmd}, +@code{vmx}, +@code{vmfunc}, +@code{smx}, +@code{xsave}, +@code{xsaveopt}, +@code{xsavec}, +@code{xsaves}, +@code{aes}, +@code{pclmul}, +@code{fsgsbase}, +@code{rdrnd}, +@code{f16c}, +@code{bmi2}, +@code{fma}, +@code{movbe}, +@code{ept}, +@code{lzcnt}, +@code{hle}, +@code{rtm}, +@code{invpcid}, +@code{clflush}, +@code{mwaitx}, +@code{clzero}, +@code{wbnoinvd}, +@code{pconfig}, +@code{waitpkg}, +@code{cldemote}, +@code{lwp}, +@code{fma4}, +@code{xop}, +@code{cx16}, +@code{syscall}, +@code{rdtscp}, +@code{3dnow}, +@code{3dnowa}, +@code{sse4a}, +@code{sse5}, +@code{svme}, +@code{abm} and +@code{padlock}. +Note that rather than extending a basic instruction set, the extension +mnemonics starting with @code{no} revoke the respective functionality. + +When the @code{.arch} directive is used with @option{-march}, the +@code{.arch} directive will take precedent. + +@cindex @samp{-mtune=} option, i386 +@cindex @samp{-mtune=} option, x86-64 +@item -mtune=@var{CPU} +This option specifies a processor to optimize for. When used in +conjunction with the @option{-march} option, only instructions +of the processor specified by the @option{-march} option will be +generated. + +Valid @var{CPU} values are identical to the processor list of +@option{-march=@var{CPU}}. + +@cindex @samp{-msse2avx} option, i386 +@cindex @samp{-msse2avx} option, x86-64 +@item -msse2avx +This option specifies that the assembler should encode SSE instructions +with VEX prefix. + +@cindex @samp{-msse-check=} option, i386 +@cindex @samp{-msse-check=} option, x86-64 +@item -msse-check=@var{none} +@itemx -msse-check=@var{warning} +@itemx -msse-check=@var{error} +These options control if the assembler should check SSE instructions. +@option{-msse-check=@var{none}} will make the assembler not to check SSE +instructions, which is the default. @option{-msse-check=@var{warning}} +will make the assembler issue a warning for any SSE instruction. +@option{-msse-check=@var{error}} will make the assembler issue an error +for any SSE instruction. + +@cindex @samp{-mavxscalar=} option, i386 +@cindex @samp{-mavxscalar=} option, x86-64 +@item -mavxscalar=@var{128} +@itemx -mavxscalar=@var{256} +These options control how the assembler should encode scalar AVX +instructions. @option{-mavxscalar=@var{128}} will encode scalar +AVX instructions with 128bit vector length, which is the default. +@option{-mavxscalar=@var{256}} will encode scalar AVX instructions +with 256bit vector length. + +WARNING: Don't use this for production code - due to CPU errata the +resulting code may not work on certain models. + +@cindex @samp{-mvexwig=} option, i386 +@cindex @samp{-mvexwig=} option, x86-64 +@item -mvexwig=@var{0} +@itemx -mvexwig=@var{1} +These options control how the assembler should encode VEX.W-ignored (WIG) +VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX +instructions with vex.w = 0, which is the default. +@option{-mvexwig=@var{1}} will encode WIG EVEX instructions with +vex.w = 1. + +WARNING: Don't use this for production code - due to CPU errata the +resulting code may not work on certain models. + +@cindex @samp{-mevexlig=} option, i386 +@cindex @samp{-mevexlig=} option, x86-64 +@item -mevexlig=@var{128} +@itemx -mevexlig=@var{256} +@itemx -mevexlig=@var{512} +These options control how the assembler should encode length-ignored +(LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG +EVEX instructions with 128bit vector length, which is the default. +@option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will +encode LIG EVEX instructions with 256bit and 512bit vector length, +respectively. + +@cindex @samp{-mevexwig=} option, i386 +@cindex @samp{-mevexwig=} option, x86-64 +@item -mevexwig=@var{0} +@itemx -mevexwig=@var{1} +These options control how the assembler should encode w-ignored (WIG) +EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG +EVEX instructions with evex.w = 0, which is the default. +@option{-mevexwig=@var{1}} will encode WIG EVEX instructions with +evex.w = 1. + +@cindex @samp{-mmnemonic=} option, i386 +@cindex @samp{-mmnemonic=} option, x86-64 +@item -mmnemonic=@var{att} +@itemx -mmnemonic=@var{intel} +This option specifies instruction mnemonic for matching instructions. +The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will +take precedent. + +@cindex @samp{-msyntax=} option, i386 +@cindex @samp{-msyntax=} option, x86-64 +@item -msyntax=@var{att} +@itemx -msyntax=@var{intel} +This option specifies instruction syntax when processing instructions. +The @code{.att_syntax} and @code{.intel_syntax} directives will +take precedent. + +@cindex @samp{-mnaked-reg} option, i386 +@cindex @samp{-mnaked-reg} option, x86-64 +@item -mnaked-reg +This option specifies that registers don't require a @samp{%} prefix. +The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent. + +@cindex @samp{-madd-bnd-prefix} option, i386 +@cindex @samp{-madd-bnd-prefix} option, x86-64 +@item -madd-bnd-prefix +This option forces the assembler to add BND prefix to all branches, even +if such prefix was not explicitly specified in the source code. + +@cindex @samp{-mshared} option, i386 +@cindex @samp{-mshared} option, x86-64 +@item -mno-shared +On ELF target, the assembler normally optimizes out non-PLT relocations +against defined non-weak global branch targets with default visibility. +The @samp{-mshared} option tells the assembler to generate code which +may go into a shared library where all non-weak global branch targets +with default visibility can be preempted. The resulting code is +slightly bigger. This option only affects the handling of branch +instructions. + +@cindex @samp{-mbig-obj} option, x86-64 +@item -mbig-obj +On x86-64 PE/COFF target this option forces the use of big object file +format, which allows more than 32768 sections. + +@cindex @samp{-momit-lock-prefix=} option, i386 +@cindex @samp{-momit-lock-prefix=} option, x86-64 +@item -momit-lock-prefix=@var{no} +@itemx -momit-lock-prefix=@var{yes} +These options control how the assembler should encode lock prefix. +This option is intended as a workaround for processors, that fail on +lock prefix. This option can only be safely used with single-core, +single-thread computers +@option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes. +@option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual, +which is the default. + +@cindex @samp{-mfence-as-lock-add=} option, i386 +@cindex @samp{-mfence-as-lock-add=} option, x86-64 +@item -mfence-as-lock-add=@var{no} +@itemx -mfence-as-lock-add=@var{yes} +These options control how the assembler should encode lfence, mfence and +sfence. +@option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and +sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and +@samp{lock addl $0x0, (%esp)} in 32-bit mode. +@option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and +sfence as usual, which is the default. + +@cindex @samp{-mrelax-relocations=} option, i386 +@cindex @samp{-mrelax-relocations=} option, x86-64 +@item -mrelax-relocations=@var{no} +@itemx -mrelax-relocations=@var{yes} +These options control whether the assembler should generate relax +relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and +R_X86_64_REX_GOTPCRELX, in 64-bit mode. +@option{-mrelax-relocations=@var{yes}} will generate relax relocations. +@option{-mrelax-relocations=@var{no}} will not generate relax +relocations. The default can be controlled by a configure option +@option{--enable-x86-relax-relocations}. + +@cindex @samp{-mx86-used-note=} option, i386 +@cindex @samp{-mx86-used-note=} option, x86-64 +@item -mx86-used-note=@var{no} +@itemx -mx86-used-note=@var{yes} +These options control whether the assembler should generate +GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED +GNU property notes. The default can be controlled by the +@option{--enable-x86-used-note} configure option. + +@cindex @samp{-mevexrcig=} option, i386 +@cindex @samp{-mevexrcig=} option, x86-64 +@item -mevexrcig=@var{rne} +@itemx -mevexrcig=@var{rd} +@itemx -mevexrcig=@var{ru} +@itemx -mevexrcig=@var{rz} +These options control how the assembler should encode SAE-only +EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits +of EVEX instruction with 00, which is the default. +@option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}} +and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions +with 01, 10 and 11 RC bits, respectively. + +@cindex @samp{-mamd64} option, x86-64 +@cindex @samp{-mintel64} option, x86-64 +@item -mamd64 +@itemx -mintel64 +This option specifies that the assembler should accept only AMD64 or +Intel64 ISA in 64-bit mode. The default is to accept both. + +@cindex @samp{-O0} option, i386 +@cindex @samp{-O0} option, x86-64 +@cindex @samp{-O} option, i386 +@cindex @samp{-O} option, x86-64 +@cindex @samp{-O1} option, i386 +@cindex @samp{-O1} option, x86-64 +@cindex @samp{-O2} option, i386 +@cindex @samp{-O2} option, x86-64 +@cindex @samp{-Os} option, i386 +@cindex @samp{-Os} option, x86-64 +@item -O0 | -O | -O1 | -O2 | -Os +Optimize instruction encoding with smaller instruction size. @samp{-O} +and @samp{-O1} encode 64-bit register load instructions with 64-bit +immediate as 32-bit register load instructions with 31-bit or 32-bits +immediates, encode 64-bit register clearing instructions with 32-bit +register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector +register clearing instructions with 128-bit VEX vector register +clearing instructions, encode 128-bit/256-bit EVEX vector +register load/store instructions with VEX vector register load/store +instructions, and encode 128-bit/256-bit EVEX packed integer logical +instructions with 128-bit/256-bit VEX packed integer logical. + +@samp{-O2} includes @samp{-O1} optimization plus encodes +256-bit/512-bit EVEX vector register clearing instructions with 128-bit +EVEX vector register clearing instructions. + +@samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit +and 64-bit register tests with immediate as 8-bit register test with +immediate. @samp{-O0} turns off this optimization. + +@end table +@c man end + +@node i386-Directives +@section x86 specific Directives + +@cindex machine directives, x86 +@cindex x86 machine directives +@table @code + +@cindex @code{lcomm} directive, COFF +@item .lcomm @var{symbol} , @var{length}[, @var{alignment}] +Reserve @var{length} (an absolute expression) bytes for a local common +denoted by @var{symbol}. The section and value of @var{symbol} are +those of the new local common. The addresses are allocated in the bss +section, so that at run-time the bytes start off zeroed. Since +@var{symbol} is not declared global, it is normally not visible to +@code{@value{LD}}. The optional third parameter, @var{alignment}, +specifies the desired alignment of the symbol in the bss section. + +This directive is only available for COFF based x86 targets. + +@cindex @code{largecomm} directive, ELF +@item .largecomm @var{symbol} , @var{length}[, @var{alignment}] +This directive behaves in the same way as the @code{comm} directive +except that the data is placed into the @var{.lbss} section instead of +the @var{.bss} section @ref{Comm}. + +The directive is intended to be used for data which requires a large +amount of space, and it is only available for ELF based x86_64 +targets. + +@c FIXME: Document other x86 specific directives ? Eg: .code16gcc, + @end table @node i386-Syntax -@section AT&T Syntax versus Intel Syntax +@section i386 Syntactical Considerations +@menu +* i386-Variations:: AT&T Syntax versus Intel Syntax +* i386-Chars:: Special Characters +@end menu + +@node i386-Variations +@subsection AT&T Syntax versus Intel Syntax @cindex i386 intel_syntax pseudo op @cindex intel_syntax pseudo op, i386 @@ -135,9 +580,9 @@ operands are prefixed by @samp{*}; they are undelimited in Intel syntax. AT&T and Intel syntax use the opposite order for source and destination operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The @samp{source, dest} convention is maintained for compatibility with -previous Unix assemblers. Note that instructions with more than one -source operand, such as the @samp{enter} instruction, do @emph{not} have -reversed order. @ref{i386-Bugs}. +previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and +instructions with 2 immediate operands, such as the @samp{enter} +instruction, do @emph{not} have reversed order. @ref{i386-Bugs}. @cindex mnemonic suffixes, i386 @cindex sizes operands, i386 @@ -149,11 +594,19 @@ reversed order. @ref{i386-Bugs}. In AT&T syntax the size of memory operands is determined from the last character of the instruction mnemonic. Mnemonic suffixes of @samp{b}, @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long -(32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes -this by prefixing memory operands (@emph{not} the instruction mnemonics) with -@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus, -Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T -syntax. +(32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes +of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm +(256-bit vector) and zmm (512-bit vector) memory references, only when there's +no other way to disambiguate an instruction. Intel syntax accomplishes this by +prefixing memory operands (@emph{not} the instruction mnemonics) with +@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr}, +@samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel +syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T +syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and +@samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references. + +In 64-bit code, @samp{movabs} can be used to encode the @samp{mov} +instruction with the 64-bit displacement or immediate operand. @cindex return instructions, i386 @cindex i386 jump, call, return @@ -177,8 +630,32 @@ The AT&T assembler does not provide support for multiple section programs. Unix style systems expect all programs to be single sections. @end itemize +@node i386-Chars +@subsection Special Characters + +@cindex line comment character, i386 +@cindex i386 line comment character +The presence of a @samp{#} appearing anywhere on a line indicates the +start of a comment that extends to the end of that line. + +If a @samp{#} appears as the first character of a line then the whole +line is treated as a comment, but in this case the line can also be a +logical line number directive (@pxref{Comments}) or a preprocessor +control command (@pxref{Preprocessing}). + +If the @option{--divide} command-line option has not been specified +then the @samp{/} character appearing anywhere on a line also +introduces a line comment. + +@cindex line separator, i386 +@cindex statement separator, i386 +@cindex i386 line separator +The @samp{;} character can be used to separate statements on the same +line. + @node i386-Mnemonics -@section Instruction Naming +@section i386-Mnemonics +@subsection Instruction Naming @cindex i386 instruction naming @cindex instruction naming, i386 @@ -213,6 +690,42 @@ thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), @samp{wq} (from word to quadruple word), and @samp{lq} (from long to quadruple word). +@cindex encoding options, i386 +@cindex encoding options, x86-64 + +Different encoding options can be specified via pseudo prefixes: + +@itemize @bullet +@item +@samp{@{disp8@}} -- prefer 8-bit displacement. + +@item +@samp{@{disp32@}} -- prefer 32-bit displacement. + +@item +@samp{@{load@}} -- prefer load-form instruction. + +@item +@samp{@{store@}} -- prefer store-form instruction. + +@item +@samp{@{vex2@}} -- prefer 2-byte VEX prefix for VEX instruction. + +@item +@samp{@{vex3@}} -- prefer 3-byte VEX prefix for VEX instruction. + +@item +@samp{@{evex@}} -- encode with EVEX prefix. + +@item +@samp{@{rex@}} -- prefer REX prefix for integer and legacy vector +instructions (x86-64 only). Note that this differs from the @samp{rex} +prefix which generates REX prefix unconditionally. + +@item +@samp{@{nooptimize@}} -- disable instruction size optimization. +@end itemize + @cindex conversion instructions, i386 @cindex i386 conversion instructions @cindex conversion instructions, x86-64 @@ -254,6 +767,21 @@ Far call/jump instructions are @samp{lcall} and @samp{ljmp} in AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel convention. +@subsection AT&T Mnemonic versus Intel Mnemonic + +@cindex i386 mnemonic compatibility +@cindex mnemonic compatibility, i386 + +@code{@value{AS}} supports assembly using Intel mnemonic. +@code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and +@code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T +syntax for compatibility with the output of @code{@value{GCC}}. +Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp}, +@samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp}, +@samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386 +assembler with different mnemonics from those in Intel IA32 specification. +@code{@value{GCC}} generates those instructions with AT&T mnemonic. + @node i386-Regs @section Register Naming @@ -286,8 +814,8 @@ the 6 section registers @samp{%cs} (code section), @samp{%ds} and @samp{%gs}. @item -the 3 processor control registers @samp{%cr0}, @samp{%cr2}, and -@samp{%cr3}. +the 5 processor control registers @samp{%cr0}, @samp{%cr2}, +@samp{%cr3}, @samp{%cr4}, and @samp{%cr8}. @item the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2}, @@ -305,7 +833,7 @@ These registers are overloaded by 8 MMX registers @samp{%mm0}, @samp{%mm6} and @samp{%mm7}. @item -the 8 SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, +the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2}, @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}. @end itemize @@ -322,13 +850,13 @@ pointer) the 8 extended registers @samp{%r8}--@samp{%r15}. @item -the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d} +the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}. @item -the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w} +the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}. @item -the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b} +the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}. @item the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. @@ -337,7 +865,43 @@ the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}. the 8 debug registers: @samp{%db8}--@samp{%db15}. @item -the 8 SSE registers: @samp{%xmm8}--@samp{%xmm15}. +the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}. +@end itemize + +With the AVX extensions more registers were made available: + +@itemize @bullet + +@item +the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8 +available in 32-bit mode). The bottom 128 bits are overlaid with the +@samp{xmm0}--@samp{xmm15} registers. + +@end itemize + +The AVX2 extensions made in 64-bit mode more registers available: + +@itemize @bullet + +@item +the 16 128-bit registers @samp{%xmm16}--@samp{%xmm31} and the 16 256-bit +registers @samp{%ymm16}--@samp{%ymm31}. + +@end itemize + +The AVX512 extensions added the following registers: + +@itemize @bullet + +@item +the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8 +available in 32-bit mode). The bottom 128 bits are overlaid with the +@samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are +overlaid with the @samp{%ymm0}--@samp{%ymm31} registers. + +@item +the 8 mask registers @samp{%k0}--@samp{%k7}. + @end itemize @node i386-Prefixes @@ -604,7 +1168,7 @@ then stores the result in the 4 byte location @samp{mem}) @code{@value{AS}} supports Intel's MMX instruction set (SIMD instructions for integer data), available on Intel's Pentium MMX processors and Pentium II processors, AMD's K6 and K6-2 processors, -Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow! +Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@: instruction set (SIMD instructions for 32-bit floating point data) available on AMD's K6-2 processor and possibly others in the future. @@ -620,6 +1184,55 @@ as the floating point stack. See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed from the Intel syntax. +@node i386-LWP +@section AMD's Lightweight Profiling Instructions + +@cindex LWP, i386 +@cindex LWP, x86-64 + +@code{@value{AS}} supports AMD's Lightweight Profiling (LWP) +instruction set, available on AMD's Family 15h (Orochi) processors. + +LWP enables applications to collect and manage performance data, and +react to performance events. The collection of performance data +requires no context switches. LWP runs in the context of a thread and +so several counters can be used independently across multiple threads. +LWP can be used in both 64-bit and legacy 32-bit modes. + +For detailed information on the LWP instruction set, see the +@cite{AMD Lightweight Profiling Specification} available at +@uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}. + +@node i386-BMI +@section Bit Manipulation Instructions + +@cindex BMI, i386 +@cindex BMI, x86-64 + +@code{@value{AS}} supports the Bit Manipulation (BMI) instruction set. + +BMI instructions provide several instructions implementing individual +bit manipulation operations such as isolation, masking, setting, or +resetting. + +@c Need to add a specification citation here when available. + +@node i386-TBM +@section AMD's Trailing Bit Manipulation Instructions + +@cindex TBM, i386 +@cindex TBM, x86-64 + +@code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM) +instruction set, available on AMD's BDVER2 processors (Trinity and +Viperfish). + +TBM instructions provide instructions implementing individual bit +manipulation operations such as isolating, masking, setting, resetting, +complementing, and operations on trailing zeros and ones. + +@c Need to add a specification citation here when available. + @node i386-16bit @section Writing 16-bit Code @@ -636,8 +1249,9 @@ or 64-bit x86-64 code depending on the default configuration, it also supports writing code to run in real mode or in 16-bit protected mode code segments. To do this, put a @samp{.code16} or @samp{.code16gcc} directive before the assembly language instructions to -be run in 16-bit mode. You can switch @code{@value{AS}} back to writing -normal 32-bit code with the @samp{.code32} directive. +be run in 16-bit mode. You can switch @code{@value{AS}} to writing +32-bit code with the @samp{.code32} directive or 64-bit code with the +@samp{.code64} directive. @samp{.code16gcc} provides experimental support for generating 16-bit code from gcc, and differs from @samp{.code16} in that @samp{call}, @@ -667,31 +1281,10 @@ value @samp{4} onto the stack, decrementing @samp{%esp} by 2. @end smallexample The same code in a 16-bit code section would generate the machine -opcode bytes @samp{6a 04} (ie. without the operand size prefix), which +opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which is correct since the processor default operand size is assumed to be 16 bits in a 16-bit code section. -@node i386-Bugs -@section AT&T Syntax bugs - -The UnixWare assembler, and probably other AT&T derived ix86 Unix -assemblers, generate floating point instructions with reversed source -and destination registers in certain cases. Unfortunately, gcc and -possibly many other programs use this reversed syntax, so we're stuck -with it. - -For example - -@smallexample - fsub %st,%st(3) -@end smallexample -@noindent -results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather -than the expected @samp{%st(3) - %st}. This happens with all the -non-commutative arithmetic floating point operations with two register -operands where the source register is @samp{%st} and the destination -register is @samp{%st(i)}. - @node i386-Arch @section Specifying CPU Architecture @@ -709,8 +1302,36 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386} @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium} @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4} -@item @samp{k6} @tab @samp{athlon} @samp{sledgehammer} -@item @samp{.mmx} @samp{.sse} @samp{.sse2} @samp{.sse3} @samp{.3dnow} +@item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2} +@item @samp{corei7} @tab @samp{l1om} @tab @samp{k1om} @tab @samp{iamcu} +@item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8} +@item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3} +@item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1} +@item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64} +@item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx} +@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} +@item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} +@item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} +@item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt} +@item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase} +@item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2} +@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle} +@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} +@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1} +@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1} +@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf} +@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma} +@item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw} +@item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni} +@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} +@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt} +@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} +@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} +@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} +@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} +@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} +@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} +@item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @end multitable Apart from the warning, there are only two other effects on @@ -742,6 +1363,27 @@ For example .arch i8086,nojumps @end smallexample +@node i386-Bugs +@section AT&T Syntax bugs + +The UnixWare assembler, and probably other AT&T derived ix86 Unix +assemblers, generate floating point instructions with reversed source +and destination registers in certain cases. Unfortunately, gcc and +possibly many other programs use this reversed syntax, so we're stuck +with it. + +For example + +@smallexample + fsub %st,%st(3) +@end smallexample +@noindent +results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather +than the expected @samp{%st(3) - %st}. This happens with all the +non-commutative arithmetic floating point operations with two register +operands where the source register is @samp{%st} and the destination +register is @samp{%st(i)}. + @node i386-Notes @section Notes