X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fdoc%2Fc-i386.texi;h=d4e6fcb698004b869f2b21428e225db62590fa2c;hb=efb763a5ea351f9d865cbe491909f03472ebf2d6;hp=9fb681e87297bbae848238139d1dd063846df461;hpb=bc31405ebb2c4297ae815ab59f59165014347528;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 9fb681e872..d4e6fcb698 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -151,6 +151,7 @@ accept various extension mnemonics. For example, @code{sse}, @code{sse2}, @code{sse3}, +@code{sse4a}, @code{ssse3}, @code{sse4.1}, @code{sse4.2}, @@ -158,6 +159,7 @@ accept various extension mnemonics. For example, @code{nosse}, @code{nosse2}, @code{nosse3}, +@code{nosse4a}, @code{nossse3}, @code{nosse4.1}, @code{nosse4.2}, @@ -185,6 +187,8 @@ accept various extension mnemonics. For example, @code{movdiri}, @code{movdir64b}, @code{enqcmd}, +@code{serialize}, +@code{tsxldtrk}, @code{avx512f}, @code{avx512cd}, @code{avx512er}, @@ -200,6 +204,7 @@ accept various extension mnemonics. For example, @code{avx512_vbmi2}, @code{avx512_vnni}, @code{avx512_bitalg}, +@code{avx512_vp2intersect}, @code{avx512_bf16}, @code{noavx512f}, @code{noavx512cd}, @@ -219,6 +224,8 @@ accept various extension mnemonics. For example, @code{noavx512_vp2intersect}, @code{noavx512_bf16}, @code{noenqcmd}, +@code{noserialize}, +@code{notsxldtrk}, @code{vmx}, @code{vmfunc}, @code{smx}, @@ -236,6 +243,7 @@ accept various extension mnemonics. For example, @code{movbe}, @code{ept}, @code{lzcnt}, +@code{popcnt}, @code{hle}, @code{rtm}, @code{invpcid}, @@ -248,6 +256,7 @@ accept various extension mnemonics. For example, @code{cldemote}, @code{rdpru}, @code{mcommit}, +@code{sev_es}, @code{lwp}, @code{fma4}, @code{xop}, @@ -258,8 +267,7 @@ accept various extension mnemonics. For example, @code{3dnowa}, @code{sse4a}, @code{sse5}, -@code{svme}, -@code{abm} and +@code{svme} and @code{padlock}. Note that rather than extending a basic instruction set, the extension mnemonics starting with @code{no} revoke the respective functionality. @@ -383,9 +391,10 @@ with default visibility can be preempted. The resulting code is slightly bigger. This option only affects the handling of branch instructions. +@cindex @samp{-mbig-obj} option, i386 @cindex @samp{-mbig-obj} option, x86-64 @item -mbig-obj -On x86-64 PE/COFF target this option forces the use of big object file +On PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections. @cindex @samp{-momit-lock-prefix=} option, i386 @@ -461,6 +470,53 @@ on an instruction. It is equivalent to @option{-malign-branch-prefix-size=5}. The default doesn't align branches. +@cindex @samp{-mlfence-after-load=} option, i386 +@cindex @samp{-mlfence-after-load=} option, x86-64 +@item -mlfence-after-load=@var{no} +@itemx -mlfence-after-load=@var{yes} +These options control whether the assembler should generate lfence +after load instructions. @option{-mlfence-after-load=@var{yes}} will +generate lfence. @option{-mlfence-after-load=@var{no}} will not generate +lfence, which is the default. + +@cindex @samp{-mlfence-before-indirect-branch=} option, i386 +@cindex @samp{-mlfence-before-indirect-branch=} option, x86-64 +@item -mlfence-before-indirect-branch=@var{none} +@item -mlfence-before-indirect-branch=@var{all} +@item -mlfence-before-indirect-branch=@var{register} +@itemx -mlfence-before-indirect-branch=@var{memory} +These options control whether the assembler should generate lfence +before indirect near branch instructions. +@option{-mlfence-before-indirect-branch=@var{all}} will generate lfence +before indirect near branch via register and issue a warning before +indirect near branch via memory. +It also implicitly sets @option{-mlfence-before-ret=@var{shl}} when +there's no explict @option{-mlfence-before-ret=}. +@option{-mlfence-before-indirect-branch=@var{register}} will generate +lfence before indirect near branch via register. +@option{-mlfence-before-indirect-branch=@var{memory}} will issue a +warning before indirect near branch via memory. +@option{-mlfence-before-indirect-branch=@var{none}} will not generate +lfence nor issue warning, which is the default. Note that lfence won't +be generated before indirect near branch via register with +@option{-mlfence-after-load=@var{yes}} since lfence will be generated +after loading branch target register. + +@cindex @samp{-mlfence-before-ret=} option, i386 +@cindex @samp{-mlfence-before-ret=} option, x86-64 +@item -mlfence-before-ret=@var{none} +@item -mlfence-before-ret=@var{shl} +@item -mlfence-before-ret=@var{or} +@item -mlfence-before-ret=@var{yes} +@itemx -mlfence-before-ret=@var{not} +These options control whether the assembler should generate lfence +before ret. @option{-mlfence-before-ret=@var{or}} will generate +generate or instruction with lfence. +@option{-mlfence-before-ret=@var{shl/yes}} will generate shl instruction +with lfence. @option{-mlfence-before-ret=@var{not}} will generate not +instruction with lfence. @option{-mlfence-before-ret=@var{none}} will not +generate lfence, which is the default. + @cindex @samp{-mx86-used-note=} option, i386 @cindex @samp{-mx86-used-note=} option, x86-64 @item -mx86-used-note=@var{no} @@ -488,7 +544,8 @@ with 01, 10 and 11 RC bits, respectively. @item -mamd64 @itemx -mintel64 This option specifies that the assembler should accept only AMD64 or -Intel64 ISA in 64-bit mode. The default is to accept both. +Intel64 ISA in 64-bit mode. The default is to accept common, Intel64 +only and AMD64 ISAs. @cindex @samp{-O0} option, i386 @cindex @samp{-O0} option, x86-64 @@ -749,22 +806,6 @@ operand. @end itemize -Almost all instructions have the same names in AT&T and Intel format. -There are a few exceptions. The sign extend and zero extend -instructions need two sizes to specify them. They need a size to -sign/zero extend @emph{from} and a size to zero extend @emph{to}. This -is accomplished by using two instruction mnemonic suffixes in AT&T -syntax. Base names for sign extend and zero extend are -@samp{movs@dots{}} and @samp{movz@dots{}} in AT&T syntax (@samp{movsx} -and @samp{movzx} in Intel syntax). The instruction mnemonic suffixes -are tacked on to this base name, the @emph{from} suffix before the -@emph{to} suffix. Thus, @samp{movsbl %al, %edx} is AT&T syntax for -``move sign extend @emph{from} %al @emph{to} %edx.'' Possible suffixes, -thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word), -@samp{wl} (from word to long), @samp{bq} (from byte to quadruple word), -@samp{wq} (from word to quadruple word), and @samp{lq} (from long to -quadruple word). - @cindex encoding options, i386 @cindex encoding options, x86-64 @@ -834,6 +875,59 @@ are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these instructions. +@cindex extension instructions, i386 +@cindex i386 extension instructions +@cindex extension instructions, x86-64 +@cindex x86-64 extension instructions +The Intel-syntax extension instructions + +@itemize @bullet +@item +@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}. + +@item +@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}. + +@item +@samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64} +(x86-64 only). + +@item +@samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32} + +@item +@samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64} +(x86-64 only). + +@item +@samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64} +(x86-64 only). + +@item +@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}. + +@item +@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}. + +@item +@samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64} +(x86-64 only). + +@item +@samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32} + +@item +@samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64} +(x86-64 only). +@end itemize + +@noindent +are called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx}, +@samp{movsbq/movsb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw}, +@samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx}, +@samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx}, +@samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax. + @cindex jump instructions, i386 @cindex call instructions, i386 @cindex jump instructions, x86-64 @@ -1390,13 +1484,14 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{btver1} @item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64} @item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx} -@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} +@item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a} @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4} @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept} @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt} @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase} @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2} -@item @samp{.lzcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} @tab @samp{.hle} +@item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc} +@item @samp{.hle} @item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1} @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1} @@ -1408,12 +1503,12 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} -@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} +@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk} @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} -@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} +@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru} -@item @samp{.mcommit} +@item @samp{.mcommit} @tab @samp{.sev_es} @end multitable Apart from the warning, there are only two other effects on @@ -1454,6 +1549,18 @@ There are some discrepancies between AMD64 and Intel64 ISAs. @item For @samp{movsxd} with 16-bit destination register, AMD64 supports 32-bit source operand and Intel64 supports 16-bit source operand. + +@item For far branches (with explicit memory operand), both ISAs support +32- and 16-bit operand size. Intel64 additionally supports 64-bit +operand size, encoded as @samp{ljmpq} and @samp{lcallq} in AT&T syntax +and with an explicit @samp{tbyte ptr} operand size specifier in Intel +syntax. + +@item @samp{lfs}, @samp{lgs}, and @samp{lss} similarly allow for 16- +and 32-bit operand size (32- and 48-bit memory operand) in both ISAs, +while Intel64 additionally supports 64-bit operand sise (80-bit memory +operands). + @end itemize @node i386-Bugs