X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fdoc%2Fc-i386.texi;h=e0d0bc9f945f47aa3cb1ee30b061a6012620ed44;hb=5641ec015a191e0584fd4cae57bb3262f7a51735;hp=77ccfbc1ab641dbba92aa2db4cab530e63b1c9ae;hpb=03751133023c5623cf60f8d3222cb79a376331f9;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi index 77ccfbc1ab..e0d0bc9f94 100644 --- a/gas/doc/c-i386.texi +++ b/gas/doc/c-i386.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1991-2018 Free Software Foundation, Inc. +@c Copyright (C) 1991-2019 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @c man end @@ -183,6 +183,7 @@ accept various extension mnemonics. For example, @code{clwb}, @code{movdiri}, @code{movdir64b}, +@code{enqcmd}, @code{avx512f}, @code{avx512cd}, @code{avx512er}, @@ -198,6 +199,7 @@ accept various extension mnemonics. For example, @code{avx512_vbmi2}, @code{avx512_vnni}, @code{avx512_bitalg}, +@code{avx512_bf16}, @code{noavx512f}, @code{noavx512cd}, @code{noavx512er}, @@ -213,6 +215,9 @@ accept various extension mnemonics. For example, @code{noavx512_vbmi2}, @code{noavx512_vnni}, @code{noavx512_bitalg}, +@code{noavx512_vp2intersect}, +@code{noavx512_bf16}, +@code{noenqcmd}, @code{vmx}, @code{vmfunc}, @code{smx}, @@ -298,6 +303,9 @@ AVX instructions with 128bit vector length, which is the default. @option{-mavxscalar=@var{256}} will encode scalar AVX instructions with 256bit vector length. +WARNING: Don't use this for production code - due to CPU errata the +resulting code may not work on certain models. + @cindex @samp{-mvexwig=} option, i386 @cindex @samp{-mvexwig=} option, x86-64 @item -mvexwig=@var{0} @@ -308,6 +316,9 @@ instructions with vex.w = 0, which is the default. @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with vex.w = 1. +WARNING: Don't use this for production code - due to CPU errata the +resulting code may not work on certain models. + @cindex @samp{-mevexlig=} option, i386 @cindex @samp{-mevexlig=} option, x86-64 @item -mevexlig=@var{128} @@ -453,10 +464,22 @@ Intel64 ISA in 64-bit mode. The default is to accept both. Optimize instruction encoding with smaller instruction size. @samp{-O} and @samp{-O1} encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits -immediates and encode 64-bit register clearing instructions with 32-bit -register clearing instructions. @samp{-O2} includes @samp{-O1} -optimization plus encodes 256-bit and 512-bit vector register clearing -instructions with 128-bit vector register clearing instructions. +immediates, encode 64-bit register clearing instructions with 32-bit +register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector +register clearing instructions with 128-bit VEX vector register +clearing instructions, encode 128-bit/256-bit EVEX vector +register load/store instructions with VEX vector register load/store +instructions, and encode 128-bit/256-bit EVEX packed integer logical +instructions with 128-bit/256-bit VEX packed integer logical. + +@samp{-O2} includes @samp{-O1} optimization plus encodes +256-bit/512-bit EVEX vector register clearing instructions with 128-bit +EVEX vector register clearing instructions. In 64-bit mode VEX encoded +instructions with commutative source operands will also have their +source operands swapped if this allows using the 2-byte VEX prefix form +instead of the 3-byte one. Certain forms of AND as well as OR with the +same (register) operand specified twice will also be changed to TEST. + @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate. @samp{-O0} turns off this optimization. @@ -575,11 +598,16 @@ instruction, do @emph{not} have reversed order. @ref{i386-Bugs}. In AT&T syntax the size of memory operands is determined from the last character of the instruction mnemonic. Mnemonic suffixes of @samp{b}, @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long -(32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes -this by prefixing memory operands (@emph{not} the instruction mnemonics) with -@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr} and @samp{qword ptr}. Thus, -Intel @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T -syntax. +(32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes +of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm +(256-bit vector) and zmm (512-bit vector) memory references, only when there's +no other way to disambiguate an instruction. Intel syntax accomplishes this by +prefixing memory operands (@emph{not} the instruction mnemonics) with +@samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr}, +@samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel +syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T +syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and +@samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references. In 64-bit code, @samp{movabs} can be used to encode the @samp{mov} instruction with the 64-bit displacement or immediate operand. @@ -1299,11 +1327,11 @@ supported on the CPU specified. The choices for @var{cpu_type} are: @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma} @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw} @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni} -@item @samp{.avx512_bitalg} +@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect} @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @item @samp{.ibt} @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote} @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq} -@item @samp{.movdiri} @tab @samp{.movdir64b} +@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}