X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fdoc%2Fc-ia64.texi;h=e408cf340f6bd2b75c9d0e23fa3d446c3c0b88cc;hb=2900e701e0f0216b17e04e4fff1ca4711a9c072f;hp=0885f1b3b99afaa0a3c1eeed61e0121c7c3c2863;hpb=2ee563b53258d390d7446e90a67f465d504ae44c;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/doc/c-ia64.texi b/gas/doc/c-ia64.texi index 0885f1b3b9..e408cf340f 100644 --- a/gas/doc/c-ia64.texi +++ b/gas/doc/c-ia64.texi @@ -1,5 +1,4 @@ -@c Copyright 2002 -@c Free Software Foundation, Inc. +@c Copyright (C) 2002-2016 Free Software Foundation, Inc. @c Contributed by David Mosberger-Tang @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @@ -44,7 +43,7 @@ flag in the ELF file header. This option instructs the assembler to mark the resulting object file as using the ``constant GP without function descriptor'' data model. This model is like the ``constant GP'' model, except that it -additionaly does away with function descriptors. What this means is +additionally does away with function descriptors. What this means is that the address of a function refers directly to the function's code entry-point. Normally, such an address would refer to a function descriptor, which contains both the code entry-point and the GP-value @@ -53,31 +52,61 @@ affect the machine code emitted by the assembler. All it does is turn on the EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. @item -milp32 -@item -milp64 -@item -mlp64 -@item -mp64 +@itemx -milp64 +@itemx -mlp64 +@itemx -mp64 These options select the data model. The assembler defaults to @code{-mlp64} (LP64 data model). @item -mle -@item -mbe +@itemx -mbe These options select the byte order. The @code{-mle} option selects little-endian byte order (default) and @code{-mbe} selects big-endian byte order. Note that IA-64 machine code always uses little-endian byte order. +@item -mtune=itanium1 +@itemx -mtune=itanium2 +Tune for a particular IA-64 CPU, @var{itanium1} or @var{itanium2}. The +default is @var{itanium2}. + +@item -munwind-check=warning +@itemx -munwind-check=error +These options control what the assembler will do when performing +consistency checks on unwind directives. @code{-munwind-check=warning} +will make the assembler issue a warning when an unwind directive check +fails. This is the default. @code{-munwind-check=error} will make the +assembler issue an error when an unwind directive check fails. + +@item -mhint.b=ok +@itemx -mhint.b=warning +@itemx -mhint.b=error +These options control what the assembler will do when the @samp{hint.b} +instruction is used. @code{-mhint.b=ok} will make the assembler accept +@samp{hint.b}. @code{-mint.b=warning} will make the assembler issue a +warning when @samp{hint.b} is used. @code{-mhint.b=error} will make +the assembler treat @samp{hint.b} as an error, which is the default. + @item -x -@item -xexplicit -These options turn on dependency violation checking. This checking is turned on by -default. +@itemx -xexplicit +These options turn on dependency violation checking. @item -xauto This option instructs the assembler to automatically insert stop bits where necessary -to remove dependency violations. +to remove dependency violations. This is the default mode. + +@item -xnone +This option turns off dependency violation checking. @item -xdebug This turns on debug output intended to help tracking down bugs in the dependency violation checker. +@item -xdebugn +This is a shortcut for -xnone -xdebug. + +@item -xdebugx +This is a shortcut for -xexplicit -xdebug. + @end table @cindex IA-64 Syntax @@ -110,12 +139,12 @@ Reference Guide. @cindex IA-64 registers @cindex register names, IA-64 -The 128 integer registers are refered to as @samp{r@var{n}}. -The 128 floating-point registers are refered to as @samp{f@var{n}}. -The 128 application registers are refered to as @samp{ar@var{n}}. -The 128 control registers are refered to as @samp{cr@var{n}}. -The 64 one-bit predicate registers are refered to as @samp{p@var{n}}. -The 8 branch registers are refered to as @samp{b@var{n}}. +The 128 integer registers are referred to as @samp{r@var{n}}. +The 128 floating-point registers are referred to as @samp{f@var{n}}. +The 128 application registers are referred to as @samp{ar@var{n}}. +The 128 control registers are referred to as @samp{cr@var{n}}. +The 64 one-bit predicate registers are referred to as @samp{p@var{n}}. +The 8 branch registers are referred to as @samp{b@var{n}}. In addition, the assembler defines a number of aliases: @samp{gp} (@samp{r1}), @samp{sp} (@samp{r12}), @samp{rp} (@samp{b0}), @samp{ret0} (@samp{r8}), @samp{ret1} (@samp{r9}), @samp{ret2} (@samp{r10}), @@ -136,10 +165,25 @@ the end-of-interrupt register (@samp{cr67}). The assembler defines bit masks for each of the bits in the IA-64 processor status register. For example, @samp{psr.ic} corresponds to a value of 0x2000. These masks are primarily intended for use with -the @sample{ssm}/@sample{sum} and @sample{rsm}/@sample{rum} +the @samp{ssm}/@samp{sum} and @samp{rsm}/@samp{rum} instructions, but they can be used anywhere else where an integer constant is expected. +@node IA-64-Relocs +@subsection Relocations +@cindex IA-64 relocations + +In addition to the standard IA-64 relocations, the following relocations are +implemented by @code{@value{AS}}: + +@table @code +@item @@slotcount(@var{V}) +Convert the address offset @var{V} into a slot count. This pseudo +function is available only on VMS. The expression @var{V} must be +known at assembly time: it can't reference undefined symbols or symbols in +different sections. +@end table + @node IA-64 Opcodes @section Opcodes For detailed information on the IA-64 machine instruction set, see the