X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fdoc%2Fc-m32r.texi;h=215092e7455240b02aa8e790d46a86882384e8e2;hb=79052aaec9ec394bb6c8ec9d68e7e86d5838e42b;hp=f121ede48145a85f2eb5c5c3c41bc82c8290078f;hpb=dc9e099fc0eced486ae2b49455c9da113c11f4ff;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/doc/c-m32r.texi b/gas/doc/c-m32r.texi index f121ede481..215092e745 100644 --- a/gas/doc/c-m32r.texi +++ b/gas/doc/c-m32r.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1991, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation, Inc. +@c Copyright (C) 1991-2016 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @ifset GENERIC @@ -11,3 +11,346 @@ @chapter M32R Dependent Features @end ifclear +@cindex M32R support +@menu +* M32R-Opts:: M32R Options +* M32R-Directives:: M32R Directives +* M32R-Warnings:: M32R Warnings +@end menu + +@node M32R-Opts +@section M32R Options + +@cindex options, M32R +@cindex M32R options + +The Renease M32R version of @code{@value{AS}} has a few machine +dependent options: + +@table @code + +@item -m32rx +@cindex @samp{-m32rx} option, M32RX +@cindex architecture options, M32RX +@cindex M32R architecture options +@code{@value{AS}} can assemble code for several different members of the +Renesas M32R family. Normally the default is to assemble code for +the M32R microprocessor. This option may be used to change the default +to the M32RX microprocessor, which adds some more instructions to the +basic M32R instruction set, and some additional parameters to some of +the original instructions. + +@item -m32r2 +@cindex @samp{-m32rx} option, M32R2 +@cindex architecture options, M32R2 +@cindex M32R architecture options +This option changes the target processor to the M32R2 +microprocessor. + +@item -m32r +@cindex @samp{-m32r} option, M32R +@cindex architecture options, M32R +@cindex M32R architecture options +This option can be used to restore the assembler's default behaviour of +assembling for the M32R microprocessor. This can be useful if the +default has been changed by a previous command line option. + +@item -little +@cindex @code{-little} option, M32R +This option tells the assembler to produce little-endian code and +data. The default is dependent upon how the toolchain was +configured. + +@item -EL +@cindex @code{-EL} option, M32R +This is a synonym for @emph{-little}. + +@item -big +@cindex @code{-big} option, M32R +This option tells the assembler to produce big-endian code and +data. + +@item -EB +@cindex @code{-EB} option, M32R +This is a synonum for @emph{-big}. + +@item -KPIC +@cindex @code{-KPIC} option, M32R +@cindex PIC code generation for M32R +This option specifies that the output of the assembler should be +marked as position-independent code (PIC). + +@item -parallel +@cindex @code{-parallel} option, M32RX +This option tells the assembler to attempts to combine two sequential +instructions into a single, parallel instruction, where it is legal to +do so. + +@item -no-parallel +@cindex @code{-no-parallel} option, M32RX +This option disables a previously enabled @emph{-parallel} option. + +@item -no-bitinst +@cindex @samp{-no-bitinst}, M32R2 +This option disables the support for the extended bit-field +instructions provided by the M32R2. If this support needs to be +re-enabled the @emph{-bitinst} switch can be used to restore it. + +@item -O +@cindex @code{-O} option, M32RX +This option tells the assembler to attempt to optimize the +instructions that it produces. This includes filling delay slots and +converting sequential instructions into parallel ones. This option +implies @emph{-parallel}. + +@item -warn-explicit-parallel-conflicts +@cindex @samp{-warn-explicit-parallel-conflicts} option, M32RX +Instructs @code{@value{AS}} to produce warning messages when +questionable parallel instructions are encountered. This option is +enabled by default, but @code{@value{GCC}} disables it when it invokes +@code{@value{AS}} directly. Questionable instructions are those whose +behaviour would be different if they were executed sequentially. For +example the code fragment @samp{mv r1, r2 || mv r3, r1} produces a +different result from @samp{mv r1, r2 \n mv r3, r1} since the former +moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1 +and r3. + +@item -Wp +@cindex @samp{-Wp} option, M32RX +This is a shorter synonym for the @emph{-warn-explicit-parallel-conflicts} +option. + +@item -no-warn-explicit-parallel-conflicts +@cindex @samp{-no-warn-explicit-parallel-conflicts} option, M32RX +Instructs @code{@value{AS}} not to produce warning messages when +questionable parallel instructions are encountered. + +@item -Wnp +@cindex @samp{-Wnp} option, M32RX +This is a shorter synonym for the @emph{-no-warn-explicit-parallel-conflicts} +option. + +@item -ignore-parallel-conflicts +@cindex @samp{-ignore-parallel-conflicts} option, M32RX +This option tells the assembler's to stop checking parallel +instructions for constraint violations. This ability is provided for +hardware vendors testing chip designs and should not be used under +normal circumstances. + +@item -no-ignore-parallel-conflicts +@cindex @samp{-no-ignore-parallel-conflicts} option, M32RX +This option restores the assembler's default behaviour of checking +parallel instructions to detect constraint violations. + +@item -Ip +@cindex @samp{-Ip} option, M32RX +This is a shorter synonym for the @emph{-ignore-parallel-conflicts} +option. + +@item -nIp +@cindex @samp{-nIp} option, M32RX +This is a shorter synonym for the @emph{-no-ignore-parallel-conflicts} +option. + +@item -warn-unmatched-high +@cindex @samp{-warn-unmatched-high} option, M32R +This option tells the assembler to produce a warning message if a +@code{.high} pseudo op is encountered without a matching @code{.low} +pseudo op. The presence of such an unmatched pseudo op usually +indicates a programming error. + +@item -no-warn-unmatched-high +@cindex @samp{-no-warn-unmatched-high} option, M32R +Disables a previously enabled @emph{-warn-unmatched-high} option. + +@item -Wuh +@cindex @samp{-Wuh} option, M32RX +This is a shorter synonym for the @emph{-warn-unmatched-high} option. + +@item -Wnuh +@cindex @samp{-Wnuh} option, M32RX +This is a shorter synonym for the @emph{-no-warn-unmatched-high} option. + +@end table + +@node M32R-Directives +@section M32R Directives +@cindex directives, M32R +@cindex M32R directives + +The Renease M32R version of @code{@value{AS}} has a few architecture +specific directives: + +@table @code + +@cindex @code{low} directive, M32R +@item low @var{expression} +The @code{low} directive computes the value of its expression and +places the lower 16-bits of the result into the immediate-field of the +instruction. For example: + +@smallexample + or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 + add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred +@end smallexample + +@item high @var{expression} +@cindex @code{high} directive, M32R +The @code{high} directive computes the value of its expression and +places the upper 16-bits of the result into the immediate-field of the +instruction. For example: + +@smallexample + seth r0, #high(0x12345678) ; compute r0 = 0x12340000 + seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred +@end smallexample + +@item shigh @var{expression} +@cindex @code{shigh} directive, M32R +The @code{shigh} directive is very similar to the @code{high} +directive. It also computes the value of its expression and places +the upper 16-bits of the result into the immediate-field of the +instruction. The difference is that @code{shigh} also checks to see +if the lower 16-bits could be interpreted as a signed number, and if +so it assumes that a borrow will occur from the upper-16 bits. To +compensate for this the @code{shigh} directive pre-biases the upper +16 bit value by adding one to it. For example: + +For example: + +@smallexample + seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 + seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 +@end smallexample + +In the second example the lower 16-bits are 0x8000. If these are +treated as a signed value and sign extended to 32-bits then the value +becomes 0xffff8000. If this value is then added to 0x00010000 then +the result is 0x00008000. + +This behaviour is to allow for the different semantics of the +@code{or3} and @code{add3} instructions. The @code{or3} instruction +treats its 16-bit immediate argument as unsigned whereas the +@code{add3} treats its 16-bit immediate as a signed value. So for +example: + +@smallexample + seth r0, #shigh(0x00008000) + add3 r0, r0, #low(0x00008000) +@end smallexample + +Produces the correct result in r0, whereas: + +@smallexample + seth r0, #shigh(0x00008000) + or3 r0, r0, #low(0x00008000) +@end smallexample + +Stores 0xffff8000 into r0. + +Note - the @code{shigh} directive does not know where in the assembly +source code the lower 16-bits of the value are going set, so it cannot +check to make sure that an @code{or3} instruction is being used rather +than an @code{add3} instruction. It is up to the programmer to make +sure that correct directives are used. + +@cindex @code{.m32r} directive, M32R +@item .m32r +The directive performs a similar thing as the @emph{-m32r} command +line option. It tells the assembler to only accept M32R instructions +from now on. An instructions from later M32R architectures are +refused. + +@cindex @code{.m32rx} directive, M32RX +@item .m32rx +The directive performs a similar thing as the @emph{-m32rx} command +line option. It tells the assembler to start accepting the extra +instructions in the M32RX ISA as well as the ordinary M32R ISA. + +@cindex @code{.m32r2} directive, M32R2 +@item .m32r2 +The directive performs a similar thing as the @emph{-m32r2} command +line option. It tells the assembler to start accepting the extra +instructions in the M32R2 ISA as well as the ordinary M32R ISA. + +@cindex @code{.little} directive, M32RX +@item .little +The directive performs a similar thing as the @emph{-little} command +line option. It tells the assembler to start producing little-endian +code and data. This option should be used with care as producing +mixed-endian binary files is fraught with danger. + +@cindex @code{.big} directive, M32RX +@item .big +The directive performs a similar thing as the @emph{-big} command +line option. It tells the assembler to start producing big-endian +code and data. This option should be used with care as producing +mixed-endian binary files is fraught with danger. + +@end table + +@node M32R-Warnings +@section M32R Warnings + +@cindex warnings, M32R +@cindex M32R warnings + +There are several warning and error messages that can be produced by +@code{@value{AS}} which are specific to the M32R: + +@table @code + +@item output of 1st instruction is the same as an input to 2nd instruction - is this intentional ? +This message is only produced if warnings for explicit parallel +conflicts have been enabled. It indicates that the assembler has +encountered a parallel instruction in which the destination register of +the left hand instruction is used as an input register in the right hand +instruction. For example in this code fragment +@samp{mv r1, r2 || neg r3, r1} register r1 is the destination of the +move instruction and the input to the neg instruction. + +@item output of 2nd instruction is the same as an input to 1st instruction - is this intentional ? +This message is only produced if warnings for explicit parallel +conflicts have been enabled. It indicates that the assembler has +encountered a parallel instruction in which the destination register of +the right hand instruction is used as an input register in the left hand +instruction. For example in this code fragment +@samp{mv r1, r2 || neg r2, r3} register r2 is the destination of the +neg instruction and the input to the move instruction. + +@item instruction @samp{...} is for the M32RX only +This message is produced when the assembler encounters an instruction +which is only supported by the M32Rx processor, and the @samp{-m32rx} +command line flag has not been specified to allow assembly of such +instructions. + +@item unknown instruction @samp{...} +This message is produced when the assembler encounters an instruction +which it does not recognize. + +@item only the NOP instruction can be issued in parallel on the m32r +This message is produced when the assembler encounters a parallel +instruction which does not involve a NOP instruction and the +@samp{-m32rx} command line flag has not been specified. Only the M32Rx +processor is able to execute two instructions in parallel. + +@item instruction @samp{...} cannot be executed in parallel. +This message is produced when the assembler encounters a parallel +instruction which is made up of one or two instructions which cannot be +executed in parallel. + +@item Instructions share the same execution pipeline +This message is produced when the assembler encounters a parallel +instruction whoes components both use the same execution pipeline. + +@item Instructions write to the same destination register. +This message is produced when the assembler encounters a parallel +instruction where both components attempt to modify the same register. +For example these code fragments will produce this message: +@samp{mv r1, r2 || neg r1, r3} +@samp{jl r0 || mv r14, r1} +@samp{st r2, @@-r1 || mv r1, r3} +@samp{mv r1, r2 || ld r0, @@r1+} +@samp{cmp r1, r2 || addx r3, r4} (Both write to the condition bit) + +@end table