X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fdoc%2Fc-mips.texi;h=40be0fb163053433442e31f717c2059aa5b5a9cd;hb=ef2e4d86d6823ab027adcbe57ba3ffaf38a550c2;hp=4138d16f1d0646e001395fc6ae4156dd6e7105e2;hpb=963ac3630d56f158f8719609b552cd9923c39840;p=deliverable%2Fbinutils-gdb.git diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index 4138d16f1d..40be0fb163 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -1,4 +1,5 @@ -@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000 +@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, +@c 2002, 2003, 2004 @c Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @@ -25,6 +26,7 @@ Assembly Language Programming'' in the same work. * MIPS Object:: ECOFF object code * MIPS Stabs:: Directives for debugging information * MIPS ISA:: Directives to override the ISA level +* MIPS symbol sizes:: Directives to override the size of symbols * MIPS autoextend:: Directives for extending MIPS 16 bit instructions * MIPS insn:: Directive to mark data as an instruction * MIPS option stack:: Directives to save and restore options @@ -67,14 +69,17 @@ to select big-endian output, and @samp{-EL} for little-endian. @itemx -mips32 @itemx -mips32r2 @itemx -mips64 +@itemx -mips64r2 Generate code for a particular MIPS Instruction Set Architecture level. @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors, @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and -@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, and -@samp{-mips64} correspond to generic @sc{MIPS V}, @sc{MIPS32}, -@sc{MIPS32 Release 2}, and -@sc{MIPS64} ISA processors, respectively. You can also switch +@sc{r10000} processors. @samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, +@samp{-mips64}, and @samp{-mips64r2} +correspond to generic +@sc{MIPS V}, @sc{MIPS32}, @sc{MIPS32 Release 2}, @sc{MIPS64}, +and @sc{MIPS64 Release 2} +ISA processors, respectively. You can also switch instruction sets during the assembly; see @ref{MIPS ISA, Directives to override the ISA level}. @@ -113,16 +118,26 @@ Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. @samp{-no-mdmx} turns off this option. +@item -mmt +@itemx -mno-mt +Generate code for the MT Application Specific Extension. +This tells the assembler to accept MT instructions. +@samp{-mno-mt} turns off this option. + @item -mfix7000 @itemx -mno-fix7000 Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions. -@item -mfix-vr4122-bugs -@itemx -no-mfix-vr4122-bugs -Insert @samp{nop} instructions to avoid errors in certain versions of -the vr4122 core. This option is intended to be used on GCC-generated -code: it is not designed to catch errors in hand-written assembler code. +@item -mfix-vr4120 +@itemx -no-mfix-vr4120 +Insert nops to work around certain VR4120 errata. This option is +intended to be used on GCC-generated code: it is not designed to catch +all problems in hand-written assembler code. + +@item -mfix-vr4130 +@itemx -no-mfix-vr4130 +Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata. @item -m4010 @itemx -no-m4010 @@ -193,6 +208,13 @@ identical to @samp{-march=@var{cpu}}. Record which ABI the source code uses. The recognized arguments are: @samp{32}, @samp{n32}, @samp{o64}, @samp{64} and @samp{eabi}. +@item -msym32 +@itemx -mno-sym32 +@cindex -msym32 +@cindex -mno-sym32 +Equivalent to adding @code{.set sym32} or @code{.set nosym32} to +the beginning of the assembler input. @xref{MIPS symbol sizes}. + @cindex @code{-nocpp} ignored (MIPS) @item -nocpp This option is ignored. It is accepted for command-line compatibility with @@ -230,9 +252,20 @@ are only supported at Instruction Set Architecture level 2 and higher. Generate code to take a break exception rather than a trap exception when an error is detected. This is the default. -@item -n -When this option is used, @code{@value{AS}} will issue a warning every -time it generates a nop instruction from a macro. +@item -mpdr +@itemx -mno-pdr +Control generation of @code{.pdr} sections. Off by default on IRIX, on +elsewhere. + +@item -mshared +@itemx -mno-shared +When generating code using the Unix calling conventions (selected by +@samp{-KPIC} or @samp{-mcall_shared}), gas will normally generate code +which can go into a shared library. The @samp{-mno-shared} option +tells gas to generate code which uses the calling convention, but can +not go into a shared library. The resulting code is slightly more +efficient. This option only affects the handling of the +@samp{.cpload} and @samp{.cpsetup} pseudo-ops. @end table @node MIPS Object @@ -282,6 +315,61 @@ not by traditional @sc{mips} debuggers (this enhancement is required to fully support C++ debugging). These directives are primarily used by compilers, not assembly language programmers! +@node MIPS symbol sizes +@section Directives to override the size of symbols + +@cindex @code{.set sym32} +@cindex @code{.set nosym32} +The n64 ABI allows symbols to have any 64-bit value. Although this +provides a great deal of flexibility, it means that some macros have +much longer expansions than their 32-bit counterparts. For example, +the non-PIC expansion of @samp{dla $4,sym} is usually: + +@smallexample +lui $4,%highest(sym) +lui $1,%hi(sym) +daddiu $4,$4,%higher(sym) +daddiu $1,$1,%lo(sym) +dsll32 $4,$4,0 +daddu $4,$4,$1 +@end smallexample + +whereas the 32-bit expansion is simply: + +@smallexample +lui $4,%hi(sym) +daddiu $4,$4,%lo(sym) +@end smallexample + +n64 code is sometimes constructed in such a way that all symbolic +constants are known to have 32-bit values, and in such cases, it's +preferable to use the 32-bit expansion instead of the 64-bit +expansion. + +You can use the @code{.set sym32} directive to tell the assembler +that, from this point on, all expressions of the form +@samp{@var{symbol}} or @samp{@var{symbol} + @var{offset}} +have 32-bit values. For example: + +@smallexample +.set sym32 +dla $4,sym +lw $4,sym+16 +sw $4,sym+0x8000($4) +@end smallexample + +will cause the assembler to treat @samp{sym}, @code{sym+16} and +@code{sym+0x8000} as 32-bit values. The handling of non-symbolic +addresses is not affected. + +The directive @code{.set nosym32} ends a @code{.set sym32} block and +reverts to the normal behavior. It is also possible to change the +symbol size using the command-line options @option{-msym32} and +@option{-mno-sym32}. + +These options and directives are always accepted, but at present, +they have no effect for anything other than n64. + @node MIPS ISA @section Directives to override the ISA level @@ -289,7 +377,8 @@ assembly language programmers! @kindex @code{.set mips@var{n}} @sc{gnu} @code{@value{AS}} supports an additional directive to change the @sc{mips} Instruction Set Architecture level on the fly: @code{.set -mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, or 64. +mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 +or 64r2. The values other than 0 make the assembler accept instructions for the corresponding @sc{isa} level, from that point on in the assembly. @code{.set mips@var{n}} affects not only which instructions @@ -368,4 +457,12 @@ from the MDMX Application Specific Extension from that point on in the assembly. The @code{.set nomdmx} directive prevents MDMX instructions from being accepted. +@cindex MIPS MT instruction generation override +@kindex @code{.set mt} +@kindex @code{.set nomt} +The directive @code{.set mt} makes the assembler accept instructions +from the MT Application Specific Extension from that point on +in the assembly. The @code{.set nomt} directive prevents MT +instructions from being accepted. + Traditional @sc{mips} assemblers do not support these directives.