X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gas%2Fdoc%2Fc-mips.texi;h=b9902ffd3c47df5ad8cdc426f331f5232c3ac17a;hb=84ea6cf2c5170547163a4bf09ac2bbb3cd424685;hp=137dfe99b186999984780f6351cb8060d047be9d;hpb=156c2f8bf75a86dfa719220f9f259196d9d2491b;p=deliverable%2Fbinutils-gdb.git

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 137dfe99b1..b9902ffd3c 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -13,7 +13,8 @@
 
 @cindex MIPS processor
 @sc{gnu} @code{@value{AS}} for @sc{mips} architectures supports several
-different @sc{mips} processors, and MIPS ISA levels I through IV.  For
+different @sc{mips} processors, and MIPS ISA levels I through V, MIPS32,
+and MIPS64.  For
 information about the @sc{mips} instruction set, see @cite{MIPS RISC
 Architecture}, by Kane and Heindrich (Prentice-Hall).  For an overview
 of @sc{mips} assembly conventions, see ``Appendix D: Assembly Language
@@ -60,12 +61,19 @@ to select big-endian output, and @samp{-EL} for little-endian.
 @itemx -mips2
 @itemx -mips3
 @itemx -mips4
+@itemx -mips5
+@itemx -mips32
+@itemx -mips64
 Generate code for a particular MIPS Instruction Set Architecture level.
 @samp{-mips1} corresponds to the @sc{r2000} and @sc{r3000} processors,
 @samp{-mips2} to the @sc{r6000} processor, @samp{-mips3} to the
 @sc{r4000} processor, and @samp{-mips4} to the @sc{r8000} and
-@sc{r10000} processors.  You can also switch instruction sets during the
-assembly; see @ref{MIPS ISA,, Directives to override the ISA level}.
+@sc{r10000} processors.
+@samp{-mips5}, @samp{-mips32}, and @samp{-mips64} correspond
+to generic @sc{MIPS V}, @sc{MIPS32}, and @sc{MIPS64} ISA
+processors, respectively.
+You can also switch instruction sets during the
+assembly; see @ref{MIPS ISA, Directives to override the ISA level}.
 
 @item -mgp32
 Assume that 32-bit general purpose registers are available.  This
@@ -140,10 +148,8 @@ rm5721,
 6000,
 rm7000,
 8000,
-10000
-4Kc
-4Km
-4Kp
+10000,
+mips32-4k
 @end quotation
 
 
@@ -239,8 +245,9 @@ assembly language programmers!
 @kindex @code{.set mips@var{n}}
 @sc{gnu} @code{@value{AS}} supports an additional directive to change
 the @sc{mips} Instruction Set Architecture level on the fly: @code{.set
-mips@var{n}}.  @var{n} should be a number from 0 to 4.  A value from 1
-to 4 makes the assembler accept instructions for the corresponding
+mips@var{n}}.  @var{n} should be a number from 0 to 5, or 32 or 64.
+The values 1 to 5, 32, and 64 make the assembler accept instructions
+for the corresponding
 @sc{isa} level, from that point on in the assembly.  @code{.set
 mips@var{n}} affects not only which instructions are permitted, but also
 how certain macros are expanded.  @code{.set mips0} restores the