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diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 25071d994c..d3860f1a99 100644
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -1,5 +1,5 @@
 @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
-@c 2002, 2003, 2004
+@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
 @c Free Software Foundation, Inc.
 @c This is part of the GAS manual.
 @c For copying conditions, see the file as.texinfo.
@@ -32,6 +32,8 @@ Assembly Language Programming'' in the same work.
 * MIPS option stack::	Directives to save and restore options
 * MIPS ASE instruction generation overrides:: Directives to control
   			generation of MIPS ASE instructions
+* MIPS floating-point:: Directives to override floating-point options
+* MIPS Syntax::         MIPS specific syntactical considerations
 @end menu
 
 @node MIPS Opts
@@ -60,12 +62,24 @@ little-endian output at run time (unlike the other @sc{gnu} development
 tools, which must be configured for one or the other).  Use @samp{-EB}
 to select big-endian output, and @samp{-EL} for little-endian.
 
+@item -KPIC
+@cindex PIC selection, MIPS
+@cindex @option{-KPIC} option, MIPS
+Generate SVR4-style PIC.  This option tells the assembler to generate
+SVR4-style position-independent macro expansions.  It also tells the
+assembler to mark the output file as PIC.
+
+@item -mvxworks-pic
+@cindex @option{-mvxworks-pic} option, MIPS
+Generate VxWorks PIC.  This option tells the assembler to generate
+VxWorks-style position-independent macro expansions.
+
 @cindex MIPS architecture options
 @item -mips1
 @itemx -mips2
 @itemx -mips3
 @itemx -mips4
-@itemx -mips5
+@itemx -mips5xo
 @itemx -mips32
 @itemx -mips32r2
 @itemx -mips64
@@ -115,6 +129,13 @@ Generate code for the MIPS 16 processor.  This is equivalent to putting
 @code{.set mips16} at the start of the assembly file.  @samp{-no-mips16}
 turns off this option.
 
+@item -mmicromips
+@itemx -mno-micromips
+Generate code for the microMIPS processor.  This is equivalent to putting
+@code{.set micromips} at the start of the assembly file.  @samp{-mno-micromips}
+turns off this option.  This is equivalent to putting @code{.set nomicromips}
+at the start of the assembly file.
+
 @item -msmartmips
 @itemx -mno-smartmips
 Enables the SmartMIPS extensions to the MIPS32 instruction set, which
@@ -137,31 +158,67 @@ This tells the assembler to accept MDMX instructions.
 
 @item -mdsp
 @itemx -mno-dsp
-Generate code for the DSP Application Specific Extension.
-This tells the assembler to accept DSP instructions.
+Generate code for the DSP Release 1 Application Specific Extension.
+This tells the assembler to accept DSP Release 1 instructions.
 @samp{-mno-dsp} turns off this option.
 
+@item -mdspr2
+@itemx -mno-dspr2
+Generate code for the DSP Release 2 Application Specific Extension.
+This option implies -mdsp.
+This tells the assembler to accept DSP Release 2 instructions.
+@samp{-mno-dspr2} turns off this option.
+
 @item -mmt
 @itemx -mno-mt
 Generate code for the MT Application Specific Extension.
 This tells the assembler to accept MT instructions.
 @samp{-mno-mt} turns off this option.
 
+@item -mmcu
+@itemx -mno-mcu
+Generate code for the MCU Application Specific Extension.
+This tells the assembler to accept MCU instructions.
+@samp{-mno-mcu} turns off this option.
+
 @item -mfix7000
 @itemx -mno-fix7000
 Cause nops to be inserted if the read of the destination register
 of an mfhi or mflo instruction occurs in the following two instructions.
 
+@item -mfix-loongson2f-jump
+@itemx -mno-fix-loongson2f-jump
+Eliminate instruction fetch from outside 256M region to work around the
+Loongson2F @samp{jump} instructions.  Without it, under extreme cases,
+the kernel may crash.  The issue has been solved in latest processor
+batches, but this fix has no side effect to them.
+
+@item -mfix-loongson2f-nop
+@itemx -mno-fix-loongson2f-nop
+Replace nops by @code{or at,at,zero} to work around the Loongson2F
+@samp{nop} errata.  Without it, under extreme cases, cpu might
+deadlock.  The issue has been solved in latest loongson2f batches, but
+this fix has no side effect to them.
+
 @item -mfix-vr4120
-@itemx -no-mfix-vr4120
+@itemx -mno-fix-vr4120
 Insert nops to work around certain VR4120 errata.  This option is
 intended to be used on GCC-generated code: it is not designed to catch
 all problems in hand-written assembler code.
 
 @item -mfix-vr4130
-@itemx -no-mfix-vr4130
+@itemx -mno-fix-vr4130
 Insert nops to work around the VR4130 @samp{mflo}/@samp{mfhi} errata.
 
+@item -mfix-24k
+@itemx -no-mfix-24k
+Insert nops to work around the 24K @samp{eret}/@samp{deret} errata.
+
+@item -mfix-cn63xxp1
+@itemx -mno-fix-cn63xxp1
+Replace @code{pref} hints 0 - 4 and 6 - 24 with hint 28 to work around
+certain CN63XXP1 errata.
+
 @item -m4010
 @itemx -no-m4010
 Generate code for the LSI @sc{r4010} chip.  This tells the assembler to
@@ -219,6 +276,8 @@ rm7000,
 rm9000,
 10000,
 12000,
+14000,
+16000,
 4kc,
 4km,
 4kp,
@@ -229,23 +288,46 @@ rm9000,
 4ksd,
 m4k,
 m4kp,
+m14k,
+m14kc,
 24kc,
+24kf2_1,
 24kf,
-24kx,
+24kf1_1,
 24kec,
+24kef2_1,
 24kef,
-24kex,
+24kef1_1,
 34kc,
+34kf2_1,
 34kf,
-34kx,
+34kf1_1,
+74kc,
+74kf2_1,
+74kf,
+74kf1_1,
+74kf3_2,
+1004kc,
+1004kf2_1,
+1004kf,
+1004kf1_1,
 5kc,
 5kf,
 20kc,
 25kf,
 sb1,
-sb1a
+sb1a,
+loongson2e,
+loongson2f,
+loongson3a,
+octeon,
+xlr
 @end quotation
 
+For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are
+accepted as synonyms for @samp{@var{n}f1_1}.  These values are
+deprecated.
+
 @item -mtune=@var{cpu}
 Schedule and tune for a particular MIPS cpu.  Valid @var{cpu} values are
 identical to @samp{-march=@var{cpu}}.
@@ -268,10 +350,21 @@ other assemblers, which use it to turn off C style preprocessing.  With
 @sc{gnu} @code{@value{AS}}, there is no need for @samp{-nocpp}, because the
 @sc{gnu} assembler itself never runs the C preprocessor.
 
+@item -msoft-float
+@itemx -mhard-float
+Disable or enable floating-point instructions.  Note that by default
+floating-point instructions are always allowed even with CPU targets
+that don't have support for these instructions.
+
+@item -msingle-float
+@itemx -mdouble-float
+Disable or enable double-precision floating-point operations.  Note
+that by default double-precision floating-point operations are always
+allowed even with CPU targets that don't have support for these
+operations.
+
 @item --construct-floats
 @itemx --no-construct-floats
-@cindex --construct-floats
-@cindex --no-construct-floats
 The @code{--no-construct-floats} option disables the construction of
 double width floating point constants by loading the two halves of the
 value into the two single width floating point registers that make up
@@ -449,6 +542,12 @@ in which it will assemble instructions for the MIPS 16 processor.  Use
 
 Traditional @sc{mips} assemblers do not support this directive.
 
+The directive @code{.set micromips} puts the assembler into microMIPS mode,
+in which it will assemble instructions for the microMIPS processor.  Use
+@code{.set nomicromips} to return to normal 32 bit mode.
+
+Traditional @sc{mips} assemblers do not support this directive.
+
 @node MIPS autoextend
 @section Directives for extending MIPS 16 bit instructions
 
@@ -469,10 +568,36 @@ This directive is only meaningful when in MIPS 16 mode.  Traditional
 
 @kindex @code{.insn}
 The @code{.insn} directive tells @code{@value{AS}} that the following
-data is actually instructions.  This makes a difference in MIPS 16 mode:
-when loading the address of a label which precedes instructions,
-@code{@value{AS}} automatically adds 1 to the value, so that jumping to
-the loaded address will do the right thing.
+data is actually instructions.  This makes a difference in MIPS 16 and
+microMIPS modes: when loading the address of a label which precedes
+instructions, @code{@value{AS}} automatically adds 1 to the value, so
+that jumping to the loaded address will do the right thing.
+
+@kindex @code{.global}
+The @code{.global} and @code{.globl} directives supported by
+@code{@value{AS}} will by default mark the symbol as pointing to a
+region of data not code.  This means that, for example, any
+instructions following such a symbol will not be disassembled by
+@code{objdump} as it will regard them as data.  To change this
+behaviour an optional section name can be placed after the symbol name
+in the @code{.global} directive.  If this section exists and is known
+to be a code section, then the symbol will be marked as poiting at
+code not data.  Ie the syntax for the directive is:
+
+  @code{.global @var{symbol}[ @var{section}][, @var{symbol}[ @var{section}]] ...},
+
+Here is a short example:
+
+@example
+        .global foo .text, bar, baz .data
+foo:
+        nop
+bar:
+        .word 0x0
+baz:
+        .word 0x1
+        
+@end example
 
 @node MIPS option stack
 @section Directives to save and restore options
@@ -520,13 +645,22 @@ from the MDMX Application Specific Extension from that point on
 in the assembly.  The @code{.set nomdmx} directive prevents MDMX
 instructions from being accepted.
 
-@cindex MIPS DSP instruction generation override
+@cindex MIPS DSP Release 1 instruction generation override
 @kindex @code{.set dsp}
 @kindex @code{.set nodsp}
 The directive @code{.set dsp} makes the assembler accept instructions
-from the DSP Application Specific Extension from that point on
-in the assembly.  The @code{.set nodsp} directive prevents DSP
-instructions from being accepted.
+from the DSP Release 1 Application Specific Extension from that point
+on in the assembly.  The @code{.set nodsp} directive prevents DSP
+Release 1 instructions from being accepted.
+
+@cindex MIPS DSP Release 2 instruction generation override
+@kindex @code{.set dspr2}
+@kindex @code{.set nodspr2}
+The directive @code{.set dspr2} makes the assembler accept instructions
+from the DSP Release 2 Application Specific Extension from that point
+on in the assembly.  This dirctive implies @code{.set dsp}.  The
+@code{.set nodspr2} directive prevents DSP Release 2 instructions from
+being accepted.
 
 @cindex MIPS MT instruction generation override
 @kindex @code{.set mt}
@@ -536,4 +670,60 @@ from the MT Application Specific Extension from that point on
 in the assembly.  The @code{.set nomt} directive prevents MT
 instructions from being accepted.
 
+@cindex MIPS MCU instruction generation override
+@kindex @code{.set mcu}
+@kindex @code{.set nomcu}
+The directive @code{.set mcu} makes the assembler accept instructions
+from the MCU Application Specific Extension from that point on
+in the assembly.  The @code{.set nomcu} directive prevents MCU
+instructions from being accepted.
+
+Traditional @sc{mips} assemblers do not support these directives.
+
+@node MIPS floating-point
+@section Directives to override floating-point options
+
+@cindex Disable floating-point instructions
+@kindex @code{.set softfloat}
+@kindex @code{.set hardfloat}
+The directives @code{.set softfloat} and @code{.set hardfloat} provide
+finer control of disabling and enabling float-point instructions.
+These directives always override the default (that hard-float
+instructions are accepted) or the command-line options
+(@samp{-msoft-float} and @samp{-mhard-float}).
+
+@cindex Disable single-precision floating-point operations
+@kindex @code{.set singlefloat}
+@kindex @code{.set doublefloat}
+The directives @code{.set singlefloat} and @code{.set doublefloat}
+provide finer control of disabling and enabling double-precision
+float-point operations.  These directives always override the default
+(that double-precision operations are accepted) or the command-line
+options (@samp{-msingle-float} and @samp{-mdouble-float}).
+
 Traditional @sc{mips} assemblers do not support these directives.
+
+@node MIPS Syntax
+@section Syntactical considerations for the MIPS assembler
+@menu
+* MIPS-Chars::                Special Characters
+@end menu
+
+@node MIPS-Chars
+@subsection Special Characters
+
+@cindex line comment character, MIPS
+@cindex MIPS line comment character
+The presence of a @samp{#} on a line indicates the start of a comment
+that extends to the end of the current line.
+
+If a @samp{#} appears as the first character of a line, the whole line
+is treated as a comment, but in this case the line can also be a
+logical line number directive (@pxref{Comments}) or a
+preprocessor control command (@pxref{Preprocessing}).
+
+@cindex line separator, MIPS
+@cindex statement separator, MIPS
+@cindex MIPS line separator
+The @samp{;} character can be used to separate statements on the same
+line.