X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gdb%2Falpha-tdep.c;h=06ee90cbc7785d8277e773bdb6b98065e2e19568;hb=2f91880f3afb3cc521111dfcc99b214c77aa97a1;hp=10e753b29452b79f8e3add204768c7f47a5330ed;hpb=7a9dd1b270ed6fa1dbf81ef4aea857e7947e9d44;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/alpha-tdep.c b/gdb/alpha-tdep.c index 10e753b294..06ee90cbc7 100644 --- a/gdb/alpha-tdep.c +++ b/gdb/alpha-tdep.c @@ -1,8 +1,6 @@ /* Target-dependent code for the ALPHA architecture, for GDB, the GNU Debugger. - Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, - 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011 - Free Software Foundation, Inc. + Copyright (C) 1993-2017 Free Software Foundation, Inc. This file is part of GDB. @@ -33,7 +31,6 @@ #include "dis-asm.h" #include "symfile.h" #include "objfiles.h" -#include "gdb_string.h" #include "linespec.h" #include "regcache.h" #include "reggroups.h" @@ -46,6 +43,7 @@ #include "elf-bfd.h" #include "alpha-tdep.h" +#include /* Instruction decoding. The notations for registers, immediates and opcodes are the same as the one used in Compaq's Alpha architecture @@ -65,6 +63,7 @@ static const int stq_opcode = 0x2d; /* Branch instruction format */ #define BR_RA(insn) MEM_RA(insn) +static const int br_opcode = 0x30; static const int bne_opcode = 0x3d; /* Operate instruction format */ @@ -111,8 +110,7 @@ alpha_register_name (struct gdbarch *gdbarch, int regno) static int alpha_cannot_fetch_register (struct gdbarch *gdbarch, int regno) { - return (regno == ALPHA_ZERO_REGNUM - || strlen (alpha_register_name (gdbarch, regno)) == 0); + return (strlen (alpha_register_name (gdbarch, regno)) == 0); } static int @@ -188,7 +186,8 @@ static void alpha_lds (struct gdbarch *gdbarch, void *out, const void *in) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - ULONGEST mem = extract_unsigned_integer (in, 4, byte_order); + ULONGEST mem + = extract_unsigned_integer ((const gdb_byte *) in, 4, byte_order); ULONGEST frac = (mem >> 0) & 0x7fffff; ULONGEST sign = (mem >> 31) & 1; ULONGEST exp_msb = (mem >> 30) & 1; @@ -208,7 +207,7 @@ alpha_lds (struct gdbarch *gdbarch, void *out, const void *in) } reg = (sign << 63) | (exp << 52) | (frac << 29); - store_unsigned_integer (out, 8, byte_order, reg); + store_unsigned_integer ((gdb_byte *) out, 8, byte_order, reg); } /* Similarly, this represents exactly the conversion performed by @@ -220,15 +219,15 @@ alpha_sts (struct gdbarch *gdbarch, void *out, const void *in) enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); ULONGEST reg, mem; - reg = extract_unsigned_integer (in, 8, byte_order); + reg = extract_unsigned_integer ((const gdb_byte *) in, 8, byte_order); mem = ((reg >> 32) & 0xc0000000) | ((reg >> 29) & 0x3fffffff); - store_unsigned_integer (out, 4, byte_order, mem); + store_unsigned_integer ((gdb_byte *) out, 4, byte_order, mem); } /* The alpha needs a conversion between register and memory format if the register is a floating point register and memory format is float, as the register format must be double or memory format is an integer with 4 - bytes or less, as the representation of integers in floating point + bytes, as the representation of integers in floating point registers is different. */ static int @@ -236,7 +235,7 @@ alpha_convert_register_p (struct gdbarch *gdbarch, int regno, struct type *type) { return (regno >= ALPHA_FP0_REGNUM && regno < ALPHA_FP0_REGNUM + 31 - && TYPE_LENGTH (type) != 8); + && TYPE_LENGTH (type) == 4); } static int @@ -245,38 +244,40 @@ alpha_register_to_value (struct frame_info *frame, int regnum, int *optimizedp, int *unavailablep) { struct gdbarch *gdbarch = get_frame_arch (frame); - gdb_byte in[MAX_REGISTER_SIZE]; + struct value *value = get_frame_register_value (frame, regnum); - /* Convert to TYPE. */ - if (!get_frame_register_bytes (frame, regnum, 0, - register_size (gdbarch, regnum), - in, optimizedp, unavailablep)) - return 0; + gdb_assert (value != NULL); + *optimizedp = value_optimized_out (value); + *unavailablep = !value_entirely_available (value); - if (TYPE_LENGTH (valtype) == 4) + if (*optimizedp || *unavailablep) { - alpha_sts (gdbarch, out, in); - *optimizedp = *unavailablep = 0; - return 1; + release_value (value); + value_free (value); + return 0; } - error (_("Cannot retrieve value from floating point register")); + /* Convert to VALTYPE. */ + + gdb_assert (TYPE_LENGTH (valtype) == 4); + alpha_sts (gdbarch, out, value_contents_all (value)); + + release_value (value); + value_free (value); + return 1; } static void alpha_value_to_register (struct frame_info *frame, int regnum, struct type *valtype, const gdb_byte *in) { - gdb_byte out[MAX_REGISTER_SIZE]; + gdb_byte out[ALPHA_REGISTER_SIZE]; + + gdb_assert (TYPE_LENGTH (valtype) == 4); + gdb_assert (register_size (get_frame_arch (frame), regnum) + <= ALPHA_REGISTER_SIZE); + alpha_lds (get_frame_arch (frame), out, in); - switch (TYPE_LENGTH (valtype)) - { - case 4: - alpha_lds (get_frame_arch (frame), out, in); - break; - default: - error (_("Cannot store value in floating point register")); - } put_frame_register (frame, regnum, out); } @@ -308,8 +309,7 @@ alpha_push_dummy_call (struct gdbarch *gdbarch, struct value *function, int len; int offset; }; - struct alpha_arg *alpha_args - = (struct alpha_arg *) alloca (nargs * sizeof (struct alpha_arg)); + struct alpha_arg *alpha_args = XALLOCAVEC (struct alpha_arg, nargs); struct alpha_arg *m_arg; gdb_byte arg_reg_buffer[ALPHA_REGISTER_SIZE * ALPHA_NUM_ARG_REGS]; int required_arg_regs; @@ -477,14 +477,13 @@ alpha_extract_return_value (struct type *valtype, struct regcache *regcache, { struct gdbarch *gdbarch = get_regcache_arch (regcache); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - int length = TYPE_LENGTH (valtype); gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; ULONGEST l; switch (TYPE_CODE (valtype)) { case TYPE_CODE_FLT: - switch (length) + switch (TYPE_LENGTH (valtype)) { case 4: regcache_cooked_read (regcache, ALPHA_FP0_REGNUM, raw_buffer); @@ -507,7 +506,7 @@ alpha_extract_return_value (struct type *valtype, struct regcache *regcache, break; case TYPE_CODE_COMPLEX: - switch (length) + switch (TYPE_LENGTH (valtype)) { case 8: /* ??? This isn't correct wrt the ABI, but it's what GCC does. */ @@ -520,7 +519,7 @@ alpha_extract_return_value (struct type *valtype, struct regcache *regcache, break; case 32: - regcache_cooked_read_signed (regcache, ALPHA_V0_REGNUM, &l); + regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); read_memory (l, valbuf, 32); break; @@ -533,7 +532,7 @@ alpha_extract_return_value (struct type *valtype, struct regcache *regcache, default: /* Assume everything else degenerates to an integer. */ regcache_cooked_read_unsigned (regcache, ALPHA_V0_REGNUM, &l); - store_unsigned_integer (valbuf, length, byte_order, l); + store_unsigned_integer (valbuf, TYPE_LENGTH (valtype), byte_order, l); break; } } @@ -546,14 +545,13 @@ alpha_store_return_value (struct type *valtype, struct regcache *regcache, const gdb_byte *valbuf) { struct gdbarch *gdbarch = get_regcache_arch (regcache); - int length = TYPE_LENGTH (valtype); gdb_byte raw_buffer[ALPHA_REGISTER_SIZE]; ULONGEST l; switch (TYPE_CODE (valtype)) { case TYPE_CODE_FLT: - switch (length) + switch (TYPE_LENGTH (valtype)) { case 4: alpha_lds (gdbarch, raw_buffer, valbuf); @@ -577,7 +575,7 @@ alpha_store_return_value (struct type *valtype, struct regcache *regcache, break; case TYPE_CODE_COMPLEX: - switch (length) + switch (TYPE_LENGTH (valtype)) { case 8: /* ??? This isn't correct wrt the ABI, but it's what GCC does. */ @@ -605,7 +603,7 @@ alpha_store_return_value (struct type *valtype, struct regcache *regcache, /* Assume everything else degenerates to an integer. */ /* 32-bit values must be sign-extended to 64 bits even if the base data type is unsigned. */ - if (length == 4) + if (TYPE_LENGTH (valtype) == 4) valtype = builtin_type (gdbarch)->builtin_int32; l = unpack_long (valtype, valbuf); regcache_cooked_write_unsigned (regcache, ALPHA_V0_REGNUM, l); @@ -614,7 +612,7 @@ alpha_store_return_value (struct type *valtype, struct regcache *regcache, } static enum return_value_convention -alpha_return_value (struct gdbarch *gdbarch, struct type *func_type, +alpha_return_value (struct gdbarch *gdbarch, struct value *function, struct type *type, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf) { @@ -649,14 +647,10 @@ alpha_return_in_memory_always (struct type *type) return 1; } -static const gdb_byte * -alpha_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len) -{ - static const gdb_byte break_insn[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */ - *len = sizeof(break_insn); - return break_insn; -} +constexpr gdb_byte alpha_break_insn[] = { 0x80, 0, 0, 0 }; /* call_pal bpt */ + +typedef BP_MANIPULATION (alpha_break_insn) alpha_breakpoint; /* This returns the PC of the first insn after the prologue. @@ -687,11 +681,11 @@ alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); gdb_byte buf[ALPHA_INSN_SIZE]; - int status; + int res; - status = target_read_memory (pc, buf, sizeof (buf)); - if (status) - memory_error (status, pc); + res = target_read_memory (pc, buf, sizeof (buf)); + if (res != 0) + memory_error (TARGET_XFER_E_IO, pc); return extract_unsigned_integer (buf, sizeof (buf), byte_order); } @@ -726,7 +720,7 @@ alpha_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) post_prologue_pc = alpha_after_prologue (pc); if (post_prologue_pc != 0) - return max (pc, post_prologue_pc); + return std::max (pc, post_prologue_pc); /* Can't determine prologue from the symbol table, need to examine instructions. */ @@ -762,6 +756,94 @@ alpha_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) return pc + offset; } + +static const int ldl_l_opcode = 0x2a; +static const int ldq_l_opcode = 0x2b; +static const int stl_c_opcode = 0x2e; +static const int stq_c_opcode = 0x2f; + +/* Checks for an atomic sequence of instructions beginning with a LDL_L/LDQ_L + instruction and ending with a STL_C/STQ_C instruction. If such a sequence + is found, attempt to step through it. A breakpoint is placed at the end of + the sequence. */ + +static std::vector +alpha_deal_with_atomic_sequence (struct regcache *regcache) +{ + struct gdbarch *gdbarch = get_regcache_arch (regcache); + CORE_ADDR pc = regcache_read_pc (regcache); + CORE_ADDR breaks[2] = {-1, -1}; + CORE_ADDR loc = pc; + CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ + unsigned int insn = alpha_read_insn (gdbarch, loc); + int insn_count; + int index; + int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ + const int atomic_sequence_length = 16; /* Instruction sequence length. */ + int bc_insn_count = 0; /* Conditional branch instruction count. */ + + /* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */ + if (INSN_OPCODE (insn) != ldl_l_opcode + && INSN_OPCODE (insn) != ldq_l_opcode) + return {}; + + /* Assume that no atomic sequence is longer than "atomic_sequence_length" + instructions. */ + for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) + { + loc += ALPHA_INSN_SIZE; + insn = alpha_read_insn (gdbarch, loc); + + /* Assume that there is at most one branch in the atomic + sequence. If a branch is found, put a breakpoint in + its destination address. */ + if (INSN_OPCODE (insn) >= br_opcode) + { + int immediate = (insn & 0x001fffff) << 2; + + immediate = (immediate ^ 0x400000) - 0x400000; + + if (bc_insn_count >= 1) + return {}; /* More than one branch found, fallback + to the standard single-step code. */ + + breaks[1] = loc + ALPHA_INSN_SIZE + immediate; + + bc_insn_count++; + last_breakpoint++; + } + + if (INSN_OPCODE (insn) == stl_c_opcode + || INSN_OPCODE (insn) == stq_c_opcode) + break; + } + + /* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */ + if (INSN_OPCODE (insn) != stl_c_opcode + && INSN_OPCODE (insn) != stq_c_opcode) + return {}; + + closing_insn = loc; + loc += ALPHA_INSN_SIZE; + + /* Insert a breakpoint right after the end of the atomic sequence. */ + breaks[0] = loc; + + /* Check for duplicated breakpoints. Check also for a breakpoint + placed (branch instruction's destination) anywhere in sequence. */ + if (last_breakpoint + && (breaks[1] == breaks[0] + || (breaks[1] >= pc && breaks[1] <= closing_insn))) + last_breakpoint = 0; + + std::vector next_pcs; + + for (index = 0; index <= last_breakpoint; index++) + next_pcs.push_back (breaks[index]); + + return next_pcs; +} + /* Figure out where the longjmp will land. We expect the first arg to be a pointer to the jmp_buf structure from @@ -807,7 +889,7 @@ alpha_sigtramp_frame_unwind_cache (struct frame_info *this_frame, struct gdbarch_tdep *tdep; if (*this_prologue_cache) - return *this_prologue_cache; + return (struct alpha_sigtramp_unwind_cache *) *this_prologue_cache; info = FRAME_OBSTACK_ZALLOC (struct alpha_sigtramp_unwind_cache); *this_prologue_cache = info; @@ -913,7 +995,7 @@ alpha_sigtramp_frame_sniffer (const struct frame_unwind *self, { struct gdbarch *gdbarch = get_frame_arch (this_frame); CORE_ADDR pc = get_frame_pc (this_frame); - char *name; + const char *name; /* NOTE: cagney/2004-04-30: Do not copy/clone this code. Instead look at tramp-frame.h and other simplier per-architecture @@ -948,7 +1030,7 @@ static const struct frame_unwind alpha_sigtramp_frame_unwind = { /* Heuristic_proc_start may hunt through the text section for a long time across a 2400 baud serial line. Allows the user to limit this search. */ -static unsigned int heuristic_fence_post = 0; +static int heuristic_fence_post = 0; /* Attempt to locate the start of the function containing PC. We assume that the previous function ends with an about_to_return insn. Not foolproof by @@ -975,7 +1057,7 @@ alpha_heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) if (func) return func; - if (heuristic_fence_post == UINT_MAX + if (heuristic_fence_post == -1 || fence < tdep->vm_min_address) fence = tdep->vm_min_address; @@ -1157,7 +1239,7 @@ alpha_heuristic_frame_unwind_cache (struct frame_info *this_frame, int frame_reg, frame_size, return_reg, reg; if (*this_prologue_cache) - return *this_prologue_cache; + return (struct alpha_heuristic_unwind_cache *) *this_prologue_cache; info = FRAME_OBSTACK_ZALLOC (struct alpha_heuristic_unwind_cache); *this_prologue_cache = info; @@ -1416,7 +1498,7 @@ void alpha_supply_int_regs (struct regcache *regcache, int regno, const void *r0_r30, const void *pc, const void *unique) { - const gdb_byte *regs = r0_r30; + const gdb_byte *regs = (const gdb_byte *) r0_r30; int i; for (i = 0; i < 31; ++i) @@ -1424,7 +1506,11 @@ alpha_supply_int_regs (struct regcache *regcache, int regno, regcache_raw_supply (regcache, i, regs + i * 8); if (regno == ALPHA_ZERO_REGNUM || regno == -1) - regcache_raw_supply (regcache, ALPHA_ZERO_REGNUM, NULL); + { + const gdb_byte zero[8] = { 0 }; + + regcache_raw_supply (regcache, ALPHA_ZERO_REGNUM, zero); + } if (regno == ALPHA_PC_REGNUM || regno == -1) regcache_raw_supply (regcache, ALPHA_PC_REGNUM, pc); @@ -1437,7 +1523,7 @@ void alpha_fill_int_regs (const struct regcache *regcache, int regno, void *r0_r30, void *pc, void *unique) { - gdb_byte *regs = r0_r30; + gdb_byte *regs = (gdb_byte *) r0_r30; int i; for (i = 0; i < 31; ++i) @@ -1455,7 +1541,7 @@ void alpha_supply_fp_regs (struct regcache *regcache, int regno, const void *f0_f30, const void *fpcr) { - const gdb_byte *regs = f0_f30; + const gdb_byte *regs = (const gdb_byte *) f0_f30; int i; for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i) @@ -1471,7 +1557,7 @@ void alpha_fill_fp_regs (const struct regcache *regcache, int regno, void *f0_f30, void *fpcr) { - gdb_byte *regs = f0_f30; + gdb_byte *regs = (gdb_byte *) f0_f30; int i; for (i = ALPHA_FP0_REGNUM; i < ALPHA_FP0_REGNUM + 31; ++i) @@ -1514,9 +1600,9 @@ fp_register_sign_bit (LONGEST reg) the target of the coming instruction and breakpoint it. */ static CORE_ADDR -alpha_next_pc (struct frame_info *frame, CORE_ADDR pc) +alpha_next_pc (struct regcache *regcache, CORE_ADDR pc) { - struct gdbarch *gdbarch = get_frame_arch (frame); + struct gdbarch *gdbarch = get_regcache_arch (regcache); unsigned int insn; unsigned int op; int regno; @@ -1532,7 +1618,7 @@ alpha_next_pc (struct frame_info *frame, CORE_ADDR pc) { /* Jump format: target PC is: RB & ~3 */ - return (get_frame_register_unsigned (frame, (insn >> 16) & 0x1f) & ~3); + return (regcache_raw_get_unsigned (regcache, (insn >> 16) & 0x1f) & ~3); } if ((op & 0x30) == 0x30) @@ -1563,7 +1649,7 @@ alpha_next_pc (struct frame_info *frame, CORE_ADDR pc) regno += gdbarch_fp0_regnum (gdbarch); } - rav = get_frame_register_signed (frame, regno); + rav = regcache_raw_get_signed (regcache, regno); switch (op) { @@ -1634,18 +1720,15 @@ alpha_next_pc (struct frame_info *frame, CORE_ADDR pc) return (pc + ALPHA_INSN_SIZE); } -int -alpha_software_single_step (struct frame_info *frame) +std::vector +alpha_software_single_step (struct regcache *regcache) { - struct gdbarch *gdbarch = get_frame_arch (frame); - struct address_space *aspace = get_frame_address_space (frame); - CORE_ADDR pc, next_pc; + struct gdbarch *gdbarch = get_regcache_arch (regcache); + CORE_ADDR pc; - pc = get_frame_pc (frame); - next_pc = alpha_next_pc (frame, pc); + pc = alpha_next_pc (regcache, regcache_read_pc (regcache)); - insert_single_step_breakpoint (gdbarch, aspace, next_pc); - return 1; + return {pc}; } @@ -1662,20 +1745,12 @@ alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) struct gdbarch_tdep *tdep; struct gdbarch *gdbarch; - /* Try to determine the ABI of the object we are loading. */ - if (info.abfd != NULL && info.osabi == GDB_OSABI_UNKNOWN) - { - /* If it's an ECOFF file, assume it's OSF/1. */ - if (bfd_get_flavour (info.abfd) == bfd_target_ecoff_flavour) - info.osabi = GDB_OSABI_OSF1; - } - /* Find a candidate among extant architectures. */ arches = gdbarch_list_lookup_by_info (arches, &info); if (arches != NULL) return arches->gdbarch; - tdep = xmalloc (sizeof (struct gdbarch_tdep)); + tdep = XCNEW (struct gdbarch_tdep); gdbarch = gdbarch_alloc (&info, tdep); /* Lowest text address. This is used by heuristic_proc_start() @@ -1697,6 +1772,8 @@ alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_int_bit (gdbarch, 32); set_gdbarch_long_bit (gdbarch, 64); set_gdbarch_long_long_bit (gdbarch, 64); + set_gdbarch_wchar_bit (gdbarch, 64); + set_gdbarch_wchar_signed (gdbarch, 0); set_gdbarch_float_bit (gdbarch, 32); set_gdbarch_double_bit (gdbarch, 64); set_gdbarch_long_double_bit (gdbarch, 64); @@ -1723,9 +1800,6 @@ alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) /* Prologue heuristics. */ set_gdbarch_skip_prologue (gdbarch, alpha_skip_prologue); - /* Disassembler. */ - set_gdbarch_print_insn (gdbarch, print_insn_alpha); - /* Call info. */ set_gdbarch_return_value (gdbarch, alpha_return_value); @@ -1742,10 +1816,16 @@ alpha_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_inner_than (gdbarch, core_addr_lessthan); set_gdbarch_skip_trampoline_code (gdbarch, find_solib_trampoline_target); - set_gdbarch_breakpoint_from_pc (gdbarch, alpha_breakpoint_from_pc); + set_gdbarch_breakpoint_kind_from_pc (gdbarch, + alpha_breakpoint::kind_from_pc); + set_gdbarch_sw_breakpoint_from_kind (gdbarch, + alpha_breakpoint::bp_from_kind); set_gdbarch_decr_pc_after_break (gdbarch, ALPHA_INSN_SIZE); set_gdbarch_cannot_step_breakpoint (gdbarch, 1); + /* Handles single stepping of atomic sequences. */ + set_gdbarch_software_single_step (gdbarch, alpha_deal_with_atomic_sequence); + /* Hook in ABI-specific overrides, if they have been registered. */ gdbarch_init_osabi (info, gdbarch); @@ -1775,7 +1855,6 @@ extern initialize_file_ftype _initialize_alpha_tdep; /* -Wmissing-prototypes */ void _initialize_alpha_tdep (void) { - struct cmd_list_element *c; gdbarch_register (bfd_arch_alpha, alpha_gdbarch_init, NULL);