X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gdb%2Famd64-tdep.h;h=44c1250cb915cfce71ee15ded244069ac9c5adb2;hb=a350efd4fb368a35ada608f6bc26ccd3bed0ae6b;hp=d4c6c9aeaab7b71e8bbc892ca7236664e121a970;hpb=c55a47e7237ebac17df73183d214d90400a49455;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/amd64-tdep.h b/gdb/amd64-tdep.h index d4c6c9aeaa..44c1250cb9 100644 --- a/gdb/amd64-tdep.h +++ b/gdb/amd64-tdep.h @@ -1,6 +1,6 @@ /* Target-dependent definitions for AMD64. - Copyright (C) 2001-2017 Free Software Foundation, Inc. + Copyright (C) 2001-2020 Free Software Foundation, Inc. Contributed by Jiri Smid, SuSE Labs. This file is part of GDB. @@ -26,6 +26,7 @@ struct frame_info; struct regcache; #include "i386-tdep.h" +#include "infrun.h" /* Register numbers of various important registers. */ @@ -87,10 +88,7 @@ enum amd64_regnum #define AMD64_NUM_REGS (AMD64_GSBASE_REGNUM + 1) -extern struct target_desc *tdesc_amd64; -extern struct target_desc *tdesc_x32; - -extern struct displaced_step_closure *amd64_displaced_step_copy_insn +extern displaced_step_closure_up amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, CORE_ADDR from, CORE_ADDR to, struct regcache *regs); extern void amd64_displaced_step_fixup (struct gdbarch *gdbarch, @@ -102,14 +100,15 @@ extern void amd64_displaced_step_fixup (struct gdbarch *gdbarch, tdesc, if INFO does not specify one. */ extern void amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch, - target_desc *default_tdesc); + const target_desc *default_tdesc); /* Initialize the ABI for x32. Uses DEFAULT_TDESC as fallback tdesc, if INFO does not specify one. */ extern void amd64_x32_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch, - target_desc *default_tdesc); -extern const struct target_desc *amd64_target_description (uint64_t xcr0); + const target_desc *default_tdesc); +extern const struct target_desc *amd64_target_description (uint64_t xcr0, + bool segments); /* Fill register REGNUM in REGCACHE with the appropriate floating-point or SSE register value from *FXSAVE. If REGNUM is