X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gdb%2Farm-tdep.c;h=8e9552a1e19d06784e5d48e15df064d5e061e196;hb=df25ebbd091aebc132f97ffd6ce9cf7964a57981;hp=0e7d9c2f872e17f1068c1c16e87ad2ddc3d22305;hpb=540314bdd87c7478d21b44dd4856d937bcc1479b;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 0e7d9c2f87..8e9552a1e1 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -1,6 +1,6 @@ /* Common target dependent code for GDB on ARM systems. - Copyright (C) 1988-2014 Free Software Foundation, Inc. + Copyright (C) 1988-2015 Free Software Foundation, Inc. This file is part of GDB. @@ -26,7 +26,6 @@ #include "infrun.h" #include "gdbcmd.h" #include "gdbcore.h" -#include #include "dis-asm.h" /* For register styles. */ #include "regcache.h" #include "reggroups.h" @@ -53,7 +52,6 @@ #include "coff/internal.h" #include "elf/arm.h" -#include "gdb_assert.h" #include "vec.h" #include "record.h" @@ -754,6 +752,11 @@ thumb_analyze_prologue (struct gdbarch *gdbarch, regs[ARM_SP_REGNUM] = pv_add_constant (regs[ARM_SP_REGNUM], -offset); } + else if (thumb_instruction_restores_sp (insn)) + { + /* Don't scan past the epilogue. */ + break; + } else if ((insn & 0xf800) == 0xa800) /* add Rd, sp, #imm */ regs[bits (insn, 8, 10)] = pv_add_constant (regs[ARM_SP_REGNUM], (insn & 0xff) << 2); @@ -1201,7 +1204,9 @@ arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, { *destreg = bits (insn1, 8, 10); *offset = 2; - address = bits (insn1, 0, 7); + address = (pc & 0xfffffffc) + 4 + (bits (insn1, 0, 7) << 2); + address = read_memory_unsigned_integer (address, 4, + byte_order_for_code); } else if ((insn1 & 0xfbf0) == 0xf240) /* movw Rd, #const */ { @@ -1230,9 +1235,12 @@ arm_analyze_load_stack_chk_guard(CORE_ADDR pc, struct gdbarch *gdbarch, unsigned int insn = read_memory_unsigned_integer (pc, 4, byte_order_for_code); - if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, #immed */ + if ((insn & 0x0e5f0000) == 0x041f0000) /* ldr Rd, [PC, #immed] */ { - address = bits (insn, 0, 11); + address = bits (insn, 0, 11) + pc + 8; + address = read_memory_unsigned_integer (address, 4, + byte_order_for_code); + *destreg = bits (insn, 12, 15); *offset = 4; } @@ -1303,11 +1311,10 @@ arm_skip_stack_protector(CORE_ADDR pc, struct gdbarch *gdbarch) return pc; stack_chk_guard = lookup_minimal_symbol_by_pc (addr); - /* If name of symbol doesn't start with '__stack_chk_guard', this - instruction sequence is not for stack protector. If symbol is - removed, we conservatively think this sequence is for stack protector. */ - if (stack_chk_guard.minsym - && strncmp (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym), + /* ADDR must correspond to a symbol whose name is __stack_chk_guard. + Otherwise, this sequence cannot be for stack protector. */ + if (stack_chk_guard.minsym == NULL + || strncmp (MSYMBOL_LINKAGE_NAME (stack_chk_guard.minsym), "__stack_chk_guard", strlen ("__stack_chk_guard")) != 0) return pc; @@ -1381,7 +1388,6 @@ arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) { enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); unsigned long inst; - CORE_ADDR skip_pc; CORE_ADDR func_addr, limit_pc; /* See if we can determine the end of the prologue via the symbol table. @@ -1391,7 +1397,7 @@ arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) { CORE_ADDR post_prologue_pc = skip_prologue_using_sal (gdbarch, func_addr); - struct symtab *s = find_pc_symtab (func_addr); + struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr); if (post_prologue_pc) post_prologue_pc @@ -1405,10 +1411,12 @@ arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) will have producer information for most binaries; if it is missing (e.g. for -gstabs), assuming the GNU tools. */ if (post_prologue_pc - && (s == NULL - || s->producer == NULL - || strncmp (s->producer, "GNU ", sizeof ("GNU ") - 1) == 0 - || strncmp (s->producer, "clang ", sizeof ("clang ") - 1) == 0)) + && (cust == NULL + || COMPUNIT_PRODUCER (cust) == NULL + || strncmp (COMPUNIT_PRODUCER (cust), "GNU ", + sizeof ("GNU ") - 1) == 0 + || strncmp (COMPUNIT_PRODUCER (cust), "clang ", + sizeof ("clang ") - 1) == 0)) return post_prologue_pc; if (post_prologue_pc != 0) @@ -1453,65 +1461,8 @@ arm_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) /* Check if this is Thumb code. */ if (arm_pc_is_thumb (gdbarch, pc)) return thumb_analyze_prologue (gdbarch, pc, limit_pc, NULL); - - for (skip_pc = pc; skip_pc < limit_pc; skip_pc += 4) - { - inst = read_memory_unsigned_integer (skip_pc, 4, byte_order_for_code); - - /* "mov ip, sp" is no longer a required part of the prologue. */ - if (inst == 0xe1a0c00d) /* mov ip, sp */ - continue; - - if ((inst & 0xfffff000) == 0xe28dc000) /* add ip, sp #n */ - continue; - - if ((inst & 0xfffff000) == 0xe24dc000) /* sub ip, sp #n */ - continue; - - /* Some prologues begin with "str lr, [sp, #-4]!". */ - if (inst == 0xe52de004) /* str lr, [sp, #-4]! */ - continue; - - if ((inst & 0xfffffff0) == 0xe92d0000) /* stmfd sp!,{a1,a2,a3,a4} */ - continue; - - if ((inst & 0xfffff800) == 0xe92dd800) /* stmfd sp!,{fp,ip,lr,pc} */ - continue; - - /* Any insns after this point may float into the code, if it makes - for better instruction scheduling, so we skip them only if we - find them, but still consider the function to be frame-ful. */ - - /* We may have either one sfmfd instruction here, or several stfe - insns, depending on the version of floating point code we - support. */ - if ((inst & 0xffbf0fff) == 0xec2d0200) /* sfmfd fn, , [sp]! */ - continue; - - if ((inst & 0xffff8fff) == 0xed6d0103) /* stfe fn, [sp, #-12]! */ - continue; - - if ((inst & 0xfffff000) == 0xe24cb000) /* sub fp, ip, #nn */ - continue; - - if ((inst & 0xfffff000) == 0xe24dd000) /* sub sp, sp, #nn */ - continue; - - if ((inst & 0xffffc000) == 0xe54b0000 /* strb r(0123),[r11,#-nn] */ - || (inst & 0xffffc0f0) == 0xe14b00b0 /* strh r(0123),[r11,#-nn] */ - || (inst & 0xffffc000) == 0xe50b0000) /* str r(0123),[r11,#-nn] */ - continue; - - if ((inst & 0xffffc000) == 0xe5cd0000 /* strb r(0123),[sp,#nn] */ - || (inst & 0xffffc0f0) == 0xe1cd00b0 /* strh r(0123),[sp,#nn] */ - || (inst & 0xffffc000) == 0xe58d0000) /* str r(0123),[sp,#nn] */ - continue; - - /* Un-recognized instruction; stop scanning. */ - break; - } - - return skip_pc; /* End of prologue. */ + else + return arm_analyze_prologue (gdbarch, pc, limit_pc, NULL); } /* *INDENT-OFF* */ @@ -1655,6 +1606,30 @@ arm_instruction_changes_pc (uint32_t this_instr) } } +/* Return 1 if the ARM instruction INSN restores SP in epilogue, 0 + otherwise. */ + +static int +arm_instruction_restores_sp (unsigned int insn) +{ + if (bits (insn, 28, 31) != INST_NV) + { + if ((insn & 0x0df0f000) == 0x0080d000 + /* ADD SP (register or immediate). */ + || (insn & 0x0df0f000) == 0x0040d000 + /* SUB SP (register or immediate). */ + || (insn & 0x0ffffff0) == 0x01a0d000 + /* MOV SP. */ + || (insn & 0x0fff0000) == 0x08bd0000 + /* POP (LDMIA). */ + || (insn & 0x0fff0000) == 0x049d0000) + /* POP of a single register. */ + return 1; + } + + return 0; +} + /* Analyze an ARM mode prologue starting at PROLOGUE_START and continuing no further than PROLOGUE_END. If CACHE is non-NULL, fill it in. Return the first address not recognized as a prologue @@ -1677,7 +1652,6 @@ arm_analyze_prologue (struct gdbarch *gdbarch, pv_t regs[ARM_FPS_REGNUM]; struct pv_area *stack; struct cleanup *back_to; - int framereg, framesize; CORE_ADDR unrecognized_pc = 0; /* Search the prologue looking for instructions that set up the @@ -1853,6 +1827,11 @@ arm_analyze_prologue (struct gdbarch *gdbarch, else if (arm_instruction_changes_pc (insn)) /* Don't scan past anything that might change control flow. */ break; + else if (arm_instruction_restores_sp (insn)) + { + /* Don't scan past the epilogue. */ + break; + } else if ((insn & 0xfe500000) == 0xe8100000 /* ldm */ && pv_is_register (regs[bits (insn, 16, 19)], ARM_SP_REGNUM)) /* Ignore block loads from the stack, potentially copying @@ -1868,33 +1847,42 @@ arm_analyze_prologue (struct gdbarch *gdbarch, continue; else { - /* The optimizer might shove anything into the prologue, - so we just skip what we don't recognize. */ + /* The optimizer might shove anything into the prologue, if + we build up cache (cache != NULL) from scanning prologue, + we just skip what we don't recognize and scan further to + make cache as complete as possible. However, if we skip + prologue, we'll stop immediately on unrecognized + instruction. */ unrecognized_pc = current_pc; - continue; + if (cache != NULL) + continue; + else + break; } } if (unrecognized_pc == 0) unrecognized_pc = current_pc; - /* The frame size is just the distance from the frame register - to the original stack pointer. */ - if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) - { - /* Frame pointer is fp. */ - framereg = ARM_FP_REGNUM; - framesize = -regs[ARM_FP_REGNUM].k; - } - else - { - /* Try the stack pointer... this is a bit desperate. */ - framereg = ARM_SP_REGNUM; - framesize = -regs[ARM_SP_REGNUM].k; - } - if (cache) { + int framereg, framesize; + + /* The frame size is just the distance from the frame register + to the original stack pointer. */ + if (pv_is_register (regs[ARM_FP_REGNUM], ARM_SP_REGNUM)) + { + /* Frame pointer is fp. */ + framereg = ARM_FP_REGNUM; + framesize = -regs[ARM_FP_REGNUM].k; + } + else + { + /* Try the stack pointer... this is a bit desperate. */ + framereg = ARM_SP_REGNUM; + framesize = -regs[ARM_SP_REGNUM].k; + } + cache->framereg = framereg; cache->framesize = framesize; @@ -3270,8 +3258,7 @@ thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) found_return = 1; else if (thumb_instruction_restores_sp (insn)) { - found_stack_adjust = 1; - if ((insn & 0xfe00) == 0xbd00) /* pop */ + if ((insn & 0xff00) == 0xbd00) /* pop */ found_return = 1; } else if (thumb_insn_size (insn) == 4) /* 32-bit Thumb-2 instruction */ @@ -3284,20 +3271,18 @@ thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) if (insn == 0xe8bd) /* ldm.w sp!, */ { - found_stack_adjust = 1; if (insn2 & 0x8000) /* include PC. */ found_return = 1; } else if (insn == 0xf85d /* ldr.w , [sp], #4 */ && (insn2 & 0x0fff) == 0x0b04) { - found_stack_adjust = 1; if ((insn2 & 0xf000) == 0xf000) /* is PC. */ found_return = 1; } else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, */ && (insn2 & 0x0e00) == 0x0a00) - found_stack_adjust = 1; + ; else break; } @@ -3314,27 +3299,24 @@ thumb_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) a 32-bit instruction. This is just a heuristic, so we do not worry too much about false positives. */ - if (!found_stack_adjust) - { - if (pc - 4 < func_start) - return 0; - if (target_read_memory (pc - 4, buf, 4)) - return 0; + if (pc - 4 < func_start) + return 0; + if (target_read_memory (pc - 4, buf, 4)) + return 0; - insn = extract_unsigned_integer (buf, 2, byte_order_for_code); - insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code); + insn = extract_unsigned_integer (buf, 2, byte_order_for_code); + insn2 = extract_unsigned_integer (buf + 2, 2, byte_order_for_code); - if (thumb_instruction_restores_sp (insn2)) - found_stack_adjust = 1; - else if (insn == 0xe8bd) /* ldm.w sp!, */ - found_stack_adjust = 1; - else if (insn == 0xf85d /* ldr.w , [sp], #4 */ - && (insn2 & 0x0fff) == 0x0b04) - found_stack_adjust = 1; - else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, */ - && (insn2 & 0x0e00) == 0x0a00) - found_stack_adjust = 1; - } + if (thumb_instruction_restores_sp (insn2)) + found_stack_adjust = 1; + else if (insn == 0xe8bd) /* ldm.w sp!, */ + found_stack_adjust = 1; + else if (insn == 0xf85d /* ldr.w , [sp], #4 */ + && (insn2 & 0x0fff) == 0x0b04) + found_stack_adjust = 1; + else if ((insn & 0xffbf) == 0xecbd /* vldm sp!, */ + && (insn2 & 0x0e00) == 0x0a00) + found_stack_adjust = 1; return found_stack_adjust; } @@ -3347,7 +3329,7 @@ arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) { enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); unsigned int insn; - int found_return, found_stack_adjust; + int found_return; CORE_ADDR func_start, func_end; if (arm_pc_is_thumb (gdbarch, pc)) @@ -3387,28 +3369,8 @@ arm_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) if (pc < func_start + 4) return 0; - found_stack_adjust = 0; insn = read_memory_unsigned_integer (pc - 4, 4, byte_order_for_code); - if (bits (insn, 28, 31) != INST_NV) - { - if ((insn & 0x0df0f000) == 0x0080d000) - /* ADD SP (register or immediate). */ - found_stack_adjust = 1; - else if ((insn & 0x0df0f000) == 0x0040d000) - /* SUB SP (register or immediate). */ - found_stack_adjust = 1; - else if ((insn & 0x0ffffff0) == 0x01a0d000) - /* MOV SP. */ - found_stack_adjust = 1; - else if ((insn & 0x0fff0000) == 0x08bd0000) - /* POP (LDMIA). */ - found_stack_adjust = 1; - else if ((insn & 0x0fff0000) == 0x049d0000) - /* POP of a single register. */ - found_stack_adjust = 1; - } - - if (found_stack_adjust) + if (arm_instruction_restores_sp (insn)) return 1; return 0; @@ -3559,8 +3521,8 @@ arm_vfp_cprc_reg_char (enum arm_vfp_cprc_base_type b) classified from *BASE_TYPE, or two types differently classified from each other, return -1, otherwise return the total number of base-type elements found (possibly 0 in an empty structure or - array). Vectors and complex types are not currently supported, - matching the generic AAPCS support. */ + array). Vector types are not currently supported, matching the + generic AAPCS support. */ static int arm_vfp_cprc_sub_candidate (struct type *t, @@ -3591,6 +3553,38 @@ arm_vfp_cprc_sub_candidate (struct type *t, } break; + case TYPE_CODE_COMPLEX: + /* Arguments of complex T where T is one of the types float or + double get treated as if they are implemented as: + + struct complexT + { + T real; + T imag; + }; + + */ + switch (TYPE_LENGTH (t)) + { + case 8: + if (*base_type == VFP_CPRC_UNKNOWN) + *base_type = VFP_CPRC_SINGLE; + else if (*base_type != VFP_CPRC_SINGLE) + return -1; + return 2; + + case 16: + if (*base_type == VFP_CPRC_UNKNOWN) + *base_type = VFP_CPRC_DOUBLE; + else if (*base_type != VFP_CPRC_DOUBLE) + return -1; + return 2; + + default: + return -1; + } + break; + case TYPE_CODE_ARRAY: { int count; @@ -9974,27 +9968,34 @@ arm_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) OBJ_ATTR_PROC, Tag_ABI_VFP_args)) { - case 0: + case AEABI_VFP_args_base: /* "The user intended FP parameter/result passing to conform to AAPCS, base variant". */ fp_model = ARM_FLOAT_SOFT_VFP; break; - case 1: + case AEABI_VFP_args_vfp: /* "The user intended FP parameter/result passing to conform to AAPCS, VFP variant". */ fp_model = ARM_FLOAT_VFP; break; - case 2: + case AEABI_VFP_args_toolchain: /* "The user intended FP parameter/result passing to conform to tool chain-specific conventions" - we don't know any such conventions, so leave it as "auto". */ break; + case AEABI_VFP_args_compatible: + /* "Code is compatible with both the base + and VFP variants; the user did not permit + non-variadic functions to pass FP + parameters/results" - leave it as + "auto". */ + break; default: /* Attribute value not mentioned in the - October 2008 ABI, so leave it as + November 2012 ABI, so leave it as "auto". */ break; } @@ -10647,6 +10648,8 @@ vfp - VFP co-processor."), #define THUMB2_INSN_SIZE_BYTES 4 +/* Position of the bit within a 32-bit ARM instruction + that defines whether the instruction is a load or store. */ #define INSN_S_L_BIT_NUM 20 #define REG_ALLOC(REGS, LENGTH, RECORD_BUF) \ @@ -11444,110 +11447,90 @@ arm_record_data_proc_imm (insn_decode_record *arm_insn_r) return 0; } -/* Handling opcode 010 insns. */ +/* Handle ARM mode instructions with opcode 010. */ static int arm_record_ld_st_imm_offset (insn_decode_record *arm_insn_r) { struct regcache *reg_cache = arm_insn_r->regcache; - uint32_t reg_src1 = 0 , reg_dest = 0; - uint32_t offset_12 = 0, tgt_mem_addr = 0; + uint32_t reg_base , reg_dest; + uint32_t offset_12, tgt_mem_addr; uint32_t record_buf[8], record_buf_mem[8]; + unsigned char wback; + ULONGEST u_regval; - ULONGEST u_regval = 0; + /* Calculate wback. */ + wback = (bit (arm_insn_r->arm_insn, 24) == 0) + || (bit (arm_insn_r->arm_insn, 21) == 1); - arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 21, 24); - arm_insn_r->decode = bits (arm_insn_r->arm_insn, 4, 7); + arm_insn_r->reg_rec_count = 0; + reg_base = bits (arm_insn_r->arm_insn, 16, 19); if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) { + /* LDR (immediate), LDR (literal), LDRB (immediate), LDRB (literal), LDRBT + and LDRT. */ + reg_dest = bits (arm_insn_r->arm_insn, 12, 15); - /* LDR insn has a capability to do branching, if - MOV LR, PC is precedded by LDR insn having Rn as R15 - in that case, it emulates branch and link insn, and hence we - need to save CSPR and PC as well. */ - if (ARM_PC_REGNUM != reg_dest) - { - record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); - arm_insn_r->reg_rec_count = 1; - } - else - { - record_buf[0] = reg_dest; - record_buf[1] = ARM_PS_REGNUM; - arm_insn_r->reg_rec_count = 2; - } + record_buf[arm_insn_r->reg_rec_count++] = reg_dest; + + /* The LDR instruction is capable of doing branching. If MOV LR, PC + preceeds a LDR instruction having R15 as reg_base, it + emulates a branch and link instruction, and hence we need to save + CPSR and PC as well. */ + if (ARM_PC_REGNUM == reg_dest) + record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; + + /* If wback is true, also save the base register, which is going to be + written to. */ + if (wback) + record_buf[arm_insn_r->reg_rec_count++] = reg_base; } else { - /* Store, immediate offset, immediate pre-indexed, - immediate post-indexed. */ - reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); + /* STR (immediate), STRB (immediate), STRBT and STRT. */ + offset_12 = bits (arm_insn_r->arm_insn, 0, 11); - regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval); - /* U == 1 */ + regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); + + /* Handle bit U. */ if (bit (arm_insn_r->arm_insn, 23)) - { - tgt_mem_addr = u_regval + offset_12; - } + { + /* U == 1: Add the offset. */ + tgt_mem_addr = (uint32_t) u_regval + offset_12; + } else - { - tgt_mem_addr = u_regval - offset_12; - } + { + /* U == 0: subtract the offset. */ + tgt_mem_addr = (uint32_t) u_regval - offset_12; + } + + /* Bit 22 tells us whether the store instruction writes 1 byte or 4 + bytes. */ + if (bit (arm_insn_r->arm_insn, 22)) + { + /* STRB and STRBT: 1 byte. */ + record_buf_mem[0] = 1; + } + else + { + /* STR and STRT: 4 bytes. */ + record_buf_mem[0] = 4; + } + + /* Handle bit P. */ + if (bit (arm_insn_r->arm_insn, 24)) + record_buf_mem[1] = tgt_mem_addr; + else + record_buf_mem[1] = (uint32_t) u_regval; - switch (arm_insn_r->opcode) - { - /* STR. */ - case 8: - case 12: - /* STR. */ - case 9: - case 13: - /* STRT. */ - case 1: - case 5: - /* STR. */ - case 4: - case 0: - record_buf_mem[0] = 4; - break; - - /* STRB. */ - case 10: - case 14: - /* STRB. */ - case 11: - case 15: - /* STRBT. */ - case 3: - case 7: - /* STRB. */ - case 2: - case 6: - record_buf_mem[0] = 1; - break; - - default: - gdb_assert_not_reached ("no decoding pattern found"); - break; - } - record_buf_mem[1] = tgt_mem_addr; arm_insn_r->mem_rec_count = 1; - if (9 == arm_insn_r->opcode || 11 == arm_insn_r->opcode - || 13 == arm_insn_r->opcode || 15 == arm_insn_r->opcode - || 0 == arm_insn_r->opcode || 2 == arm_insn_r->opcode - || 4 == arm_insn_r->opcode || 6 == arm_insn_r->opcode - || 1 == arm_insn_r->opcode || 3 == arm_insn_r->opcode - || 5 == arm_insn_r->opcode || 7 == arm_insn_r->opcode - ) - { - /* We are handling pre-indexed mode; post-indexed mode; - where Rn is going to be changed. */ - record_buf[0] = reg_src1; - arm_insn_r->reg_rec_count = 1; - } + /* If wback is true, also save the base register, which is going to be + written to. */ + if (wback) + record_buf[arm_insn_r->reg_rec_count++] = reg_base; } REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); @@ -11818,134 +11801,99 @@ arm_record_ld_st_reg_offset (insn_decode_record *arm_insn_r) return 0; } -/* Handling opcode 100 insns. */ +/* Handle ARM mode instructions with opcode 100. */ static int arm_record_ld_st_multiple (insn_decode_record *arm_insn_r) { struct regcache *reg_cache = arm_insn_r->regcache; - - uint32_t register_list[16] = {0}, register_count = 0, register_bits = 0; - uint32_t reg_src1 = 0, addr_mode = 0, no_of_regs = 0; - uint32_t start_address = 0, index = 0; + uint32_t register_count = 0, register_bits; + uint32_t reg_base, addr_mode; uint32_t record_buf[24], record_buf_mem[48]; + uint32_t wback; + ULONGEST u_regval; - ULONGEST u_regval[2] = {0}; + /* Fetch the list of registers. */ + register_bits = bits (arm_insn_r->arm_insn, 0, 15); + arm_insn_r->reg_rec_count = 0; - /* This mode is exclusively for load and store multiple. */ - /* Handle incremenrt after/before and decrment after.before mode; - Rn is changing depending on W bit, but as of now we store Rn too - without optimization. */ + /* Fetch the base register that contains the address we are loading data + to. */ + reg_base = bits (arm_insn_r->arm_insn, 16, 19); + + /* Calculate wback. */ + wback = (bit (arm_insn_r->arm_insn, 21) == 1); if (bit (arm_insn_r->arm_insn, INSN_S_L_BIT_NUM)) { - /* LDM (1,2,3) where LDM (3) changes CPSR too. */ + /* LDM/LDMIA/LDMFD, LDMDA/LDMFA, LDMDB and LDMIB. */ - if (bit (arm_insn_r->arm_insn, 20) && !bit (arm_insn_r->arm_insn, 22)) - { - register_bits = bits (arm_insn_r->arm_insn, 0, 15); - no_of_regs = 15; - } - else - { - register_bits = bits (arm_insn_r->arm_insn, 0, 14); - no_of_regs = 14; - } - /* Get Rn. */ - reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); + /* Find out which registers are going to be loaded from memory. */ while (register_bits) - { - if (register_bits & 0x00000001) - record_buf[index++] = register_count; - register_bits = register_bits >> 1; - register_count++; - } + { + if (register_bits & 0x00000001) + record_buf[arm_insn_r->reg_rec_count++] = register_count; + register_bits = register_bits >> 1; + register_count++; + } + + + /* If wback is true, also save the base register, which is going to be + written to. */ + if (wback) + record_buf[arm_insn_r->reg_rec_count++] = reg_base; - /* Extra space for Base Register and CPSR; wihtout optimization. */ - record_buf[index++] = reg_src1; - record_buf[index++] = ARM_PS_REGNUM; - arm_insn_r->reg_rec_count = index; + /* Save the CPSR register. */ + record_buf[arm_insn_r->reg_rec_count++] = ARM_PS_REGNUM; } else { - /* It handles both STM(1) and STM(2). */ - addr_mode = bits (arm_insn_r->arm_insn, 23, 24); + /* STM (STMIA, STMEA), STMDA (STMED), STMDB (STMFD) and STMIB (STMFA). */ - register_bits = bits (arm_insn_r->arm_insn, 0, 15); - /* Get Rn. */ - reg_src1 = bits (arm_insn_r->arm_insn, 16, 19); - regcache_raw_read_unsigned (reg_cache, reg_src1, &u_regval[0]); + addr_mode = bits (arm_insn_r->arm_insn, 23, 24); + + regcache_raw_read_unsigned (reg_cache, reg_base, &u_regval); + + /* Find out how many registers are going to be stored to memory. */ while (register_bits) - { - if (register_bits & 0x00000001) - register_count++; - register_bits = register_bits >> 1; - } + { + if (register_bits & 0x00000001) + register_count++; + register_bits = register_bits >> 1; + } switch (addr_mode) - { - /* Decrement after. */ - case 0: - start_address = (u_regval[0]) - (register_count * 4) + 4; - arm_insn_r->mem_rec_count = register_count; - while (register_count) - { - record_buf_mem[(register_count * 2) - 1] = start_address; - record_buf_mem[(register_count * 2) - 2] = 4; - start_address = start_address + 4; - register_count--; - } - break; - - /* Increment after. */ - case 1: - start_address = u_regval[0]; - arm_insn_r->mem_rec_count = register_count; - while (register_count) - { - record_buf_mem[(register_count * 2) - 1] = start_address; - record_buf_mem[(register_count * 2) - 2] = 4; - start_address = start_address + 4; - register_count--; - } - break; - - /* Decrement before. */ - case 2: - - start_address = (u_regval[0]) - (register_count * 4); - arm_insn_r->mem_rec_count = register_count; - while (register_count) - { - record_buf_mem[(register_count * 2) - 1] = start_address; - record_buf_mem[(register_count * 2) - 2] = 4; - start_address = start_address + 4; - register_count--; - } - break; - - /* Increment before. */ - case 3: - start_address = u_regval[0] + 4; - arm_insn_r->mem_rec_count = register_count; - while (register_count) - { - record_buf_mem[(register_count * 2) - 1] = start_address; - record_buf_mem[(register_count * 2) - 2] = 4; - start_address = start_address + 4; - register_count--; - } - break; - - default: - gdb_assert_not_reached ("no decoding pattern found"); - break; - } + { + /* STMDA (STMED): Decrement after. */ + case 0: + record_buf_mem[1] = (uint32_t) u_regval + - register_count * INT_REGISTER_SIZE + 4; + break; + /* STM (STMIA, STMEA): Increment after. */ + case 1: + record_buf_mem[1] = (uint32_t) u_regval; + break; + /* STMDB (STMFD): Decrement before. */ + case 2: + record_buf_mem[1] = (uint32_t) u_regval + - register_count * INT_REGISTER_SIZE; + break; + /* STMIB (STMFA): Increment before. */ + case 3: + record_buf_mem[1] = (uint32_t) u_regval + INT_REGISTER_SIZE; + break; + default: + gdb_assert_not_reached ("no decoding pattern found"); + break; + } - /* Base register also changes; based on condition and W bit. */ - /* We save it anyway without optimization. */ - record_buf[0] = reg_src1; - arm_insn_r->reg_rec_count = 1; + record_buf_mem[0] = register_count * INT_REGISTER_SIZE; + arm_insn_r->mem_rec_count = 1; + + /* If wback is true, also save the base register, which is going to be + written to. */ + if (wback) + record_buf[arm_insn_r->reg_rec_count++] = reg_base; } REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); @@ -11987,50 +11935,620 @@ arm_record_unsupported_insn (insn_decode_record *arm_insn_r) return -1; } -/* Handling opcode 111 insns. */ +/* Record handler for vector data transfer instructions. */ static int -arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) +arm_record_vdata_transfer_insn (insn_decode_record *arm_insn_r) { - struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch); - struct regcache *reg_cache = arm_insn_r->regcache; - uint32_t ret = 0; /* function return value: -1:record failure ; 0:success */ - ULONGEST u_regval = 0; + uint32_t bits_a, bit_c, bit_l, reg_t, reg_v; + uint32_t record_buf[4]; - arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); + const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); + reg_t = bits (arm_insn_r->arm_insn, 12, 15); + reg_v = bits (arm_insn_r->arm_insn, 21, 23); + bits_a = bits (arm_insn_r->arm_insn, 21, 23); + bit_l = bit (arm_insn_r->arm_insn, 20); + bit_c = bit (arm_insn_r->arm_insn, 8); - /* Handle arm SWI/SVC system call instructions. */ - if (15 == arm_insn_r->opcode) + /* Handle VMOV instruction. */ + if (bit_l && bit_c) { - if (tdep->arm_syscall_record != NULL) + record_buf[0] = reg_t; + arm_insn_r->reg_rec_count = 1; + } + else if (bit_l && !bit_c) + { + /* Handle VMOV instruction. */ + if (bits_a == 0x00) { - ULONGEST svc_operand, svc_number; + if (bit (arm_insn_r->arm_insn, 20)) + record_buf[0] = reg_t; + else + record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | + (reg_v << 1)); - svc_operand = (0x00ffffff & arm_insn_r->arm_insn); + arm_insn_r->reg_rec_count = 1; + } + /* Handle VMRS instruction. */ + else if (bits_a == 0x07) + { + if (reg_t == 15) + reg_t = ARM_PS_REGNUM; - if (svc_operand) /* OABI. */ - svc_number = svc_operand - 0x900000; - else /* EABI. */ - regcache_raw_read_unsigned (reg_cache, 7, &svc_number); + record_buf[0] = reg_t; + arm_insn_r->reg_rec_count = 1; + } + } + else if (!bit_l && !bit_c) + { + /* Handle VMOV instruction. */ + if (bits_a == 0x00) + { + if (bit (arm_insn_r->arm_insn, 20)) + record_buf[0] = reg_t; + else + record_buf[0] = num_regs + (bit (arm_insn_r->arm_insn, 7) | + (reg_v << 1)); - ret = tdep->arm_syscall_record (reg_cache, svc_number); + arm_insn_r->reg_rec_count = 1; } - else + /* Handle VMSR instruction. */ + else if (bits_a == 0x07) { - printf_unfiltered (_("no syscall record support\n")); - ret = -1; + record_buf[0] = ARM_FPSCR_REGNUM; + arm_insn_r->reg_rec_count = 1; } } - else + else if (!bit_l && bit_c) { - arm_record_unsupported_insn (arm_insn_r); - ret = -1; + /* Handle VMOV instruction. */ + if (!(bits_a & 0x04)) + { + record_buf[0] = (reg_v | (bit (arm_insn_r->arm_insn, 7) << 4)) + + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + } + /* Handle VDUP instruction. */ + else + { + if (bit (arm_insn_r->arm_insn, 21)) + { + reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); + record_buf[0] = reg_v + ARM_D0_REGNUM; + record_buf[1] = reg_v + ARM_D0_REGNUM + 1; + arm_insn_r->reg_rec_count = 2; + } + else + { + reg_v = reg_v | (bit (arm_insn_r->arm_insn, 7) << 4); + record_buf[0] = reg_v + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + } + } } - return ret; + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + return 0; } -/* Handling opcode 000 insns. */ +/* Record handler for extension register load/store instructions. */ + +static int +arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r) +{ + uint32_t opcode, single_reg; + uint8_t op_vldm_vstm; + uint32_t record_buf[8], record_buf_mem[128]; + ULONGEST u_regval = 0; + + struct regcache *reg_cache = arm_insn_r->regcache; + const int num_regs = gdbarch_num_regs (arm_insn_r->gdbarch); + + opcode = bits (arm_insn_r->arm_insn, 20, 24); + single_reg = bit (arm_insn_r->arm_insn, 8); + op_vldm_vstm = opcode & 0x1b; + + /* Handle VMOV instructions. */ + if ((opcode & 0x1e) == 0x04) + { + if (bit (arm_insn_r->arm_insn, 4)) + { + record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); + record_buf[1] = bits (arm_insn_r->arm_insn, 16, 19); + arm_insn_r->reg_rec_count = 2; + } + else + { + uint8_t reg_m = (bits (arm_insn_r->arm_insn, 0, 3) << 1) + | bit (arm_insn_r->arm_insn, 5); + + if (!single_reg) + { + record_buf[0] = num_regs + reg_m; + record_buf[1] = num_regs + reg_m + 1; + arm_insn_r->reg_rec_count = 2; + } + else + { + record_buf[0] = reg_m + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + } + } + } + /* Handle VSTM and VPUSH instructions. */ + else if (op_vldm_vstm == 0x08 || op_vldm_vstm == 0x0a + || op_vldm_vstm == 0x12) + { + uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; + uint32_t memory_index = 0; + + reg_rn = bits (arm_insn_r->arm_insn, 16, 19); + regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); + imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); + imm_off32 = imm_off8 << 24; + memory_count = imm_off8; + + if (bit (arm_insn_r->arm_insn, 23)) + start_address = u_regval; + else + start_address = u_regval - imm_off32; + + if (bit (arm_insn_r->arm_insn, 21)) + { + record_buf[0] = reg_rn; + arm_insn_r->reg_rec_count = 1; + } + + while (memory_count > 0) + { + if (!single_reg) + { + record_buf_mem[memory_index] = start_address; + record_buf_mem[memory_index + 1] = 4; + start_address = start_address + 4; + memory_index = memory_index + 2; + } + else + { + record_buf_mem[memory_index] = start_address; + record_buf_mem[memory_index + 1] = 4; + record_buf_mem[memory_index + 2] = start_address + 4; + record_buf_mem[memory_index + 3] = 4; + start_address = start_address + 8; + memory_index = memory_index + 4; + } + memory_count--; + } + arm_insn_r->mem_rec_count = (memory_index >> 1); + } + /* Handle VLDM instructions. */ + else if (op_vldm_vstm == 0x09 || op_vldm_vstm == 0x0b + || op_vldm_vstm == 0x13) + { + uint32_t reg_count, reg_vd; + uint32_t reg_index = 0; + + reg_vd = bits (arm_insn_r->arm_insn, 12, 15); + reg_count = bits (arm_insn_r->arm_insn, 0, 7); + + if (single_reg) + reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4); + else + reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); + + if (bit (arm_insn_r->arm_insn, 21)) + record_buf[reg_index++] = bits (arm_insn_r->arm_insn, 16, 19); + + while (reg_count > 0) + { + if (single_reg) + record_buf[reg_index++] = num_regs + reg_vd + reg_count - 1; + else + record_buf[reg_index++] = ARM_D0_REGNUM + reg_vd + reg_count - 1; + + reg_count--; + } + arm_insn_r->reg_rec_count = reg_index; + } + /* VSTR Vector store register. */ + else if ((opcode & 0x13) == 0x10) + { + uint32_t start_address, reg_rn, imm_off32, imm_off8, memory_count; + uint32_t memory_index = 0; + + reg_rn = bits (arm_insn_r->arm_insn, 16, 19); + regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); + imm_off8 = bits (arm_insn_r->arm_insn, 0, 7); + imm_off32 = imm_off8 << 24; + memory_count = imm_off8; + + if (bit (arm_insn_r->arm_insn, 23)) + start_address = u_regval + imm_off32; + else + start_address = u_regval - imm_off32; + + if (single_reg) + { + record_buf_mem[memory_index] = start_address; + record_buf_mem[memory_index + 1] = 4; + arm_insn_r->mem_rec_count = 1; + } + else + { + record_buf_mem[memory_index] = start_address; + record_buf_mem[memory_index + 1] = 4; + record_buf_mem[memory_index + 2] = start_address + 4; + record_buf_mem[memory_index + 3] = 4; + arm_insn_r->mem_rec_count = 2; + } + } + /* VLDR Vector load register. */ + else if ((opcode & 0x13) == 0x11) + { + uint32_t reg_vd = bits (arm_insn_r->arm_insn, 12, 15); + + if (!single_reg) + { + reg_vd = reg_vd | (bit (arm_insn_r->arm_insn, 22) << 4); + record_buf[0] = ARM_D0_REGNUM + reg_vd; + } + else + { + reg_vd = (reg_vd << 1) | bit (arm_insn_r->arm_insn, 22); + record_buf[0] = num_regs + reg_vd; + } + arm_insn_r->reg_rec_count = 1; + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + MEM_ALLOC (arm_insn_r->arm_mems, arm_insn_r->mem_rec_count, record_buf_mem); + return 0; +} + +/* Record handler for arm/thumb mode VFP data processing instructions. */ + +static int +arm_record_vfp_data_proc_insn (insn_decode_record *arm_insn_r) +{ + uint32_t opc1, opc2, opc3, dp_op_sz, bit_d, reg_vd; + uint32_t record_buf[4]; + enum insn_types {INSN_T0, INSN_T1, INSN_T2, INSN_T3, INSN_INV}; + enum insn_types curr_insn_type = INSN_INV; + + reg_vd = bits (arm_insn_r->arm_insn, 12, 15); + opc1 = bits (arm_insn_r->arm_insn, 20, 23); + opc2 = bits (arm_insn_r->arm_insn, 16, 19); + opc3 = bits (arm_insn_r->arm_insn, 6, 7); + dp_op_sz = bit (arm_insn_r->arm_insn, 8); + bit_d = bit (arm_insn_r->arm_insn, 22); + opc1 = opc1 & 0x04; + + /* Handle VMLA, VMLS. */ + if (opc1 == 0x00) + { + if (bit (arm_insn_r->arm_insn, 10)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VNMLA, VNMLS, VNMUL. */ + else if (opc1 == 0x01) + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + /* Handle VMUL. */ + else if (opc1 == 0x02 && !(opc3 & 0x01)) + { + if (bit (arm_insn_r->arm_insn, 10)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VADD, VSUB. */ + else if (opc1 == 0x03) + { + if (!bit (arm_insn_r->arm_insn, 9)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VDIV. */ + else if (opc1 == 0x0b) + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + /* Handle all other vfp data processing instructions. */ + else if (opc1 == 0x0b) + { + /* Handle VMOV. */ + if (!(opc3 & 0x01) || (opc2 == 0x00 && opc3 == 0x01)) + { + if (bit (arm_insn_r->arm_insn, 4)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VNEG and VABS. */ + else if ((opc2 == 0x01 && opc3 == 0x01) + || (opc2 == 0x00 && opc3 == 0x03)) + { + if (!bit (arm_insn_r->arm_insn, 11)) + { + if (bit (arm_insn_r->arm_insn, 6)) + curr_insn_type = INSN_T0; + else + curr_insn_type = INSN_T1; + } + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VSQRT. */ + else if (opc2 == 0x01 && opc3 == 0x03) + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + /* Handle VCVT. */ + else if (opc2 == 0x07 && opc3 == 0x03) + { + if (!dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + else if (opc3 & 0x01) + { + /* Handle VCVT. */ + if ((opc2 == 0x08) || (opc2 & 0x0e) == 0x0c) + { + if (!bit (arm_insn_r->arm_insn, 18)) + curr_insn_type = INSN_T2; + else + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + } + /* Handle VCVT. */ + else if ((opc2 & 0x0e) == 0x0a || (opc2 & 0x0e) == 0x0e) + { + if (dp_op_sz) + curr_insn_type = INSN_T1; + else + curr_insn_type = INSN_T2; + } + /* Handle VCVTB, VCVTT. */ + else if ((opc2 & 0x0e) == 0x02) + curr_insn_type = INSN_T2; + /* Handle VCMP, VCMPE. */ + else if ((opc2 & 0x0e) == 0x04) + curr_insn_type = INSN_T3; + } + } + + switch (curr_insn_type) + { + case INSN_T0: + reg_vd = reg_vd | (bit_d << 4); + record_buf[0] = reg_vd + ARM_D0_REGNUM; + record_buf[1] = reg_vd + ARM_D0_REGNUM + 1; + arm_insn_r->reg_rec_count = 2; + break; + + case INSN_T1: + reg_vd = reg_vd | (bit_d << 4); + record_buf[0] = reg_vd + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + break; + + case INSN_T2: + reg_vd = (reg_vd << 1) | bit_d; + record_buf[0] = reg_vd + ARM_D0_REGNUM; + arm_insn_r->reg_rec_count = 1; + break; + + case INSN_T3: + record_buf[0] = ARM_FPSCR_REGNUM; + arm_insn_r->reg_rec_count = 1; + break; + + default: + gdb_assert_not_reached ("no decoding pattern found"); + break; + } + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, record_buf); + return 0; +} + +/* Handling opcode 110 insns. */ + +static int +arm_record_asimd_vfp_coproc (insn_decode_record *arm_insn_r) +{ + uint32_t op, op1, op1_sbit, op1_ebit, coproc; + + coproc = bits (arm_insn_r->arm_insn, 8, 11); + op1 = bits (arm_insn_r->arm_insn, 20, 25); + op1_ebit = bit (arm_insn_r->arm_insn, 20); + + if ((coproc & 0x0e) == 0x0a) + { + /* Handle extension register ld/st instructions. */ + if (!(op1 & 0x20)) + return arm_record_exreg_ld_st_insn (arm_insn_r); + + /* 64-bit transfers between arm core and extension registers. */ + if ((op1 & 0x3e) == 0x04) + return arm_record_exreg_ld_st_insn (arm_insn_r); + } + else + { + /* Handle coprocessor ld/st instructions. */ + if (!(op1 & 0x3a)) + { + /* Store. */ + if (!op1_ebit) + return arm_record_unsupported_insn (arm_insn_r); + else + /* Load. */ + return arm_record_unsupported_insn (arm_insn_r); + } + + /* Move to coprocessor from two arm core registers. */ + if (op1 == 0x4) + return arm_record_unsupported_insn (arm_insn_r); + + /* Move to two arm core registers from coprocessor. */ + if (op1 == 0x5) + { + uint32_t reg_t[2]; + + reg_t[0] = bits (arm_insn_r->arm_insn, 12, 15); + reg_t[1] = bits (arm_insn_r->arm_insn, 16, 19); + arm_insn_r->reg_rec_count = 2; + + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, reg_t); + return 0; + } + } + return arm_record_unsupported_insn (arm_insn_r); +} + +/* Handling opcode 111 insns. */ + +static int +arm_record_coproc_data_proc (insn_decode_record *arm_insn_r) +{ + uint32_t op, op1_sbit, op1_ebit, coproc; + struct gdbarch_tdep *tdep = gdbarch_tdep (arm_insn_r->gdbarch); + struct regcache *reg_cache = arm_insn_r->regcache; + ULONGEST u_regval = 0; + + arm_insn_r->opcode = bits (arm_insn_r->arm_insn, 24, 27); + coproc = bits (arm_insn_r->arm_insn, 8, 11); + op1_sbit = bit (arm_insn_r->arm_insn, 24); + op1_ebit = bit (arm_insn_r->arm_insn, 20); + op = bit (arm_insn_r->arm_insn, 4); + + /* Handle arm SWI/SVC system call instructions. */ + if (op1_sbit) + { + if (tdep->arm_syscall_record != NULL) + { + ULONGEST svc_operand, svc_number; + + svc_operand = (0x00ffffff & arm_insn_r->arm_insn); + + if (svc_operand) /* OABI. */ + svc_number = svc_operand - 0x900000; + else /* EABI. */ + regcache_raw_read_unsigned (reg_cache, 7, &svc_number); + + return tdep->arm_syscall_record (reg_cache, svc_number); + } + else + { + printf_unfiltered (_("no syscall record support\n")); + return -1; + } + } + + if ((coproc & 0x0e) == 0x0a) + { + /* VFP data-processing instructions. */ + if (!op1_sbit && !op) + return arm_record_vfp_data_proc_insn (arm_insn_r); + + /* Advanced SIMD, VFP instructions. */ + if (!op1_sbit && op) + return arm_record_vdata_transfer_insn (arm_insn_r); + } + else + { + /* Coprocessor data operations. */ + if (!op1_sbit && !op) + return arm_record_unsupported_insn (arm_insn_r); + + /* Move to Coprocessor from ARM core register. */ + if (!op1_sbit && !op1_ebit && op) + return arm_record_unsupported_insn (arm_insn_r); + + /* Move to arm core register from coprocessor. */ + if (!op1_sbit && op1_ebit && op) + { + uint32_t record_buf[1]; + + record_buf[0] = bits (arm_insn_r->arm_insn, 12, 15); + if (record_buf[0] == 15) + record_buf[0] = ARM_PS_REGNUM; + + arm_insn_r->reg_rec_count = 1; + REG_ALLOC (arm_insn_r->arm_regs, arm_insn_r->reg_rec_count, + record_buf); + return 0; + } + } + + return arm_record_unsupported_insn (arm_insn_r); +} + +/* Handling opcode 000 insns. */ static int thumb_record_shift_add_sub (insn_decode_record *thumb_insn_r) @@ -12943,6 +13461,206 @@ thumb2_record_lmul_lmla_div (insn_decode_record *thumb2_insn_r) return ARM_RECORD_SUCCESS; } +/* Record handler for thumb32 coprocessor instructions. */ + +static int +thumb2_record_coproc_insn (insn_decode_record *thumb2_insn_r) +{ + if (bit (thumb2_insn_r->arm_insn, 25)) + return arm_record_coproc_data_proc (thumb2_insn_r); + else + return arm_record_asimd_vfp_coproc (thumb2_insn_r); +} + +/* Record handler for advance SIMD structure load/store instructions. */ + +static int +thumb2_record_asimd_struct_ld_st (insn_decode_record *thumb2_insn_r) +{ + struct regcache *reg_cache = thumb2_insn_r->regcache; + uint32_t l_bit, a_bit, b_bits; + uint32_t record_buf[128], record_buf_mem[128]; + uint32_t reg_rn, reg_vd, address, f_esize, f_elem; + uint32_t index_r = 0, index_e = 0, bf_regs = 0, index_m = 0, loop_t = 0; + uint8_t f_ebytes; + + l_bit = bit (thumb2_insn_r->arm_insn, 21); + a_bit = bit (thumb2_insn_r->arm_insn, 23); + b_bits = bits (thumb2_insn_r->arm_insn, 8, 11); + reg_rn = bits (thumb2_insn_r->arm_insn, 16, 19); + reg_vd = bits (thumb2_insn_r->arm_insn, 12, 15); + reg_vd = (bit (thumb2_insn_r->arm_insn, 22) << 4) | reg_vd; + f_ebytes = (1 << bits (thumb2_insn_r->arm_insn, 6, 7)); + f_esize = 8 * f_ebytes; + f_elem = 8 / f_ebytes; + + if (!l_bit) + { + ULONGEST u_regval = 0; + regcache_raw_read_unsigned (reg_cache, reg_rn, &u_regval); + address = u_regval; + + if (!a_bit) + { + /* Handle VST1. */ + if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) + { + if (b_bits == 0x07) + bf_regs = 1; + else if (b_bits == 0x0a) + bf_regs = 2; + else if (b_bits == 0x06) + bf_regs = 3; + else if (b_bits == 0x02) + bf_regs = 4; + else + bf_regs = 0; + + for (index_r = 0; index_r < bf_regs; index_r++) + { + for (index_e = 0; index_e < f_elem; index_e++) + { + record_buf_mem[index_m++] = f_ebytes; + record_buf_mem[index_m++] = address; + address = address + f_ebytes; + thumb2_insn_r->mem_rec_count += 1; + } + } + } + /* Handle VST2. */ + else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) + { + if (b_bits == 0x09 || b_bits == 0x08) + bf_regs = 1; + else if (b_bits == 0x03) + bf_regs = 2; + else + bf_regs = 0; + + for (index_r = 0; index_r < bf_regs; index_r++) + for (index_e = 0; index_e < f_elem; index_e++) + { + for (loop_t = 0; loop_t < 2; loop_t++) + { + record_buf_mem[index_m++] = f_ebytes; + record_buf_mem[index_m++] = address + (loop_t * f_ebytes); + thumb2_insn_r->mem_rec_count += 1; + } + address = address + (2 * f_ebytes); + } + } + /* Handle VST3. */ + else if ((b_bits & 0x0e) == 0x04) + { + for (index_e = 0; index_e < f_elem; index_e++) + { + for (loop_t = 0; loop_t < 3; loop_t++) + { + record_buf_mem[index_m++] = f_ebytes; + record_buf_mem[index_m++] = address + (loop_t * f_ebytes); + thumb2_insn_r->mem_rec_count += 1; + } + address = address + (3 * f_ebytes); + } + } + /* Handle VST4. */ + else if (!(b_bits & 0x0e)) + { + for (index_e = 0; index_e < f_elem; index_e++) + { + for (loop_t = 0; loop_t < 4; loop_t++) + { + record_buf_mem[index_m++] = f_ebytes; + record_buf_mem[index_m++] = address + (loop_t * f_ebytes); + thumb2_insn_r->mem_rec_count += 1; + } + address = address + (4 * f_ebytes); + } + } + } + else + { + uint8_t bft_size = bits (thumb2_insn_r->arm_insn, 10, 11); + + if (bft_size == 0x00) + f_ebytes = 1; + else if (bft_size == 0x01) + f_ebytes = 2; + else if (bft_size == 0x02) + f_ebytes = 4; + else + f_ebytes = 0; + + /* Handle VST1. */ + if (!(b_bits & 0x0b) || b_bits == 0x08) + thumb2_insn_r->mem_rec_count = 1; + /* Handle VST2. */ + else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09) + thumb2_insn_r->mem_rec_count = 2; + /* Handle VST3. */ + else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a) + thumb2_insn_r->mem_rec_count = 3; + /* Handle VST4. */ + else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b) + thumb2_insn_r->mem_rec_count = 4; + + for (index_m = 0; index_m < thumb2_insn_r->mem_rec_count; index_m++) + { + record_buf_mem[index_m] = f_ebytes; + record_buf_mem[index_m] = address + (index_m * f_ebytes); + } + } + } + else + { + if (!a_bit) + { + /* Handle VLD1. */ + if (b_bits == 0x02 || b_bits == 0x0a || (b_bits & 0x0e) == 0x06) + thumb2_insn_r->reg_rec_count = 1; + /* Handle VLD2. */ + else if (b_bits == 0x03 || (b_bits & 0x0e) == 0x08) + thumb2_insn_r->reg_rec_count = 2; + /* Handle VLD3. */ + else if ((b_bits & 0x0e) == 0x04) + thumb2_insn_r->reg_rec_count = 3; + /* Handle VLD4. */ + else if (!(b_bits & 0x0e)) + thumb2_insn_r->reg_rec_count = 4; + } + else + { + /* Handle VLD1. */ + if (!(b_bits & 0x0b) || b_bits == 0x08 || b_bits == 0x0c) + thumb2_insn_r->reg_rec_count = 1; + /* Handle VLD2. */ + else if ((b_bits & 0x0b) == 0x01 || b_bits == 0x09 || b_bits == 0x0d) + thumb2_insn_r->reg_rec_count = 2; + /* Handle VLD3. */ + else if ((b_bits & 0x0b) == 0x02 || b_bits == 0x0a || b_bits == 0x0e) + thumb2_insn_r->reg_rec_count = 3; + /* Handle VLD4. */ + else if ((b_bits & 0x0b) == 0x03 || b_bits == 0x0b || b_bits == 0x0f) + thumb2_insn_r->reg_rec_count = 4; + + for (index_r = 0; index_r < thumb2_insn_r->reg_rec_count; index_r++) + record_buf[index_r] = reg_vd + ARM_D0_REGNUM + index_r; + } + } + + if (bits (thumb2_insn_r->arm_insn, 0, 3) != 15) + { + record_buf[index_r] = reg_rn; + thumb2_insn_r->reg_rec_count += 1; + } + + REG_ALLOC (thumb2_insn_r->arm_regs, thumb2_insn_r->reg_rec_count, + record_buf); + MEM_ALLOC (thumb2_insn_r->arm_mems, thumb2_insn_r->mem_rec_count, + record_buf_mem); + return 0; +} + /* Decodes thumb2 instruction type and invokes its record handler. */ static unsigned int @@ -12974,7 +13692,7 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) else if (op2 & 0x40) { /* Co-processor instructions. */ - arm_record_unsupported_insn (thumb2_insn_r); + return thumb2_record_coproc_insn (thumb2_insn_r); } } else if (op1 == 0x02) @@ -13005,7 +13723,7 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) else if (!((op2 & 0x71) ^ 0x10)) { /* Advanced SIMD or structure load/store instructions. */ - return arm_record_unsupported_insn (thumb2_insn_r); + return thumb2_record_asimd_struct_ld_st (thumb2_insn_r); } else if (!((op2 & 0x67) ^ 0x01)) { @@ -13040,7 +13758,7 @@ thumb2_record_decode_insn_handler (insn_decode_record *thumb2_insn_r) else if (op2 & 0x40) { /* Co-processor instructions. */ - return arm_record_unsupported_insn (thumb2_insn_r); + return thumb2_record_coproc_insn (thumb2_insn_r); } } @@ -13061,7 +13779,7 @@ extract_arm_insn (insn_decode_record *insn_record, uint32_t insn_size) return 1; insn_record->arm_insn = (uint32_t) extract_unsigned_integer (&buf[0], insn_size, - gdbarch_byte_order (insn_record->gdbarch)); + gdbarch_byte_order_for_code (insn_record->gdbarch)); return 0; } @@ -13084,7 +13802,7 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type, arm_record_ld_st_reg_offset, /* 011. */ arm_record_ld_st_multiple, /* 100. */ arm_record_b_bl, /* 101. */ - arm_record_unsupported_insn, /* 110. */ + arm_record_asimd_vfp_coproc, /* 110. */ arm_record_coproc_data_proc /* 111. */ };