X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gdb%2Farm-tdep.h;h=f8ba122b35a34796b07ef1ff5438f5cfc57cfcd2;hb=ee01b6652ad55437e777fb7e6b1745782dc205a4;hp=968c4f28df1ff495460c9fb283e4a123641789c9;hpb=58d6951de562a3ef2214927006541fc16f0e5bd0;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h index 968c4f28df..f8ba122b35 100644 --- a/gdb/arm-tdep.h +++ b/gdb/arm-tdep.h @@ -1,5 +1,5 @@ /* Common target dependent code for GDB on ARM systems. - Copyright (C) 2002, 2003, 2007, 2008, 2009 Free Software Foundation, Inc. + Copyright (C) 2002-2014 Free Software Foundation, Inc. This file is part of GDB. @@ -22,6 +22,7 @@ /* Forward declarations. */ struct gdbarch; struct regset; +struct address_space; /* Register numbers of various important registers. */ @@ -49,6 +50,7 @@ enum gdb_regnum { ARM_WCGR7_REGNUM = ARM_WCGR0_REGNUM + 7, ARM_D0_REGNUM, /* VFP double-precision registers. */ ARM_D31_REGNUM = ARM_D0_REGNUM + 31, + ARM_FPSCR_REGNUM, ARM_NUM_REGS, @@ -69,6 +71,10 @@ enum gdb_regnum { bits. DWORD aligned they use 96 bits. */ #define FP_REGISTER_SIZE 12 +/* Say how long VFP double precision registers are. Used for documentation + purposes and code readability. These are fixed at 64 bits. */ +#define VFP_REGISTER_SIZE 8 + /* Number of machine registers. The only define actually required is gdbarch_num_regs. The other definitions are used for documentation purposes and code readability. */ @@ -106,6 +112,8 @@ enum gdb_regnum { #define CPSR_T 0x20 +#define XPSR_T 0x01000000 + /* Type of floating-point code in use by inferior. There are really 3 models that are traditionally supported (plus the endianness issue), but gcc can only generate 2 of those. The third is APCS_FLOAT, where arguments to @@ -161,15 +169,23 @@ struct gdbarch_tdep have_vfp_pseudos. */ int have_neon; /* Do we have a NEON unit? */ + int is_m; /* Does the target follow the "M" profile. */ CORE_ADDR lowest_pc; /* Lowest address at which instructions will appear. */ - const char *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */ + const gdb_byte *arm_breakpoint; /* Breakpoint pattern for an ARM insn. */ int arm_breakpoint_size; /* And its size. */ - const char *thumb_breakpoint; /* Breakpoint pattern for an ARM insn. */ + const gdb_byte *thumb_breakpoint; /* Breakpoint pattern for a Thumb insn. */ int thumb_breakpoint_size; /* And its size. */ - int jb_pc; /* Offset to PC value in jump buffer. + /* If the Thumb breakpoint is an undefined instruction (which is + affected by IT blocks) rather than a BKPT instruction (which is + not), then we need a 32-bit Thumb breakpoint to preserve the + instruction count in IT blocks. */ + const gdb_byte *thumb2_breakpoint; + int thumb2_breakpoint_size; + + int jb_pc; /* Offset to PC value in jump buffer. If this is negative, longjmp support will be disabled. */ size_t jb_elt_size; /* And the size of each entry in the buf. */ @@ -178,19 +194,151 @@ struct gdbarch_tdep enum struct_return struct_return; /* Cached core file helpers. */ - struct regset *gregset, *fpregset; + struct regset *gregset, *fpregset, *vfpregset; /* ISA-specific data types. */ struct type *arm_ext_type; struct type *neon_double_type; struct type *neon_quad_type; + + /* Return the expected next PC if FRAME is stopped at a syscall + instruction. */ + CORE_ADDR (*syscall_next_pc) (struct frame_info *frame); + + /* syscall record. */ + int (*arm_syscall_record) (struct regcache *regcache, unsigned long svc_number); +}; + +/* Structures used for displaced stepping. */ + +/* The maximum number of temporaries available for displaced instructions. */ +#define DISPLACED_TEMPS 16 +/* The maximum number of modified instructions generated for one single-stepped + instruction, including the breakpoint (usually at the end of the instruction + sequence) and any scratch words, etc. */ +#define DISPLACED_MODIFIED_INSNS 8 + +struct displaced_step_closure +{ + ULONGEST tmp[DISPLACED_TEMPS]; + int rd; + int wrote_to_pc; + union + { + struct + { + int xfersize; + int rn; /* Writeback register. */ + unsigned int immed : 1; /* Offset is immediate. */ + unsigned int writeback : 1; /* Perform base-register writeback. */ + unsigned int restore_r4 : 1; /* Used r4 as scratch. */ + } ldst; + + struct + { + unsigned long dest; + unsigned int link : 1; + unsigned int exchange : 1; + unsigned int cond : 4; + } branch; + + struct + { + unsigned int regmask; + int rn; + CORE_ADDR xfer_addr; + unsigned int load : 1; + unsigned int user : 1; + unsigned int increment : 1; + unsigned int before : 1; + unsigned int writeback : 1; + unsigned int cond : 4; + } block; + + struct + { + unsigned int immed : 1; + } preload; + + struct + { + /* If non-NULL, override generic SVC handling (e.g. for a particular + OS). */ + int (*copy_svc_os) (struct gdbarch *gdbarch, struct regcache *regs, + struct displaced_step_closure *dsc); + } svc; + } u; + + /* The size of original instruction, 2 or 4. */ + unsigned int insn_size; + /* True if the original insn (and thus all replacement insns) are Thumb + instead of ARM. */ + unsigned int is_thumb; + + /* The slots in the array is used in this way below, + - ARM instruction occupies one slot, + - Thumb 16 bit instruction occupies one slot, + - Thumb 32-bit instruction occupies *two* slots, one part for each. */ + unsigned long modinsn[DISPLACED_MODIFIED_INSNS]; + int numinsns; + CORE_ADDR insn_addr; + CORE_ADDR scratch_base; + void (*cleanup) (struct gdbarch *, struct regcache *, + struct displaced_step_closure *); +}; + +/* Values for the WRITE_PC argument to displaced_write_reg. If the register + write may write to the PC, specifies the way the CPSR T bit, etc. is + modified by the instruction. */ + +enum pc_write_style +{ + BRANCH_WRITE_PC, + BX_WRITE_PC, + LOAD_WRITE_PC, + ALU_WRITE_PC, + CANNOT_WRITE_PC }; +extern void + arm_process_displaced_insn (struct gdbarch *gdbarch, CORE_ADDR from, + CORE_ADDR to, struct regcache *regs, + struct displaced_step_closure *dsc); +extern void + arm_displaced_init_closure (struct gdbarch *gdbarch, CORE_ADDR from, + CORE_ADDR to, struct displaced_step_closure *dsc); +extern ULONGEST + displaced_read_reg (struct regcache *regs, struct displaced_step_closure *dsc, + int regno); +extern void + displaced_write_reg (struct regcache *regs, + struct displaced_step_closure *dsc, int regno, + ULONGEST val, enum pc_write_style write_pc); CORE_ADDR arm_skip_stub (struct frame_info *, CORE_ADDR); CORE_ADDR arm_get_next_pc (struct frame_info *, CORE_ADDR); +void arm_insert_single_step_breakpoint (struct gdbarch *, + struct address_space *, CORE_ADDR); +int arm_deal_with_atomic_sequence (struct frame_info *); int arm_software_single_step (struct frame_info *); +int arm_frame_is_thumb (struct frame_info *frame); +extern struct displaced_step_closure * + arm_displaced_step_copy_insn (struct gdbarch *, CORE_ADDR, CORE_ADDR, + struct regcache *); +extern void arm_displaced_step_fixup (struct gdbarch *, + struct displaced_step_closure *, + CORE_ADDR, CORE_ADDR, struct regcache *); + +/* Return the bit mask in ARM_PS_REGNUM that indicates Thumb mode. */ +extern int arm_psr_thumb_bit (struct gdbarch *); + +/* Is the instruction at the given memory address a Thumb or ARM + instruction? */ +extern int arm_pc_is_thumb (struct gdbarch *, CORE_ADDR); + +extern int arm_process_record (struct gdbarch *gdbarch, + struct regcache *regcache, CORE_ADDR addr); /* Functions exported from armbsd-tdep.h. */ /* Return the appropriate register set for the core section identified @@ -200,4 +348,11 @@ extern const struct regset * armbsd_regset_from_core_section (struct gdbarch *gdbarch, const char *sect_name, size_t sect_size); +/* Target descriptions. */ +extern struct target_desc *tdesc_arm_with_m; +extern struct target_desc *tdesc_arm_with_iwmmxt; +extern struct target_desc *tdesc_arm_with_vfpv2; +extern struct target_desc *tdesc_arm_with_vfpv3; +extern struct target_desc *tdesc_arm_with_neon; + #endif /* arm-tdep.h */