X-Git-Url: http://drtracing.org/?a=blobdiff_plain;f=gdb%2Fd10v-tdep.c;h=3002444fe23ca23b5ccc8e8b761f0973918da0a5;hb=eb8bc2821737a21e228c59dfce228e03cb7586a8;hp=f4b52f62295bb13dd6115dacbffad9fb195c1e21;hpb=c906108c21474dfb4ed285bcc0ac6fe02cd400cc;p=deliverable%2Fbinutils-gdb.git diff --git a/gdb/d10v-tdep.c b/gdb/d10v-tdep.c index f4b52f6229..135a0dd401 100644 --- a/gdb/d10v-tdep.c +++ b/gdb/d10v-tdep.c @@ -1,27 +1,31 @@ /* Target-dependent code for Mitsubishi D10V, for GDB. - Copyright (C) 1996, 1997 Free Software Foundation, Inc. -This file is part of GDB. + Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software + Foundation, Inc. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. + This file is part of GDB. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* Contributed by Martin Hunt, hunt@cygnus.com */ #include "defs.h" #include "frame.h" -#include "obstack.h" +#include "frame-unwind.h" +#include "frame-base.h" #include "symtab.h" #include "gdbtypes.h" #include "gdbcmd.h" @@ -29,21 +33,86 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "gdb_string.h" #include "value.h" #include "inferior.h" -#include "dis-asm.h" +#include "dis-asm.h" #include "symfile.h" #include "objfiles.h" +#include "language.h" +#include "arch-utils.h" +#include "regcache.h" +#include "remote.h" +#include "floatformat.h" +#include "gdb/sim-d10v.h" +#include "sim-regno.h" +#include "disasm.h" +#include "trad-frame.h" + +#include "gdb_assert.h" + +struct gdbarch_tdep + { + int a0_regnum; + int nr_dmap_regs; + unsigned long (*dmap_register) (void *regcache, int nr); + unsigned long (*imap_register) (void *regcache, int nr); + }; + +/* These are the addresses the D10V-EVA board maps data and + instruction memory to. */ + +enum memspace { + DMEM_START = 0x2000000, + IMEM_START = 0x1000000, + STACK_START = 0x200bffe +}; + +/* d10v register names. */ + +enum + { + R0_REGNUM = 0, + R3_REGNUM = 3, + D10V_FP_REGNUM = 11, + LR_REGNUM = 13, + D10V_SP_REGNUM = 15, + PSW_REGNUM = 16, + D10V_PC_REGNUM = 18, + NR_IMAP_REGS = 2, + NR_A_REGS = 2, + TS2_NUM_REGS = 37, + TS3_NUM_REGS = 42, + /* d10v calling convention. */ + ARG1_REGNUM = R0_REGNUM, + ARGN_REGNUM = R3_REGNUM, + RET1_REGNUM = R0_REGNUM, + }; -void d10v_frame_find_saved_regs PARAMS ((struct frame_info *fi, - struct frame_saved_regs *fsr)); +static int +nr_dmap_regs (struct gdbarch *gdbarch) +{ + return gdbarch_tdep (gdbarch)->nr_dmap_regs; +} -int -d10v_frame_chain_valid (chain, frame) - CORE_ADDR chain; - struct frame_info *frame; /* not used here */ +static int +a0_regnum (struct gdbarch *gdbarch) { - return ((chain) != 0 && (frame) != 0 && (frame)->pc > IMEM_START); + return gdbarch_tdep (gdbarch)->a0_regnum; } +/* Local functions */ + +extern void _initialize_d10v_tdep (void); + +static void d10v_eva_prepare_to_trace (void); + +static void d10v_eva_get_trace_data (void); + +static CORE_ADDR +d10v_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) +{ + /* Align to the size of an instruction (so that they can safely be + pushed onto the stack. */ + return sp & ~3; +} /* Should we use EXTRACT_STRUCT_VALUE_ADDRESS instead of EXTRACT_RETURN_VALUE? GCC_P is true if compiled with gcc @@ -52,62 +121,350 @@ d10v_frame_chain_valid (chain, frame) The d10v returns anything less than 8 bytes in size in registers. */ -int -d10v_use_struct_convention (gcc_p, type) - int gcc_p; - struct type *type; +static int +d10v_use_struct_convention (int gcc_p, struct type *type) { - return (TYPE_LENGTH (type) > 8); + long alignment; + int i; + /* The d10v only passes a struct in a register when that structure + has an alignment that matches the size of a register. */ + /* If the structure doesn't fit in 4 registers, put it on the + stack. */ + if (TYPE_LENGTH (type) > 8) + return 1; + /* If the struct contains only one field, don't put it on the stack + - gcc can fit it in one or more registers. */ + if (TYPE_NFIELDS (type) == 1) + return 0; + alignment = TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)); + for (i = 1; i < TYPE_NFIELDS (type); i++) + { + /* If the alignment changes, just assume it goes on the + stack. */ + if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, i)) != alignment) + return 1; + } + /* If the alignment is suitable for the d10v's 16 bit registers, + don't put it on the stack. */ + if (alignment == 2 || alignment == 4) + return 0; + return 1; } -/* Discard from the stack the innermost frame, restoring all saved - registers. */ +static const unsigned char * +d10v_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) +{ + static unsigned char breakpoint[] = + {0x2f, 0x90, 0x5e, 0x00}; + *lenptr = sizeof (breakpoint); + return breakpoint; +} -void -d10v_pop_frame (frame) - struct frame_info *frame; +/* Map the REG_NR onto an ascii name. Return NULL or an empty string + when the reg_nr isn't valid. */ + +enum ts2_regnums + { + TS2_IMAP0_REGNUM = 32, + TS2_DMAP_REGNUM = 34, + TS2_NR_DMAP_REGS = 1, + TS2_A0_REGNUM = 35 + }; + +static const char * +d10v_ts2_register_name (int reg_nr) +{ + static char *register_names[] = + { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", + "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", + "imap0", "imap1", "dmap", "a0", "a1" + }; + if (reg_nr < 0) + return NULL; + if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) + return NULL; + return register_names[reg_nr]; +} + +enum ts3_regnums + { + TS3_IMAP0_REGNUM = 36, + TS3_DMAP0_REGNUM = 38, + TS3_NR_DMAP_REGS = 4, + TS3_A0_REGNUM = 32 + }; + +static const char * +d10v_ts3_register_name (int reg_nr) { - CORE_ADDR fp; - int regnum; - struct frame_saved_regs fsr; - char raw_buffer[8]; - - fp = FRAME_FP (frame); - /* fill out fsr with the address of where each */ - /* register was stored in the frame */ - get_frame_saved_regs (frame, &fsr); - - /* now update the current registers with the old values */ - for (regnum = A0_REGNUM; regnum < A0_REGNUM+2 ; regnum++) + static char *register_names[] = + { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "psw", "bpsw", "pc", "bpc", "cr4", "cr5", "cr6", "rpt_c", + "rpt_s", "rpt_e", "mod_s", "mod_e", "cr12", "cr13", "iba", "cr15", + "a0", "a1", + "spi", "spu", + "imap0", "imap1", + "dmap0", "dmap1", "dmap2", "dmap3" + }; + if (reg_nr < 0) + return NULL; + if (reg_nr >= (sizeof (register_names) / sizeof (*register_names))) + return NULL; + return register_names[reg_nr]; +} + +/* Access the DMAP/IMAP registers in a target independent way. + + Divide the D10V's 64k data space into four 16k segments: + 0x0000 -- 0x3fff, 0x4000 -- 0x7fff, 0x8000 -- 0xbfff, and + 0xc000 -- 0xffff. + + On the TS2, the first two segments (0x0000 -- 0x3fff, 0x4000 -- + 0x7fff) always map to the on-chip data RAM, and the fourth always + maps to I/O space. The third (0x8000 - 0xbfff) can be mapped into + unified memory or instruction memory, under the control of the + single DMAP register. + + On the TS3, there are four DMAP registers, each of which controls + one of the segments. */ + +static unsigned long +d10v_ts2_dmap_register (void *regcache, int reg_nr) +{ + switch (reg_nr) { - if (fsr.regs[regnum]) - { - read_memory (fsr.regs[regnum], raw_buffer, REGISTER_RAW_SIZE(regnum)); - write_register_bytes (REGISTER_BYTE (regnum), raw_buffer, REGISTER_RAW_SIZE(regnum)); - } + case 0: + case 1: + return 0x2000; + case 2: + { + ULONGEST reg; + regcache_cooked_read_unsigned (regcache, TS2_DMAP_REGNUM, ®); + return reg; + } + default: + return 0; + } +} + +static unsigned long +d10v_ts3_dmap_register (void *regcache, int reg_nr) +{ + ULONGEST reg; + regcache_cooked_read_unsigned (regcache, TS3_DMAP0_REGNUM + reg_nr, ®); + return reg; +} + +static unsigned long +d10v_ts2_imap_register (void *regcache, int reg_nr) +{ + ULONGEST reg; + regcache_cooked_read_unsigned (regcache, TS2_IMAP0_REGNUM + reg_nr, ®); + return reg; +} + +static unsigned long +d10v_ts3_imap_register (void *regcache, int reg_nr) +{ + ULONGEST reg; + regcache_cooked_read_unsigned (regcache, TS3_IMAP0_REGNUM + reg_nr, ®); + return reg; +} + +/* MAP GDB's internal register numbering (determined by the layout fo + the REGISTER_BYTE array) onto the simulator's register + numbering. */ + +static int +d10v_ts2_register_sim_regno (int nr) +{ + /* Only makes sense to supply raw registers. */ + gdb_assert (nr >= 0 && nr < NUM_REGS); + if (nr >= TS2_IMAP0_REGNUM + && nr < TS2_IMAP0_REGNUM + NR_IMAP_REGS) + return nr - TS2_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; + if (nr == TS2_DMAP_REGNUM) + return nr - TS2_DMAP_REGNUM + SIM_D10V_TS2_DMAP_REGNUM; + if (nr >= TS2_A0_REGNUM + && nr < TS2_A0_REGNUM + NR_A_REGS) + return nr - TS2_A0_REGNUM + SIM_D10V_A0_REGNUM; + return nr; +} + +static int +d10v_ts3_register_sim_regno (int nr) +{ + /* Only makes sense to supply raw registers. */ + gdb_assert (nr >= 0 && nr < NUM_REGS); + if (nr >= TS3_IMAP0_REGNUM + && nr < TS3_IMAP0_REGNUM + NR_IMAP_REGS) + return nr - TS3_IMAP0_REGNUM + SIM_D10V_IMAP0_REGNUM; + if (nr >= TS3_DMAP0_REGNUM + && nr < TS3_DMAP0_REGNUM + TS3_NR_DMAP_REGS) + return nr - TS3_DMAP0_REGNUM + SIM_D10V_DMAP0_REGNUM; + if (nr >= TS3_A0_REGNUM + && nr < TS3_A0_REGNUM + NR_A_REGS) + return nr - TS3_A0_REGNUM + SIM_D10V_A0_REGNUM; + return nr; +} + +/* Return the GDB type object for the "standard" data type + of data in register N. */ + +static struct type * +d10v_register_type (struct gdbarch *gdbarch, int reg_nr) +{ + if (reg_nr == D10V_PC_REGNUM) + return builtin_type_void_func_ptr; + if (reg_nr == D10V_SP_REGNUM || reg_nr == D10V_FP_REGNUM) + return builtin_type_void_data_ptr; + else if (reg_nr >= a0_regnum (gdbarch) + && reg_nr < (a0_regnum (gdbarch) + NR_A_REGS)) + return builtin_type_int64; + else + return builtin_type_int16; +} + +static int +d10v_daddr_p (CORE_ADDR x) +{ + return (((x) & 0x3000000) == DMEM_START); +} + +static int +d10v_iaddr_p (CORE_ADDR x) +{ + return (((x) & 0x3000000) == IMEM_START); +} + +static CORE_ADDR +d10v_make_daddr (CORE_ADDR x) +{ + return ((x) | DMEM_START); +} + +static CORE_ADDR +d10v_make_iaddr (CORE_ADDR x) +{ + if (d10v_iaddr_p (x)) + return x; /* Idempotency -- x is already in the IMEM space. */ + else + return (((x) << 2) | IMEM_START); +} + +static CORE_ADDR +d10v_convert_iaddr_to_raw (CORE_ADDR x) +{ + return (((x) >> 2) & 0xffff); +} + +static CORE_ADDR +d10v_convert_daddr_to_raw (CORE_ADDR x) +{ + return ((x) & 0xffff); +} + +static void +d10v_address_to_pointer (struct type *type, void *buf, CORE_ADDR addr) +{ + /* Is it a code address? */ + if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC + || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) + { + store_unsigned_integer (buf, TYPE_LENGTH (type), + d10v_convert_iaddr_to_raw (addr)); } - for (regnum = 0; regnum < SP_REGNUM; regnum++) + else { - if (fsr.regs[regnum]) - { - write_register (regnum, read_memory_unsigned_integer (fsr.regs[regnum], REGISTER_RAW_SIZE(regnum))); - } + /* Strip off any upper segment bits. */ + store_unsigned_integer (buf, TYPE_LENGTH (type), + d10v_convert_daddr_to_raw (addr)); + } +} + +static CORE_ADDR +d10v_pointer_to_address (struct type *type, const void *buf) +{ + CORE_ADDR addr = extract_unsigned_integer (buf, TYPE_LENGTH (type)); + /* Is it a code address? */ + if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC + || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD + || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) + return d10v_make_iaddr (addr); + else + return d10v_make_daddr (addr); +} + +/* Don't do anything if we have an integer, this way users can type 'x + ' w/o having gdb outsmart them. The internal gdb conversions + to the correct space are taken care of in the pointer_to_address + function. If we don't do this, 'x $fp' wouldn't work. */ +static CORE_ADDR +d10v_integer_to_address (struct type *type, void *buf) +{ + LONGEST val; + val = unpack_long (type, buf); + return val; +} + +/* Write into appropriate registers a function return value + of type TYPE, given in virtual format. + + Things always get returned in RET1_REGNUM, RET2_REGNUM, ... */ + +static void +d10v_store_return_value (struct type *type, struct regcache *regcache, + const void *valbuf) +{ + /* Only char return values need to be shifted right within the first + regnum. */ + if (TYPE_LENGTH (type) == 1 + && TYPE_CODE (type) == TYPE_CODE_INT) + { + bfd_byte tmp[2]; + tmp[1] = *(bfd_byte *)valbuf; + regcache_cooked_write (regcache, RET1_REGNUM, tmp); } - if (fsr.regs[PSW_REGNUM]) + else { - write_register (PSW_REGNUM, read_memory_unsigned_integer (fsr.regs[PSW_REGNUM], REGISTER_RAW_SIZE(PSW_REGNUM))); + int reg; + /* A structure is never more than 8 bytes long. See + use_struct_convention(). */ + gdb_assert (TYPE_LENGTH (type) <= 8); + /* Write out most registers, stop loop before trying to write + out any dangling byte at the end of the buffer. */ + for (reg = 0; (reg * 2) + 1 < TYPE_LENGTH (type); reg++) + { + regcache_cooked_write (regcache, RET1_REGNUM + reg, + (bfd_byte *) valbuf + reg * 2); + } + /* Write out any dangling byte at the end of the buffer. */ + if ((reg * 2) + 1 == TYPE_LENGTH (type)) + regcache_cooked_write_part (regcache, reg, 0, 1, + (bfd_byte *) valbuf + reg * 2); } +} + +/* Extract from an array REGBUF containing the (raw) register state + the address in which a function should return its structure value, + as a CORE_ADDR (or an expression that can be used as one). */ - write_register (PC_REGNUM, read_register (LR_REGNUM)); - write_register (SP_REGNUM, fp + frame->size); - target_store_registers (-1); - flush_cached_frames (); +static CORE_ADDR +d10v_extract_struct_value_address (struct regcache *regcache) +{ + ULONGEST addr; + regcache_cooked_read_unsigned (regcache, ARG1_REGNUM, &addr); + return (addr | DMEM_START); } -static int -check_prologue (op) - unsigned short op; +static int +check_prologue (unsigned short op) { /* st rn, @-sp */ if ((op & 0x7E1F) == 0x6C1F) @@ -134,15 +491,14 @@ check_prologue (op) return 1; /* st2w rn, @sp */ - if ((op & 0x7E3F) == 0x3A1E) - return 1; + if ((op & 0x7E3F) == 0x3A1E) + return 1; return 0; } -CORE_ADDR -d10v_skip_prologue (pc) - CORE_ADDR pc; +static CORE_ADDR +d10v_skip_prologue (CORE_ADDR pc) { unsigned long op; unsigned short op1, op2; @@ -154,22 +510,22 @@ d10v_skip_prologue (pc) if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) { sal = find_pc_line (func_addr, 0); - if ( sal.end && sal.end < func_end) + if (sal.end && sal.end < func_end) return sal.end; } - - if (target_read_memory (pc, (char *)&op, 4)) + + if (target_read_memory (pc, (char *) &op, 4)) return pc; /* Can't access it -- assume no prologue. */ while (1) { - op = (unsigned long)read_memory_integer (pc, 4); + op = (unsigned long) read_memory_integer (pc, 4); if ((op & 0xC0000000) == 0xC0000000) { /* long instruction */ - if ( ((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ - ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ - ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ + if (((op & 0x3FFF0000) != 0x01FF0000) && /* add3 sp,sp,n */ + ((op & 0x3F0F0000) != 0x340F0000) && /* st rn, @(offset,sp) */ + ((op & 0x3F1F0000) != 0x350F0000)) /* st2w rn, @(offset,sp) */ break; } else @@ -179,15 +535,15 @@ d10v_skip_prologue (pc) { op2 = (op & 0x3FFF8000) >> 15; op1 = op & 0x7FFF; - } - else + } + else { op1 = (op & 0x3FFF8000) >> 15; op2 = op & 0x7FFF; } - if (check_prologue(op1)) + if (check_prologue (op1)) { - if (!check_prologue(op2)) + if (!check_prologue (op2)) { /* if the previous opcode was really part of the prologue */ /* and not just a NOP, then we want to break after both instructions */ @@ -204,43 +560,27 @@ d10v_skip_prologue (pc) return pc; } -/* Given a GDB frame, determine the address of the calling function's frame. - This will be used to create a new GDB frame struct, and then - INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame. -*/ - -CORE_ADDR -d10v_frame_chain (frame) - struct frame_info *frame; +struct d10v_unwind_cache { - struct frame_saved_regs fsr; - - d10v_frame_find_saved_regs (frame, &fsr); - - if (frame->return_pc == IMEM_START || inside_entry_file(frame->return_pc)) - return (CORE_ADDR)0; - - if (!fsr.regs[FP_REGNUM]) - { - if (!fsr.regs[SP_REGNUM] || fsr.regs[SP_REGNUM] == STACK_START) - return (CORE_ADDR)0; - - return fsr.regs[SP_REGNUM]; - } - - if (!read_memory_unsigned_integer(fsr.regs[FP_REGNUM], REGISTER_RAW_SIZE(FP_REGNUM))) - return (CORE_ADDR)0; - - return D10V_MAKE_DADDR (read_memory_unsigned_integer (fsr.regs[FP_REGNUM], REGISTER_RAW_SIZE (FP_REGNUM))); -} - -static int next_addr, uses_frame; + /* The previous frame's inner most stack address. Used as this + frame ID's stack_addr. */ + CORE_ADDR prev_sp; + /* The frame's base, optionally used by the high-level debug info. */ + CORE_ADDR base; + int size; + /* How far the SP and r11 (FP) have been offset from the start of + the stack frame (as defined by the previous frame's stack + pointer). */ + LONGEST sp_offset; + LONGEST r11_offset; + int uses_frame; + /* Table indicating the location of each and every register. */ + struct trad_frame_saved_reg *saved_regs; +}; -static int -prologue_find_regs (op, fsr, addr) - unsigned short op; - struct frame_saved_regs *fsr; - CORE_ADDR addr; +static int +prologue_find_regs (struct d10v_unwind_cache *info, unsigned short op, + CORE_ADDR addr) { int n; @@ -248,8 +588,8 @@ prologue_find_regs (op, fsr, addr) if ((op & 0x7E1F) == 0x6C1F) { n = (op & 0x1E0) >> 5; - next_addr -= 2; - fsr->regs[n] = next_addr; + info->sp_offset -= 2; + info->saved_regs[n].addr = info->sp_offset; return 1; } @@ -257,9 +597,9 @@ prologue_find_regs (op, fsr, addr) else if ((op & 0x7E3F) == 0x6E1F) { n = (op & 0x1E0) >> 5; - next_addr -= 4; - fsr->regs[n] = next_addr; - fsr->regs[n+1] = next_addr+2; + info->sp_offset -= 4; + info->saved_regs[n + 0].addr = info->sp_offset + 0; + info->saved_regs[n + 1].addr = info->sp_offset + 2; return 1; } @@ -269,14 +609,23 @@ prologue_find_regs (op, fsr, addr) n = (op & 0x1E) >> 1; if (n == 0) n = 16; - next_addr -= n; + info->sp_offset -= n; return 1; } /* mv r11, sp */ if (op == 0x417E) { - uses_frame = 1; + info->uses_frame = 1; + info->r11_offset = info->sp_offset; + return 1; + } + + /* st rn, @r11 */ + if ((op & 0x7E1F) == 0x6816) + { + n = (op & 0x1E0) >> 5; + info->saved_regs[n].addr = info->r11_offset; return 1; } @@ -288,7 +637,7 @@ prologue_find_regs (op, fsr, addr) if ((op & 0x7E1F) == 0x681E) { n = (op & 0x1E0) >> 5; - fsr->regs[n] = next_addr; + info->saved_regs[n].addr = info->sp_offset; return 1; } @@ -296,39 +645,49 @@ prologue_find_regs (op, fsr, addr) if ((op & 0x7E3F) == 0x3A1E) { n = (op & 0x1E0) >> 5; - fsr->regs[n] = next_addr; - fsr->regs[n+1] = next_addr+2; + info->saved_regs[n + 0].addr = info->sp_offset + 0; + info->saved_regs[n + 1].addr = info->sp_offset + 2; return 1; } return 0; } -/* Put here the code to store, into a struct frame_saved_regs, the - addresses of the saved registers of frame described by FRAME_INFO. - This includes special registers such as pc and fp saved in special - ways in the stack frame. sp is even more special: the address we - return for it IS the sp for the next frame. */ -void -d10v_frame_find_saved_regs (fi, fsr) - struct frame_info *fi; - struct frame_saved_regs *fsr; +/* Put here the code to store, into fi->saved_regs, the addresses of + the saved registers of frame described by FRAME_INFO. This + includes special registers such as pc and fp saved in special ways + in the stack frame. sp is even more special: the address we return + for it IS the sp for the next frame. */ + +static struct d10v_unwind_cache * +d10v_frame_unwind_cache (struct frame_info *next_frame, + void **this_prologue_cache) { - CORE_ADDR fp, pc; + struct gdbarch *gdbarch = get_frame_arch (next_frame); + CORE_ADDR pc; + ULONGEST prev_sp; + ULONGEST this_base; unsigned long op; unsigned short op1, op2; int i; + struct d10v_unwind_cache *info; - fp = fi->frame; - memset (fsr, 0, sizeof (*fsr)); - next_addr = 0; + if ((*this_prologue_cache)) + return (*this_prologue_cache); - pc = get_pc_function_start (fi->pc); + info = FRAME_OBSTACK_ZALLOC (struct d10v_unwind_cache); + (*this_prologue_cache) = info; + info->saved_regs = trad_frame_alloc_saved_regs (next_frame); - uses_frame = 0; - while (1) + info->size = 0; + info->sp_offset = 0; + + info->uses_frame = 0; + for (pc = frame_func_unwind (next_frame); + pc > 0 && pc < frame_pc_unwind (next_frame); + pc += 4) { - op = (unsigned long)read_memory_integer (pc, 4); + op = get_frame_memory_unsigned (next_frame, pc, 4); if ((op & 0xC0000000) == 0xC0000000) { /* long instruction */ @@ -336,22 +695,22 @@ d10v_frame_find_saved_regs (fi, fsr) { /* add3 sp,sp,n */ short n = op & 0xFFFF; - next_addr += n; + info->sp_offset += n; } else if ((op & 0x3F0F0000) == 0x340F0000) { /* st rn, @(offset,sp) */ short offset = op & 0xFFFF; short n = (op >> 20) & 0xF; - fsr->regs[n] = next_addr + offset; + info->saved_regs[n].addr = info->sp_offset + offset; } else if ((op & 0x3F1F0000) == 0x350F0000) { /* st2w rn, @(offset,sp) */ short offset = op & 0xFFFF; short n = (op >> 20) & 0xF; - fsr->regs[n] = next_addr + offset; - fsr->regs[n+1] = next_addr + offset + 2; + info->saved_regs[n + 0].addr = info->sp_offset + offset + 0; + info->saved_regs[n + 1].addr = info->sp_offset + offset + 2; } else break; @@ -363,281 +722,323 @@ d10v_frame_find_saved_regs (fi, fsr) { op2 = (op & 0x3FFF8000) >> 15; op1 = op & 0x7FFF; - } - else + } + else { op1 = (op & 0x3FFF8000) >> 15; op2 = op & 0x7FFF; } - if (!prologue_find_regs(op1,fsr,pc) || !prologue_find_regs(op2,fsr,pc)) + if (!prologue_find_regs (info, op1, pc) + || !prologue_find_regs (info, op2, pc)) break; } - pc += 4; } - - fi->size = -next_addr; - - if (!(fp & 0xffff)) - fp = D10V_MAKE_DADDR (read_register(SP_REGNUM)); - for (i=0; iregs[i]) - { - fsr->regs[i] = fp - (next_addr - fsr->regs[i]); - } + info->size = -info->sp_offset; - if (fsr->regs[LR_REGNUM]) + /* Compute the previous frame's stack pointer (which is also the + frame's ID's stack address), and this frame's base pointer. */ + if (info->uses_frame) { - CORE_ADDR return_pc = read_memory_unsigned_integer (fsr->regs[LR_REGNUM], REGISTER_RAW_SIZE (LR_REGNUM)); - fi->return_pc = D10V_MAKE_IADDR (return_pc); + /* The SP was moved to the FP. This indicates that a new frame + was created. Get THIS frame's FP value by unwinding it from + the next frame. */ + frame_unwind_unsigned_register (next_frame, D10V_FP_REGNUM, &this_base); + /* The FP points at the last saved register. Adjust the FP back + to before the first saved register giving the SP. */ + prev_sp = this_base + info->size; } else { - fi->return_pc = D10V_MAKE_IADDR (read_register(LR_REGNUM)); - } - - /* th SP is not normally (ever?) saved, but check anyway */ - if (!fsr->regs[SP_REGNUM]) - { - /* if the FP was saved, that means the current FP is valid, */ - /* otherwise, it isn't being used, so we use the SP instead */ - if (uses_frame) - fsr->regs[SP_REGNUM] = read_register(FP_REGNUM) + fi->size; - else - { - fsr->regs[SP_REGNUM] = fp + fi->size; - fi->frameless = 1; - fsr->regs[FP_REGNUM] = 0; - } + /* Assume that the FP is this frame's SP but with that pushed + stack space added back. */ + frame_unwind_unsigned_register (next_frame, D10V_SP_REGNUM, &this_base); + prev_sp = this_base + info->size; } + + /* Convert that SP/BASE into real addresses. */ + info->prev_sp = d10v_make_daddr (prev_sp); + info->base = d10v_make_daddr (this_base); + + /* Adjust all the saved registers so that they contain addresses and + not offsets. */ + for (i = 0; i < NUM_REGS - 1; i++) + if (trad_frame_addr_p (info->saved_regs, i)) + { + info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); + } + + /* The call instruction moves the caller's PC in the callee's LR. + Since this is an unwind, do the reverse. Copy the location of LR + into PC (the address / regnum) so that a request for PC will be + converted into a request for the LR. */ + info->saved_regs[D10V_PC_REGNUM] = info->saved_regs[LR_REGNUM]; + + /* The previous frame's SP needed to be computed. Save the computed + value. */ + trad_frame_set_value (info->saved_regs, D10V_SP_REGNUM, + d10v_make_daddr (prev_sp)); + + return info; } -void -d10v_init_extra_frame_info (fromleaf, fi) - int fromleaf; - struct frame_info *fi; +static void +d10v_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, + struct frame_info *frame, int regnum, int all) { - fi->frameless = 0; - fi->size = 0; - fi->return_pc = 0; - - /* The call dummy doesn't save any registers on the stack, so we can - return now. */ - if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame)) + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + if (regnum >= 0) { + default_print_registers_info (gdbarch, file, frame, regnum, all); return; } - else - { - struct frame_saved_regs dummy; - d10v_frame_find_saved_regs (fi, &dummy); - } + + { + ULONGEST pc, psw, rpt_s, rpt_e, rpt_c; + frame_read_unsigned_register (frame, D10V_PC_REGNUM, &pc); + frame_read_unsigned_register (frame, PSW_REGNUM, &psw); + frame_read_unsigned_register (frame, frame_map_name_to_regnum (frame, "rpt_s", -1), &rpt_s); + frame_read_unsigned_register (frame, frame_map_name_to_regnum (frame, "rpt_e", -1), &rpt_e); + frame_read_unsigned_register (frame, frame_map_name_to_regnum (frame, "rpt_c", -1), &rpt_c); + fprintf_filtered (file, "PC=%04lx (0x%lx) PSW=%04lx RPT_S=%04lx RPT_E=%04lx RPT_C=%04lx\n", + (long) pc, (long) d10v_make_iaddr (pc), (long) psw, + (long) rpt_s, (long) rpt_e, (long) rpt_c); + } + + { + int group; + for (group = 0; group < 16; group += 8) + { + int r; + fprintf_filtered (file, "R%d-R%-2d", group, group + 7); + for (r = group; r < group + 8; r++) + { + ULONGEST tmp; + frame_read_unsigned_register (frame, r, &tmp); + fprintf_filtered (file, " %04lx", (long) tmp); + } + fprintf_filtered (file, "\n"); + } + } + + /* Note: The IMAP/DMAP registers don't participate in function + calls. Don't bother trying to unwind them. */ + + { + int a; + for (a = 0; a < NR_IMAP_REGS; a++) + { + if (a > 0) + fprintf_filtered (file, " "); + fprintf_filtered (file, "IMAP%d %04lx", a, + tdep->imap_register (current_regcache, a)); + } + if (nr_dmap_regs (gdbarch) == 1) + /* Registers DMAP0 and DMAP1 are constant. Just return dmap2. */ + fprintf_filtered (file, " DMAP %04lx\n", + tdep->dmap_register (current_regcache, 2)); + else + { + for (a = 0; a < nr_dmap_regs (gdbarch); a++) + { + fprintf_filtered (file, " DMAP%d %04lx", a, + tdep->dmap_register (current_regcache, a)); + } + fprintf_filtered (file, "\n"); + } + } + + { + char num[MAX_REGISTER_SIZE]; + int a; + fprintf_filtered (file, "A0-A%d", NR_A_REGS - 1); + for (a = a0_regnum (gdbarch); a < a0_regnum (gdbarch) + NR_A_REGS; a++) + { + int i; + fprintf_filtered (file, " "); + frame_read_register (frame, a, num); + for (i = 0; i < register_size (gdbarch, a); i++) + { + fprintf_filtered (file, "%02x", (num[i] & 0xff)); + } + } + } + fprintf_filtered (file, "\n"); } static void -show_regs (args, from_tty) - char *args; - int from_tty; +show_regs (char *args, int from_tty) { - int a; - printf_filtered ("PC=%04x (0x%x) PSW=%04x RPT_S=%04x RPT_E=%04x RPT_C=%04x\n", - read_register (PC_REGNUM), D10V_MAKE_IADDR (read_register (PC_REGNUM)), - read_register (PSW_REGNUM), - read_register (24), - read_register (25), - read_register (23)); - printf_filtered ("R0-R7 %04x %04x %04x %04x %04x %04x %04x %04x\n", - read_register (0), - read_register (1), - read_register (2), - read_register (3), - read_register (4), - read_register (5), - read_register (6), - read_register (7)); - printf_filtered ("R8-R15 %04x %04x %04x %04x %04x %04x %04x %04x\n", - read_register (8), - read_register (9), - read_register (10), - read_register (11), - read_register (12), - read_register (13), - read_register (14), - read_register (15)); - printf_filtered ("IMAP0 %04x IMAP1 %04x DMAP %04x\n", - read_register (IMAP0_REGNUM), - read_register (IMAP1_REGNUM), - read_register (DMAP_REGNUM)); - printf_filtered ("A0-A1"); - for (a = A0_REGNUM; a <= A0_REGNUM + 1; a++) - { - char num[MAX_REGISTER_RAW_SIZE]; - int i; - printf_filtered (" "); - read_register_gen (a, (char *)&num); - for (i = 0; i < MAX_REGISTER_RAW_SIZE; i++) - { - printf_filtered ("%02x", (num[i] & 0xff)); - } - } - printf_filtered ("\n"); + d10v_print_registers_info (current_gdbarch, gdb_stdout, + get_current_frame (), -1, 1); } -CORE_ADDR -d10v_read_pc (pid) - int pid; +static CORE_ADDR +d10v_read_pc (ptid_t ptid) { - int save_pid; + ptid_t save_ptid; CORE_ADDR pc; CORE_ADDR retval; - save_pid = inferior_pid; - inferior_pid = pid; - pc = (int) read_register (PC_REGNUM); - inferior_pid = save_pid; - retval = D10V_MAKE_IADDR (pc); + save_ptid = inferior_ptid; + inferior_ptid = ptid; + pc = (int) read_register (D10V_PC_REGNUM); + inferior_ptid = save_ptid; + retval = d10v_make_iaddr (pc); return retval; } -void -d10v_write_pc (val, pid) - CORE_ADDR val; - int pid; +static void +d10v_write_pc (CORE_ADDR val, ptid_t ptid) { - int save_pid; + ptid_t save_ptid; - save_pid = inferior_pid; - inferior_pid = pid; - write_register (PC_REGNUM, D10V_CONVERT_IADDR_TO_RAW (val)); - inferior_pid = save_pid; + save_ptid = inferior_ptid; + inferior_ptid = ptid; + write_register (D10V_PC_REGNUM, d10v_convert_iaddr_to_raw (val)); + inferior_ptid = save_ptid; } -CORE_ADDR -d10v_read_sp () +static CORE_ADDR +d10v_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) { - return (D10V_MAKE_DADDR (read_register (SP_REGNUM))); + ULONGEST sp; + frame_unwind_unsigned_register (next_frame, D10V_SP_REGNUM, &sp); + return d10v_make_daddr (sp); } -void -d10v_write_sp (val) - CORE_ADDR val; -{ - write_register (SP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val)); -} +/* When arguments must be pushed onto the stack, they go on in reverse + order. The below implements a FILO (stack) to do this. */ -void -d10v_write_fp (val) - CORE_ADDR val; +struct stack_item { - write_register (FP_REGNUM, D10V_CONVERT_DADDR_TO_RAW (val)); + int len; + struct stack_item *prev; + void *data; +}; + +static struct stack_item *push_stack_item (struct stack_item *prev, + void *contents, int len); +static struct stack_item * +push_stack_item (struct stack_item *prev, void *contents, int len) +{ + struct stack_item *si; + si = xmalloc (sizeof (struct stack_item)); + si->data = xmalloc (len); + si->len = len; + si->prev = prev; + memcpy (si->data, contents, len); + return si; } -CORE_ADDR -d10v_read_fp () +static struct stack_item *pop_stack_item (struct stack_item *si); +static struct stack_item * +pop_stack_item (struct stack_item *si) { - return (D10V_MAKE_DADDR (read_register(FP_REGNUM))); + struct stack_item *dead = si; + si = si->prev; + xfree (dead->data); + xfree (dead); + return si; } -/* Function: push_return_address (pc) - Set up the return address for the inferior function call. - Needed for targets where we don't actually execute a JSR/BSR instruction */ - -CORE_ADDR -d10v_push_return_address (pc, sp) - CORE_ADDR pc; - CORE_ADDR sp; + +static CORE_ADDR +d10v_push_dummy_code (struct gdbarch *gdbarch, + CORE_ADDR sp, CORE_ADDR funaddr, int using_gcc, + struct value **args, int nargs, + struct type *value_type, + CORE_ADDR *real_pc, CORE_ADDR *bp_addr) { - write_register (LR_REGNUM, D10V_CONVERT_IADDR_TO_RAW (CALL_DUMMY_ADDRESS ())); + /* Allocate space sufficient for a breakpoint. */ + sp = (sp - 4) & ~3; + /* Store the address of that breakpoint taking care to first convert + it into a code (IADDR) address from a stack (DADDR) address. + This of course assumes that the two virtual addresses map onto + the same real address. */ + (*bp_addr) = d10v_make_iaddr (d10v_convert_iaddr_to_raw (sp)); + /* d10v always starts the call at the callee's entry point. */ + (*real_pc) = funaddr; return sp; } - - -CORE_ADDR -d10v_push_arguments (nargs, args, sp, struct_return, struct_addr) - int nargs; - value_ptr *args; - CORE_ADDR sp; - int struct_return; - CORE_ADDR struct_addr; + +static CORE_ADDR +d10v_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr, + struct regcache *regcache, CORE_ADDR bp_addr, + int nargs, struct value **args, CORE_ADDR sp, int struct_return, + CORE_ADDR struct_addr) { int i; int regnum = ARG1_REGNUM; - + struct stack_item *si = NULL; + long val; + + /* Set the return address. For the d10v, the return breakpoint is + always at BP_ADDR. */ + regcache_cooked_write_unsigned (regcache, LR_REGNUM, + d10v_convert_iaddr_to_raw (bp_addr)); + + /* If STRUCT_RETURN is true, then the struct return address (in + STRUCT_ADDR) will consume the first argument-passing register. + Both adjust the register count and store that value. */ + if (struct_return) + { + regcache_cooked_write_unsigned (regcache, regnum, struct_addr); + regnum++; + } + /* Fill in registers and arg lists */ for (i = 0; i < nargs; i++) { - value_ptr arg = args[i]; + struct value *arg = args[i]; struct type *type = check_typedef (VALUE_TYPE (arg)); char *contents = VALUE_CONTENTS (arg); int len = TYPE_LENGTH (type); - /* printf ("push: type=%d len=%d\n", type->code, len); */ - if (TYPE_CODE (type) == TYPE_CODE_PTR) + int aligned_regnum = (regnum + 1) & ~1; + + /* printf ("push: type=%d len=%d\n", TYPE_CODE (type), len); */ + if (len <= 2 && regnum <= ARGN_REGNUM) + /* fits in a single register, do not align */ { - /* pointers require special handling - first convert and - then store */ - long val = extract_signed_integer (contents, len); - len = 2; - if (TYPE_TARGET_TYPE (type) - && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)) - { - /* function pointer */ - val = D10V_CONVERT_IADDR_TO_RAW (val); - } - else if (D10V_IADDR_P (val)) + val = extract_unsigned_integer (contents, len); + regcache_cooked_write_unsigned (regcache, regnum++, val); + } + else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) + /* value fits in remaining registers, store keeping left + aligned */ + { + int b; + regnum = aligned_regnum; + for (b = 0; b < (len & ~1); b += 2) { - /* also function pointer! */ - val = D10V_CONVERT_DADDR_TO_RAW (val); + val = extract_unsigned_integer (&contents[b], 2); + regcache_cooked_write_unsigned (regcache, regnum++, val); } - else + if (b < len) { - /* data pointer */ - val &= 0xFFFF; - } - if (regnum <= ARGN_REGNUM) - write_register (regnum++, val & 0xffff); - else - { - char ptr[2]; - sp -= 2; - store_address (ptr, val & 0xffff, 2); - write_memory (sp, ptr, 2); + val = extract_unsigned_integer (&contents[b], 1); + regcache_cooked_write_unsigned (regcache, regnum++, (val << 8)); } } else { - int aligned_regnum = (regnum + 1) & ~1; - if (len <= 2 && regnum <= ARGN_REGNUM) - /* fits in a single register, do not align */ - { - long val = extract_unsigned_integer (contents, len); - write_register (regnum++, val); - } - else if (len <= (ARGN_REGNUM - aligned_regnum + 1) * 2) - /* value fits in remaining registers, store keeping left - aligned */ - { - int b; - regnum = aligned_regnum; - for (b = 0; b < (len & ~1); b += 2) - { - long val = extract_unsigned_integer (&contents[b], 2); - write_register (regnum++, val); - } - if (b < len) - { - long val = extract_unsigned_integer (&contents[b], 1); - write_register (regnum++, (val << 8)); - } - } - else - { - /* arg goes straight on stack */ - regnum = ARGN_REGNUM + 1; - sp = (sp - len) & ~1; - write_memory (sp, contents, len); - } + /* arg will go onto stack */ + regnum = ARGN_REGNUM + 1; + si = push_stack_item (si, contents, len); } } + + while (si) + { + sp = (sp - si->len) & ~1; + write_memory (sp, si->data, si->len); + si = pop_stack_item (si); + } + + /* Finally, update the SP register. */ + regcache_cooked_write_unsigned (regcache, D10V_SP_REGNUM, + d10v_convert_daddr_to_raw (sp)); + return sp; } @@ -645,54 +1046,64 @@ d10v_push_arguments (nargs, args, sp, struct_return, struct_addr) /* Given a return value in `regbuf' with a type `valtype', extract and copy its value into `valbuf'. */ -void -d10v_extract_return_value (type, regbuf, valbuf) - struct type *type; - char regbuf[REGISTER_BYTES]; - char *valbuf; +static void +d10v_extract_return_value (struct type *type, struct regcache *regcache, + void *valbuf) { int len; - /* printf("RET: TYPE=%d len=%d r%d=0x%x\n",type->code, TYPE_LENGTH (type), RET1_REGNUM - R0_REGNUM, (int) extract_unsigned_integer (regbuf + REGISTER_BYTE(RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM))); */ - if (TYPE_CODE (type) == TYPE_CODE_PTR - && TYPE_TARGET_TYPE (type) - && (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC)) - { - /* pointer to function */ - int num; - short snum; - snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); - store_address ( valbuf, 4, D10V_MAKE_IADDR(snum)); - } - else if (TYPE_CODE(type) == TYPE_CODE_PTR) + if (TYPE_LENGTH (type) == 1) { - /* pointer to data */ - int num; - short snum; - snum = extract_address (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); - store_address ( valbuf, 4, D10V_MAKE_DADDR(snum)); + ULONGEST c; + regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &c); + store_unsigned_integer (valbuf, 1, c); } else { - len = TYPE_LENGTH (type); - if (len == 1) + /* For return values of odd size, the first byte is in the + least significant part of the first register. The + remaining bytes in remaining registers. Interestingly, when + such values are passed in, the last byte is in the most + significant byte of that same register - wierd. */ + int reg = RET1_REGNUM; + int off = 0; + if (TYPE_LENGTH (type) & 1) { - unsigned short c = extract_unsigned_integer (regbuf + REGISTER_BYTE (RET1_REGNUM), REGISTER_RAW_SIZE (RET1_REGNUM)); - store_unsigned_integer (valbuf, 1, c); + regcache_cooked_read_part (regcache, RET1_REGNUM, 1, 1, + (bfd_byte *)valbuf + off); + off++; + reg++; } - else if ((len & 1) == 0) - memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM), len); - else + /* Transfer the remaining registers. */ + for (; off < TYPE_LENGTH (type); reg++, off += 2) { - /* For return values of odd size, the first byte is in the - least significant part of the first register. The - remaining bytes in remaining registers. Interestingly, - when such values are passed in, the last byte is in the - most significant byte of that same register - wierd. */ - memcpy (valbuf, regbuf + REGISTER_BYTE (RET1_REGNUM) + 1, len); + regcache_cooked_read (regcache, RET1_REGNUM + reg, + (bfd_byte *) valbuf + off); } } } +/* Translate a GDB virtual ADDR/LEN into a format the remote target + understands. Returns number of bytes that can be transfered + starting at TARG_ADDR. Return ZERO if no bytes can be transfered + (segmentation fault). Since the simulator knows all about how the + VM system works, we just call that to do the translation. */ + +static void +remote_d10v_translate_xfer_address (struct gdbarch *gdbarch, + struct regcache *regcache, + CORE_ADDR memaddr, int nr_bytes, + CORE_ADDR *targ_addr, int *targ_len) +{ + struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); + long out_addr; + long out_len; + out_len = sim_d10v_translate_addr (memaddr, nr_bytes, &out_addr, regcache, + tdep->dmap_register, tdep->imap_register); + *targ_addr = out_addr; + *targ_len = out_len; +} + + /* The following code implements access to, and display of, the D10V's instruction trace buffer. The buffer consists of 64K or more 4-byte words of data, of which each words includes an 8-bit count, @@ -719,15 +1130,15 @@ d10v_extract_return_value (type, regbuf, valbuf) #define TRACE_BUFFER_BASE (0xf40000) -static void trace_command PARAMS ((char *, int)); +static void trace_command (char *, int); -static void untrace_command PARAMS ((char *, int)); +static void untrace_command (char *, int); -static void trace_info PARAMS ((char *, int)); +static void trace_info (char *, int); -static void tdisassemble_command PARAMS ((char *, int)); +static void tdisassemble_command (char *, int); -static void display_trace PARAMS ((int, int)); +static void display_trace (int, int); /* True when instruction traces are being collected. */ @@ -745,23 +1156,23 @@ static int trace_display; static int default_trace_show_source = 1; -struct trace_buffer { - int size; - short *counts; - CORE_ADDR *addrs; -} trace_data; +struct trace_buffer + { + int size; + short *counts; + CORE_ADDR *addrs; + } +trace_data; static void -trace_command (args, from_tty) - char *args; - int from_tty; +trace_command (char *args, int from_tty) { /* Clear the host-side trace buffer, allocating space if needed. */ trace_data.size = 0; if (trace_data.counts == NULL) - trace_data.counts = (short *) xmalloc (65536 * sizeof(short)); + trace_data.counts = XCALLOC (65536, short); if (trace_data.addrs == NULL) - trace_data.addrs = (CORE_ADDR *) xmalloc (65536 * sizeof(CORE_ADDR)); + trace_data.addrs = XCALLOC (65536, CORE_ADDR); tracing = 1; @@ -769,9 +1180,7 @@ trace_command (args, from_tty) } static void -untrace_command (args, from_tty) - char *args; - int from_tty; +untrace_command (char *args, int from_tty) { tracing = 0; @@ -779,9 +1188,7 @@ untrace_command (args, from_tty) } static void -trace_info (args, from_tty) - char *args; - int from_tty; +trace_info (char *args, int from_tty) { int i; @@ -791,10 +1198,11 @@ trace_info (args, from_tty) for (i = 0; i < trace_data.size; ++i) { - printf_filtered ("%d: %d instruction%s at 0x%x\n", - i, trace_data.counts[i], + printf_filtered ("%d: %d instruction%s at 0x%s\n", + i, + trace_data.counts[i], (trace_data.counts[i] == 1 ? "" : "s"), - trace_data.addrs[i]); + paddr_nz (trace_data.addrs[i])); } } else @@ -803,39 +1211,20 @@ trace_info (args, from_tty) printf_filtered ("Tracing is currently %s.\n", (tracing ? "on" : "off")); } -/* Print the instruction at address MEMADDR in debugged memory, - on STREAM. Returns length of the instruction, in bytes. */ - -static int -print_insn (memaddr, stream) - CORE_ADDR memaddr; - GDB_FILE *stream; -{ - /* If there's no disassembler, something is very wrong. */ - if (tm_print_insn == NULL) - abort (); - - if (TARGET_BYTE_ORDER == BIG_ENDIAN) - tm_print_insn_info.endian = BFD_ENDIAN_BIG; - else - tm_print_insn_info.endian = BFD_ENDIAN_LITTLE; - return (*tm_print_insn) (memaddr, &tm_print_insn_info); -} - -void -d10v_eva_prepare_to_trace () +static void +d10v_eva_prepare_to_trace (void) { if (!tracing) return; - last_pc = read_register (PC_REGNUM); + last_pc = read_register (D10V_PC_REGNUM); } /* Collect trace data from the target board and format it into a form more useful for display. */ -void -d10v_eva_get_trace_data () +static void +d10v_eva_get_trace_data (void) { int count, i, j, oldsize; int trace_addr, trace_seg, trace_cnt, next_cnt; @@ -845,7 +1234,7 @@ d10v_eva_get_trace_data () if (!tracing) return; - tmpspace = xmalloc (65536 * sizeof(unsigned int)); + tmpspace = xmalloc (65536 * sizeof (unsigned int)); last_trace = read_memory_unsigned_integer (DBBC_ADDR, 2) << 2; @@ -888,42 +1277,43 @@ d10v_eva_get_trace_data () oldsize = trace_data.size; trace_data.size += count; - free (tmpspace); + xfree (tmpspace); if (trace_display) display_trace (oldsize, trace_data.size); } static void -tdisassemble_command (arg, from_tty) - char *arg; - int from_tty; +tdisassemble_command (char *arg, int from_tty) { int i, count; CORE_ADDR low, high; - char *space_index; if (!arg) { low = 0; high = trace_data.size; } - else if (!(space_index = (char *) strchr (arg, ' '))) - { - low = parse_and_eval_address (arg); - high = low + 5; - } else - { - /* Two arguments. */ - *space_index = '\0'; - low = parse_and_eval_address (arg); - high = parse_and_eval_address (space_index + 1); - if (high < low) - high = low; + { + char *space_index = strchr (arg, ' '); + if (space_index == NULL) + { + low = parse_and_eval_address (arg); + high = low + 5; + } + else + { + /* Two arguments. */ + *space_index = '\0'; + low = parse_and_eval_address (arg); + high = parse_and_eval_address (space_index + 1); + if (high < low) + high = low; + } } - printf_filtered ("Dump of trace from %d to %d:\n", low, high); + printf_filtered ("Dump of trace from %s to %s:\n", paddr_u (low), paddr_u (high)); display_trace (low, high); @@ -932,14 +1322,13 @@ tdisassemble_command (arg, from_tty) } static void -display_trace (low, high) - int low, high; +display_trace (int low, int high) { int i, count, trace_show_source, first, suppress; CORE_ADDR next_address; trace_show_source = default_trace_show_source; - if (!have_full_symbols () && !have_partial_symbols()) + if (!have_full_symbols () && !have_partial_symbols ()) { trace_show_source = 0; printf_filtered ("No symbol table is loaded. Use the \"file\" command.\n"); @@ -951,7 +1340,7 @@ display_trace (low, high) for (i = low; i < high; ++i) { next_address = trace_data.addrs[i]; - count = trace_data.counts[i]; + count = trace_data.counts[i]; while (count-- > 0) { QUIT; @@ -973,7 +1362,7 @@ display_trace (low, high) if (!suppress) /* FIXME-32x64--assumes sal.pc fits in long. */ printf_filtered ("No source file for address %s.\n", - local_hex_string((unsigned long) sal.pc)); + local_hex_string ((unsigned long) sal.pc)); suppress = 1; } } @@ -982,47 +1371,272 @@ display_trace (low, high) printf_filtered (":"); printf_filtered ("\t"); wrap_here (" "); - next_address = next_address + print_insn (next_address, gdb_stdout); + next_address += gdb_print_insn (next_address, gdb_stdout); printf_filtered ("\n"); gdb_flush (gdb_stdout); } } } -extern void (*target_resume_hook) PARAMS ((void)); -extern void (*target_wait_loop_hook) PARAMS ((void)); +static CORE_ADDR +d10v_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) +{ + ULONGEST pc; + frame_unwind_unsigned_register (next_frame, D10V_PC_REGNUM, &pc); + return d10v_make_iaddr (pc); +} + +/* Given a GDB frame, determine the address of the calling function's + frame. This will be used to create a new GDB frame struct. */ + +static void +d10v_frame_this_id (struct frame_info *next_frame, + void **this_prologue_cache, + struct frame_id *this_id) +{ + struct d10v_unwind_cache *info + = d10v_frame_unwind_cache (next_frame, this_prologue_cache); + CORE_ADDR base; + CORE_ADDR func; + struct frame_id id; + + /* The FUNC is easy. */ + func = frame_func_unwind (next_frame); + + /* This is meant to halt the backtrace at "_start". Make sure we + don't halt it at a generic dummy frame. */ + if (func <= IMEM_START || inside_entry_file (func)) + return; + + /* Hopefully the prologue analysis either correctly determined the + frame's base (which is the SP from the previous frame), or set + that base to "NULL". */ + base = info->prev_sp; + if (base == STACK_START || base == 0) + return; + + id = frame_id_build (base, func); + + /* Check that we're not going round in circles with the same frame + ID (but avoid applying the test to sentinel frames which do go + round in circles). Can't use frame_id_eq() as that doesn't yet + compare the frame's PC value. */ + if (frame_relative_level (next_frame) >= 0 + && get_frame_type (next_frame) != DUMMY_FRAME + && frame_id_eq (get_frame_id (next_frame), id)) + return; + + (*this_id) = id; +} + +static void +d10v_frame_prev_register (struct frame_info *next_frame, + void **this_prologue_cache, + int regnum, int *optimizedp, + enum lval_type *lvalp, CORE_ADDR *addrp, + int *realnump, void *bufferp) +{ + struct d10v_unwind_cache *info + = d10v_frame_unwind_cache (next_frame, this_prologue_cache); + trad_frame_prev_register (next_frame, info->saved_regs, regnum, + optimizedp, lvalp, addrp, realnump, bufferp); +} + +static const struct frame_unwind d10v_frame_unwind = { + NORMAL_FRAME, + d10v_frame_this_id, + d10v_frame_prev_register +}; + +static const struct frame_unwind * +d10v_frame_p (CORE_ADDR pc) +{ + return &d10v_frame_unwind; +} + +static CORE_ADDR +d10v_frame_base_address (struct frame_info *next_frame, void **this_cache) +{ + struct d10v_unwind_cache *info + = d10v_frame_unwind_cache (next_frame, this_cache); + return info->base; +} + +static const struct frame_base d10v_frame_base = { + &d10v_frame_unwind, + d10v_frame_base_address, + d10v_frame_base_address, + d10v_frame_base_address +}; + +/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that + dummy frame. The frame ID's base needs to match the TOS value + saved by save_dummy_frame_tos(), and the PC match the dummy frame's + breakpoint. */ + +static struct frame_id +d10v_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) +{ + return frame_id_build (d10v_unwind_sp (gdbarch, next_frame), + frame_pc_unwind (next_frame)); +} + +static gdbarch_init_ftype d10v_gdbarch_init; + +static struct gdbarch * +d10v_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) +{ + struct gdbarch *gdbarch; + int d10v_num_regs; + struct gdbarch_tdep *tdep; + gdbarch_register_name_ftype *d10v_register_name; + gdbarch_register_sim_regno_ftype *d10v_register_sim_regno; + + /* Find a candidate among the list of pre-declared architectures. */ + arches = gdbarch_list_lookup_by_info (arches, &info); + if (arches != NULL) + return arches->gdbarch; + + /* None found, create a new architecture from the information + provided. */ + tdep = XMALLOC (struct gdbarch_tdep); + gdbarch = gdbarch_alloc (&info, tdep); + + switch (info.bfd_arch_info->mach) + { + case bfd_mach_d10v_ts2: + d10v_num_regs = 37; + d10v_register_name = d10v_ts2_register_name; + d10v_register_sim_regno = d10v_ts2_register_sim_regno; + tdep->a0_regnum = TS2_A0_REGNUM; + tdep->nr_dmap_regs = TS2_NR_DMAP_REGS; + tdep->dmap_register = d10v_ts2_dmap_register; + tdep->imap_register = d10v_ts2_imap_register; + break; + default: + case bfd_mach_d10v_ts3: + d10v_num_regs = 42; + d10v_register_name = d10v_ts3_register_name; + d10v_register_sim_regno = d10v_ts3_register_sim_regno; + tdep->a0_regnum = TS3_A0_REGNUM; + tdep->nr_dmap_regs = TS3_NR_DMAP_REGS; + tdep->dmap_register = d10v_ts3_dmap_register; + tdep->imap_register = d10v_ts3_imap_register; + break; + } + + set_gdbarch_read_pc (gdbarch, d10v_read_pc); + set_gdbarch_write_pc (gdbarch, d10v_write_pc); + set_gdbarch_unwind_sp (gdbarch, d10v_unwind_sp); + + set_gdbarch_num_regs (gdbarch, d10v_num_regs); + set_gdbarch_sp_regnum (gdbarch, D10V_SP_REGNUM); + set_gdbarch_register_name (gdbarch, d10v_register_name); + set_gdbarch_register_type (gdbarch, d10v_register_type); + + set_gdbarch_ptr_bit (gdbarch, 2 * TARGET_CHAR_BIT); + set_gdbarch_addr_bit (gdbarch, 32); + set_gdbarch_address_to_pointer (gdbarch, d10v_address_to_pointer); + set_gdbarch_pointer_to_address (gdbarch, d10v_pointer_to_address); + set_gdbarch_integer_to_address (gdbarch, d10v_integer_to_address); + set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); + set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); + set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT); + set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); + /* NOTE: The d10v as a 32 bit ``float'' and ``double''. ``long + double'' is 64 bits. */ + set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); + set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT); + set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); + switch (info.byte_order) + { + case BFD_ENDIAN_BIG: + set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_big); + set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_big); + set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_big); + break; + case BFD_ENDIAN_LITTLE: + set_gdbarch_float_format (gdbarch, &floatformat_ieee_single_little); + set_gdbarch_double_format (gdbarch, &floatformat_ieee_single_little); + set_gdbarch_long_double_format (gdbarch, &floatformat_ieee_double_little); + break; + default: + internal_error (__FILE__, __LINE__, + "d10v_gdbarch_init: bad byte order for float format"); + } + + set_gdbarch_extract_return_value (gdbarch, d10v_extract_return_value); + set_gdbarch_push_dummy_code (gdbarch, d10v_push_dummy_code); + set_gdbarch_push_dummy_call (gdbarch, d10v_push_dummy_call); + set_gdbarch_store_return_value (gdbarch, d10v_store_return_value); + set_gdbarch_extract_struct_value_address (gdbarch, d10v_extract_struct_value_address); + set_gdbarch_use_struct_convention (gdbarch, d10v_use_struct_convention); + + set_gdbarch_skip_prologue (gdbarch, d10v_skip_prologue); + set_gdbarch_inner_than (gdbarch, core_addr_lessthan); + set_gdbarch_decr_pc_after_break (gdbarch, 4); + set_gdbarch_function_start_offset (gdbarch, 0); + set_gdbarch_breakpoint_from_pc (gdbarch, d10v_breakpoint_from_pc); + + set_gdbarch_remote_translate_xfer_address (gdbarch, remote_d10v_translate_xfer_address); + + set_gdbarch_frame_args_skip (gdbarch, 0); + set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue); + + set_gdbarch_frame_align (gdbarch, d10v_frame_align); + + set_gdbarch_register_sim_regno (gdbarch, d10v_register_sim_regno); + + set_gdbarch_print_registers_info (gdbarch, d10v_print_registers_info); + + frame_unwind_append_predicate (gdbarch, d10v_frame_p); + frame_base_set_default (gdbarch, &d10v_frame_base); + + /* Methods for saving / extracting a dummy frame's ID. The ID's + stack address must match the SP value returned by + PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ + set_gdbarch_unwind_dummy_id (gdbarch, d10v_unwind_dummy_id); + + /* Return the unwound PC value. */ + set_gdbarch_unwind_pc (gdbarch, d10v_unwind_pc); + + set_gdbarch_print_insn (gdbarch, print_insn_d10v); + + return gdbarch; +} void -_initialize_d10v_tdep () +_initialize_d10v_tdep (void) { - tm_print_insn = print_insn_d10v; + register_gdbarch_init (bfd_arch_d10v, d10v_gdbarch_init); target_resume_hook = d10v_eva_prepare_to_trace; target_wait_loop_hook = d10v_eva_get_trace_data; - add_com ("regs", class_vars, show_regs, "Print all registers"); + deprecate_cmd (add_com ("regs", class_vars, show_regs, "Print all registers"), + "info registers"); - add_com ("trace", class_support, trace_command, + add_com ("itrace", class_support, trace_command, "Enable tracing of instruction execution."); - add_com ("untrace", class_support, untrace_command, + add_com ("iuntrace", class_support, untrace_command, "Disable tracing of instruction execution."); - add_com ("tdisassemble", class_vars, tdisassemble_command, + add_com ("itdisassemble", class_vars, tdisassemble_command, "Disassemble the trace buffer.\n\ Two optional arguments specify a range of trace buffer entries\n\ as reported by info trace (NOT addresses!)."); - add_info ("trace", trace_info, + add_info ("itrace", trace_info, "Display info about the trace data buffer."); - add_show_from_set (add_set_cmd ("tracedisplay", no_class, - var_integer, (char *)&trace_display, - "Set automatic display of trace.\n", &setlist), - &showlist); - add_show_from_set (add_set_cmd ("tracesource", no_class, - var_integer, (char *)&default_trace_show_source, - "Set display of source code with trace.\n", &setlist), - &showlist); - -} + add_setshow_boolean_cmd ("itracedisplay", no_class, &trace_display, + "Set automatic display of trace.\n", + "Show automatic display of trace.\n", + NULL, NULL, &setlist, &showlist); + add_setshow_boolean_cmd ("itracesource", no_class, + &default_trace_show_source, + "Set display of source code with trace.\n", + "Show display of source code with trace.\n", + NULL, NULL, &setlist, &showlist); +}